CN117766606A - Photoelectric detector, preparation method thereof and photoelectric communication device - Google Patents
Photoelectric detector, preparation method thereof and photoelectric communication device Download PDFInfo
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Abstract
The application discloses a photoelectric detector and a preparation method thereof and a photoelectric communication device, wherein the photoelectric detector comprises a substrate and a photoelectric conversion part, the substrate is provided with two sides in a first direction, the photoelectric conversion part is arranged on one side of the substrate, the photoelectric conversion part comprises an intrinsic body, the intrinsic body is provided with a middle area in a second direction and two side parts positioned at two sides of the middle area, and the two side parts of the intrinsic body are correspondingly embedded with N-type doped ions and P-type doped ions so as to correspondingly form an N-type semiconductor layer and a P-type semiconductor layer; wherein the first direction and the second direction are arranged in an intersecting manner. The N-type doping and the P-type doping are both generated in the intrinsic layer, the deposition of polysilicon for ohmic contact is avoided, and meanwhile, the L-type doping can ensure the uniformity of an internal electric field in the intrinsic layer, so that the device is ensured to have higher bandwidth.
Description
Technical Field
The present disclosure relates to the field of optical and electrical technologies, and in particular, to a photodetector, a method for manufacturing the same, and a photoelectric communication device.
Background
At present, two main methods for improving the photoelectric bandwidth of the waveguide integrated Ge/Si pin photoelectric detector exist, one is an inductive gain peak (inductive-gain peak) technology, and the method is only suitable for the situation that the bandwidth of the pin photoelectric detector is mainly limited by RC time, namely the charge-discharge time constant of a parasitic capacitance-resistance network of a semiconductor device; another is to increase the bandwidth of the pin photodetector, also known as ultra-thin intrinsic region technology, by narrowing the width or thickness of the intrinsic light absorption region, which theoretically allows bandwidths greater than 200GHz to be achieved, but typically results in very low light responsivity due to the intrinsic light absorption region narrowing. The existing pin photoelectric detector with ultra-high bandwidth of 265GHz has lower device light response, only 0.3A/W, and the device preparation process is more complex: the intrinsic layer is etched, polysilicon is deposited on the surface of the intrinsic layer to form electrical contact, and impurities are diffused to the intrinsic layer due to the doping of the polysilicon, so that the internal electric field of the intrinsic layer is further influenced, and the working efficiency of the device is influenced.
Content of the application
The main purpose of the application is to provide a photoelectric detector, a preparation method thereof and a photoelectric communication device, and aims to simplify the preparation process of the photoelectric detector, reduce the influence of impurities on the diffusion of an intrinsic layer in the doping of polysilicon, improve the uniformity of an internal electric field of the intrinsic layer and improve the bandwidth of a device.
To achieve the above object, the present application proposes a photodetector comprising:
a substrate having two sides in a first direction; and
the photoelectric conversion part is arranged on one side of the substrate and comprises an intrinsic body, the intrinsic body is provided with a middle area in the second direction and two side parts positioned on two sides of the middle area, and N-type doped ions and P-type doped ions are correspondingly embedded in the two side parts of the intrinsic body so as to correspondingly form an N-type semiconductor layer and a P-type semiconductor layer;
wherein the first direction and the second direction are arranged in an intersecting manner.
Alternatively, the process may be carried out in a single-stage,
the size of the middle region of the intrinsic body in the first direction is 20-80 nm; and/or the number of the groups of groups,
the size of the middle region of the intrinsic body in the second direction is 100-200 nm; and/or the number of the groups of groups,
the size of the middle region of the intrinsic body in the third direction is 10-50 mu m; and/or the number of the groups of groups,
the material of the N-type semiconductor layer comprises an N-type semiconductor layer formed by doping phosphorus or arsenic atoms in Ge, or an N-type semiconductor layer formed by doping tellurium or tin or silicon atoms in InGaAs, or an N-type semiconductor layer formed by doping tellurium or tin or silicon atoms in InGaAsP; and/or the number of the groups of groups,
The material of the P-type semiconductor layer comprises a P-type semiconductor layer formed by doping boron atoms in Ge, or a P-type semiconductor layer formed by doping zinc atoms in InGaAs, or a P-type semiconductor layer formed by doping zinc atoms in InGaAsP;
wherein the third direction intersects the first direction and the second direction, respectively.
Optionally, each of the side portions includes a side body extending in a first direction, and a side protrusion extending outwardly from an end of the side body adjacent the substrate;
the side body and the side convex part of one side are embedded with N-type doped ions, so that the N-type semiconductor layer is L-shaped;
the side body and the side convex part of the other side are embedded with P-type doped ions, so that the P-type semiconductor layer is arranged in an L-type mode.
Optionally, the side body of the N-type semiconductor layer has a dimension in the second direction of 1 to 3 μm;
the dimension of the side convex part of the N-type semiconductor layer in the first direction is 20-80 nm;
the dimension of the N-type semiconductor layer in the third direction is 10-50 mu m;
the side body of the P-type semiconductor layer has a dimension in the second direction of 1-3 μm;
The dimension of the side convex part of the second P-type semiconductor layer in the first direction is 20-80 nm;
the dimension of the P-type semiconductor layer in the third direction is 10-50 mu m;
wherein the third direction intersects the first direction and the second direction, respectively.
Optionally, the material of the intrinsic body includes at least one of Ge, inGaAs, and InGaAsP.
Optionally, the substrate includes:
a substrate silicon layer;
a buried silicon dioxide layer located on one side of the substrate silicon layer; and
a top silicon layer, which is positioned at one side of the buried silicon dioxide layer away from the substrate silicon layer, and part of the substrate silicon layer, the buried silicon dioxide layer and the top silicon layer form an optical coupling region and a waveguide region;
the optical coupling area comprises any one of a grating and an end surface coupler;
the waveguide region includes an optical waveguide and a silicon taper, the optical waveguide being located between the silicon taper and the optical coupling region.
Optionally, the silicon taper includes a first silicon taper and a second silicon taper and an etch stop layer taper disposed between the first silicon taper and the second silicon taper, wherein:
the first silicon taper comprises a monocrystalline silicon taper;
the second silicon taper comprises any one of a polysilicon taper and an amorphous silicon taper.
The invention also provides a preparation method of the photoelectric detector, which comprises the following steps:
s10, providing a substrate;
s20, forming a photoelectric conversion part on a first side of a substrate, wherein the photoelectric conversion part comprises an intrinsic body, the intrinsic body is provided with a middle area in a second direction and two side parts positioned at two sides of the middle area, and N-type doped ions and P-type doped ions are correspondingly embedded in the two side parts of the intrinsic body so as to correspondingly form an N-type semiconductor layer and a P-type semiconductor layer;
wherein the first direction and the second direction are arranged in an intersecting manner.
Optionally, step S20 includes:
s210, forming an intrinsic body on one side of a substrate;
s220, etching a concave part on a first side of the intrinsic layer body in a second direction, wherein the concave part is correspondingly arranged through one end of the intrinsic part, which is opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
s230, implanting ions which enable the intrinsic layer to form first type doping into the side body and the side protruding part to form a first type semiconductor layer;
s240, etching a concave part on a second side of the intrinsic layer body in a second direction, wherein the concave part is correspondingly arranged through one end of the intrinsic part, which is opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
S250, implanting ions which enable the intrinsic layer to form second type doping into the side body and the side protruding part to form a second type semiconductor layer;
wherein one of the first type doped ions and the second type doped ions is an N type doped ion, and the other is a P type doped ion;
one of the first type semiconductor layer and the second type semiconductor layer is an N type semiconductor layer, and the other is a P type semiconductor layer.
Optionally, step S10 includes:
s110, providing a wafer containing a top silicon layer;
s120, depositing an etching barrier layer on the surface of the top silicon layer of the wafer;
s130, depositing a polysilicon layer on one side of the etching barrier layer away from the top silicon layer;
and S140, etching a polysilicon cone on the polysilicon-containing layer, and etching a grating, a waveguide and a monocrystalline silicon cone on the top silicon layer.
Optionally, the material of the etching barrier layer includes at least one of silicon dioxide, silicon nitride or silicon oxynitride.
Optionally, step S210 includes:
s2101, etching a ridge waveguide on a substrate;
s2102, forming a silicon dioxide film layer on the surface of the first side of the substrate;
s2103, etching a silicon dioxide film layer and part of the ridge waveguide in the middle of the ridge waveguide to form a concave part;
And S2104, growing the Ge layer in the concave part by a heteroepitaxy method to obtain the substrate containing the intrinsic layer.
Optionally, the heteroepitaxy method includes at least one of a reduced pressure chemical vapor deposition method, an ultra-high vacuum chemical vapor deposition method, and a molecular beam epitaxy method.
Alternatively, the process may be carried out in a single-stage,
step S220 includes:
s221, coating photoresist on the surface of the whole wafer, exposing and developing the surface of the second side in the second direction by utilizing a photoetching plate, and etching a concave part on the second side, wherein the concave part is correspondingly arranged at one end, opposite to the substrate, of the intrinsic part, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end, close to the substrate, of the side part main body;
step S240 includes: removing photoresist on the surface of the whole wafer, recoating the photoresist on the surface of the whole wafer, exposing and developing the surface photoresist on the first side by using a photoetching plate, and etching a concave part on the first side, wherein the concave part is correspondingly arranged at one end of the intrinsic part opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body close to the substrate.
Optionally, the thickness of the photoresist in the first direction is 1 to 5 μm.
The angle of the first type ion implantation of the side convex part of the first type semiconductor layer is 7-10 degrees;
the energy of the first type ion implantation of the side convex part of the first type semiconductor layer is 40-80 KeV;
the angle of the second type ion implantation of the side convex part of the second type semiconductor layer is 7-10 degrees;
the energy of the second type ion implantation of the side convex part of the second type semiconductor layer is 40-80 KeV.
The invention also provides a photoelectric communication device which comprises the photoelectric detector or the photoelectric detector prepared by the preparation method of the photoelectric detector.
Optionally, the optical-electrical communication device includes any one of an optical receiver in an optical module used in optical fiber communication and data center and an optical receiving unit in a high-speed optoelectronic integrated chip.
The intrinsic body is provided with a middle region in the second direction and two side parts positioned at two sides of the middle region, and N-type doped ions and P-type doped ions are correspondingly embedded at the two side parts of the intrinsic body so as to correspondingly form an N-type semiconductor layer and a P-type semiconductor layer, so that the N-type doping and the P-type doping occur in the intrinsic layer, the deposition of polysilicon for ohmic contact is avoided, meanwhile, the uniformity of an internal electric field in the intrinsic layer can be ensured by the L-type doping, and the device is ensured to have higher bandwidth.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from the structures shown in these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic view of a photodetector according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for fabricating a photodetector according to an embodiment of the present application;
FIG. 3 is a flowchart of a method for fabricating a photodetector according to yet another embodiment of the present application;
fig. 4 is a schematic structural diagram of a process of forming a photodetector in a method for manufacturing a photodetector according to an embodiment of the application.
Reference numerals illustrate:
100 photodetectors; 1 a substrate; 11 a substrate silicon layer; 12 a buried silicon dioxide layer; a 14 optical coupling region; 141 grating; 15 waveguide regions; 151 optical waveguides; 152 silicon cone; 1521 a first silicon cone; 1522 a second silicon cone; 1523 etching the barrier cone; 2 a photoelectric conversion unit; a 21 eigenbody; 211 side; 212 middle region; 213N-type semiconductor layer; 214P-type semiconductor layer; 2111 side body; 2112 side protrusions.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention. In addition, the meaning of "and/or" as it appears throughout includes three parallel schemes, for example "A and/or B", including the A scheme, or the B scheme, or the scheme where A and B are satisfied simultaneously. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
At present, two main methods for improving the photoelectric bandwidth of the waveguide integrated Ge/Si pin photoelectric detector exist, one is an inductive gain peak (inductive-gain peak) technology, and the method is only suitable for the situation that the bandwidth of the pin photoelectric detector is limited by RC time, namely the charge-discharge time constant of a parasitic capacitance-resistance network of a semiconductor device; another is to increase the bandwidth of the pin photodetector, also known as ultra-thin intrinsic region technology, by narrowing the width or thickness of the intrinsic light absorption region, which can achieve a bandwidth theoretically greater than 200GHz, but typically results in a very low light responsivity due to the intrinsic light absorption region narrowing. The existing pin photoelectric detector with ultra-high bandwidth of 265GHz has lower device light response, only 0.3A/W, and the device preparation process is more complex: the Ge etching is needed, polysilicon is deposited on the surface of the Ge so as to form electrical contact, and impurities are diffused to the Ge layer due to the doping of the polysilicon, so that the internal electric field of the Ge layer is further influenced, and the working efficiency of the device is influenced.
In view of this, as shown in fig. 1, the present application proposes a photodetector including:
a substrate 1 having both sides in a first direction; and
a photoelectric conversion portion 2 disposed on one side of the substrate 1, the photoelectric conversion portion 2 including an intrinsic body 21, the intrinsic body 21 having a middle region 212 in a second direction and two side portions 211 located on both sides of the middle region 212, the two side portions 211 of the intrinsic body 21 being correspondingly embedded with N-type doped ions and P-type doped ions to correspondingly form an N-type semiconductor layer 213 and a P-type semiconductor layer 214;
wherein the first direction and the second direction are arranged in an intersecting manner.
In the technical solution of the present invention, the intrinsic body 21 has the middle region 212 in the second direction and two side portions 211 located at two sides of the middle region 212, and the two side portions 211 of the intrinsic body 21 are correspondingly embedded with N-type doped ions and P-type doped ions to correspondingly form the N-type semiconductor layer 213 and the P-type semiconductor layer 214, so that both N-type doping and P-type doping occur in the intrinsic layer, thereby avoiding the deposition of polysilicon for ohmic contact, and meanwhile, the L-type doping can ensure the uniformity of the electric field inside the intrinsic layer, so as to ensure that the device has a higher bandwidth.
It should be noted that N-type doping means that the doped impurity atoms and the semiconductor material atoms still have excessive electrons to participate in conduction after forming a stable 8-electron structure by sharing the outermost electron, P-type doping means that the doped impurity atoms and the semiconductor material atoms form a stable 8-electron structure by sharing the outermost electron and acquiring 1 electron from the adjacent atoms while leaving a vacancy at the adjacent atom position, that is, having excessive holes to participate in conduction, and when the materials of the intrinsic layers are different, the doped ions are also different.
In any embodiment of the present invention, the size of the intermediate region 212 of the intrinsic body 21 in the first direction is 20 to 80nm, and the intermediate region 212 of the intrinsic body 21 having a suitable thickness can be obtained.
In any embodiment of the present invention, the size of the middle region 212 of the intrinsic body 21 in the second direction is 100-200 nm, which can shorten the thickness of the middle region 212 of the intrinsic body 21 in the second direction, reduce the distance between electron and hole transport, and further improve the bandwidth of the photodetector.
In any embodiment of the present invention, the middle region 212 of the intrinsic body 21 has a dimension in the third direction of 10-50 μm, because the length of the intrinsic body 21 is positively correlated with the junction capacitance of the detector, which in turn is negatively correlated with the junction capacitance. The dimension of the intermediate region 212 of the eigenbody 21 in the third direction is within this range to ensure a suitable responsivity of the detector without a reduction in bandwidth due to the eigenbody 21 being too long. As shown in fig. 4a, wherein the third direction intersects the first direction and the second direction, respectively.
The material of the N-type semiconductor layer 213 includes an N-type semiconductor layer formed by doping phosphorus or arsenic atoms in Ge, or an N-type semiconductor layer formed by doping tellurium or tin or silicon atoms in InGaAs, or an N-type semiconductor layer formed by doping tellurium or tin or silicon atoms in InGaAsP.
The material of the P-type semiconductor layer 214 includes a P-type semiconductor layer formed by doping boron atoms in Ge, or a P-type semiconductor layer formed by doping zinc atoms in InGaAs, or a P-type semiconductor layer formed by doping zinc atoms in InGaAsP.
The dimensions of the intermediate region 212 of the intrinsic body 21 in the first direction, the second direction, and the third direction, the selection of the N-type semiconductor layer 213, and the selection of the P-type semiconductor layer 214 may be set simultaneously or separately, and the detection efficiency of the photodetector is better when the two layers are set simultaneously.
In any embodiment of the present invention, each of the side portions 211 includes a side body 2111 extending in a first direction, and a side protrusion 2112 extending outwardly from an end of the side body 2111 adjacent to the substrate 1; the side body 2111 and the side protrusion 2112 of one side 211 are embedded with N-type doped ions, so that the N-type semiconductor layer 213 is L-shaped; the side body 2111 and the side protrusion 2112 of the other side portion 211 are embedded with P-type doped ions, so that the P-type semiconductor layer 214 is in an L-type arrangement. By setting the N-type semiconductor layer 213 and the P-type semiconductor layer 214 to be L-shaped, uniformity of the electric field in the middle region 212 of the intrinsic body 21 can be improved, ensuring a high bandwidth of the photodetector.
In any embodiment of the present invention, the side body 2111 of the N-type semiconductor layer 213 has a dimension of 1 to 3 μm, preferably 1.5 μm in the second direction, and the side body 2111 of the N-type semiconductor layer 213 having a proper width can be obtained. The dimension of the side protrusions 2112 of the N-type semiconductor layer 213 in the first direction is 20 to 80nm, preferably 50nm, and the side protrusions 2112 of the N-type semiconductor layer 213 having a proper thickness can be obtained.
The side main body 2111 and the side protrusions 2112 of the N-type semiconductor layer 213 have a size of 10 to 50 μm in the third direction, and an N-type semiconductor layer of an appropriate length can be obtained.
The side body 2111 of the P-type semiconductor layer 214 has a dimension in the second direction of 1 to 3 μm, preferably 1.5 μm or more, and a side body 2111 of the P-type semiconductor layer 214 having a proper width can be obtained.
The dimension of the side protrusions 2112 of the second P-type semiconductor layer 214 in the first direction is 20 to 80nm, preferably 50nm, and the side protrusions 2112 of the P-type semiconductor layer 214 having a proper thickness can be obtained.
The side body 2111 and the side protrusion 2112 of the P-type semiconductor layer 214 have a dimension of 10 to 50 μm in the third direction, and a P-type semiconductor layer having a proper length can be obtained.
In any embodiment of the present invention, the material of the intrinsic body 21 includes at least one of Ge, inGaAs and InGaAsP, and the use of at least one of the above materials of the intrinsic body 21 can ensure that the detector has a high detection efficiency in the optical fiber communication wavelength range (1260 to 1625 nm).
In any embodiment of the present invention, the substrate 1 includes: a substrate silicon layer 11, a buried silicon dioxide layer 12 and a top silicon layer, the buried silicon dioxide layer 12 being located on one side of the substrate silicon layer 11; the top silicon layer is positioned on one side of the buried silicon dioxide layer 12 away from the substrate silicon layer 11, and part of the substrate silicon layer 11, the buried silicon dioxide layer 12 and the top silicon layer form an optical coupling region 14 and a waveguide region 15; the optical coupling region 14 includes any one of a grating 141 and an end-face coupler; the waveguide region 15 includes an optical waveguide 151 and a silicon taper 152, the optical waveguide 151 being located between the silicon taper 152 and the optical coupling region 14. When light in the optical fiber is coupled into the optical waveguide 151 through the grating 141 or the end face coupler and excites a single mode therein, and the single mode light of the waveguide is transmitted to the silicon cone 152, the optical wave mode field becomes larger gradually, and the reflection loss when the light enters the ridge waveguide from the single mode optical waveguide 151 can be reduced.
In any embodiment of the present invention, the silicon taper 152 includes a first silicon taper 1521 and a second silicon taper 1522 and an etch stop layer taper 1523 disposed between the first silicon taper 1521 and the second silicon taper 1522, wherein: the first silicon taper 1521 comprises a monocrystalline silicon taper 152; the second silicon taper 1522 includes any one of a polysilicon taper 152 and an amorphous silicon taper 152. When light is transmitted in the silicon cone 152, part of light energy in the silicon cone 152 enters the polysilicon cone 152 through evanescent coupling and propagates forwards because the polysilicon cone 152 and the silicon cone 152 are marked by an etching barrier layer; light energy propagating forward in the silicon cone 152 enters the light absorbing layer by means of evanescent coupling, and light energy propagating forward in the polysilicon cone 152 enters the light absorbing layer by means of butt coupling; compared with simple evanescent coupling, the introduction of the polysilicon taper 152 can improve the optical power absorbed by the light absorbing layer, thereby improving the optical responsivity to a certain extent. Light is absorbed in the light absorbing layer to excite electron-hole pairs, and under the action of an external electric field, the photo-generated electrons and holes respectively move to the n-type doped region and the p-type doped region and are collected by the cathode and the anode respectively, and current is formed in the external circuit.
It should be noted that the material and thickness of the etching barrier layer are not limited in the present invention, and the etching barrier layer may be a silicon dioxide layer, a silicon nitride layer or a silicon oxynitride layer, where the thickness of the etching barrier layer is generally about 10nm, and the specific thickness depends on the etching selection ratio of the etched material to the etching barrier layer.
As shown in fig. 2, the invention further provides a preparation method of the photoelectric detector, which comprises the following steps:
s10, providing a substrate 1;
s20, forming a photoelectric conversion portion 2 on a first side of a substrate 1, wherein the photoelectric conversion portion 2 includes an intrinsic body 21, the intrinsic body 21 has a middle region 212 located in a second direction and two side portions 211 located at two sides of the middle region 212, and the two side portions 211 of the intrinsic body 21 are correspondingly embedded with N-type doped ions and P-type doped ions so as to correspondingly form an N-type semiconductor layer 213 and a P-type semiconductor layer 214; wherein the first direction and the second direction are arranged in an intersecting manner.
The intrinsic body 21 is provided with the middle region 212 positioned in the second direction and the two side parts 211 positioned at two sides of the middle region 212, and the two side parts 211 of the intrinsic body 21 are correspondingly embedded with N-type doped ions and P-type doped ions so as to correspondingly form the N-type semiconductor layer 213 and the P-type semiconductor layer 214, so that the N-type doping and the P-type doping occur in the intrinsic layer, polysilicon deposition is not needed, the device preparation process is simplified, the device preparation cost is reduced, meanwhile, ions are prevented from penetrating into the intrinsic layer in the process of doping to form the N-type doping and the P-type doping in the polysilicon, and the middle region 212 with enough width is ensured to absorb incident photons so as to ensure that the detector has enough high detection efficiency.
As shown in fig. 3, in any embodiment of the present invention, step S20 includes:
s210, forming an intrinsic body 21 on one side of the substrate 1;
s220, etching a concave part on a first side of the intrinsic layer body in a second direction, wherein the concave part is correspondingly arranged through one end of the intrinsic part, which is opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
s230, implanting ions which enable the intrinsic layer to form first type doping into the side body and the side protruding part to form a first type semiconductor layer;
s240, etching a concave part on a second side of the intrinsic layer body in a second direction, wherein the concave part is correspondingly arranged through one end of the intrinsic part, which is opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
s250, implanting ions which enable the intrinsic layer to form second type doping into the side body and the side protruding part to form a second type semiconductor layer;
wherein one of the first type doped ions and the second type doped ions is an N type doped ion, and the other is a P type doped ion;
One of the first type semiconductor layer and the second type semiconductor layer is an N type semiconductor layer, and the other is a P type semiconductor layer.
By sequentially implanting different ions at both sides of the intrinsic layer to form the N-type doped semiconductor layer and the P-type semiconductor layer 214, a high-precision photolithography process can be avoided, and the manufacturing cost of the photodetector can be reduced.
As shown in fig. 3, in any embodiment of the present invention, step S10 includes:
s110, providing a wafer containing a top silicon layer; the waveguide integrated Ge/Si pin photodetector is usually fabricated using an SOI (Silicon-On-Insulator) wafer, which is typically composed of a bottom Silicon substrate 1, a middle buried Silicon dioxide layer 12, and a top Silicon layer On top, where the Silicon substrate 1 mainly serves as a mechanical support, the buried Silicon dioxide layer 12 serves as a lower cladding layer of the optical waveguide 151, and the top Silicon layer is a processing layer where the optoelectronic device is located. Currently, the main stream wafer size for processing silicon-based optoelectronic devices including waveguide integrated Ge/Si pin photodetectors is 8 inches; the typical specification is as follows: a 750 μm silicon substrate 1, a buried silicon dioxide layer 12 of about 2-3 μm, and a top silicon layer of about 220nm, wherein the top silicon layer is mostly high resistivity, i.e. low doping concentration, in order to avoid that impurities in the top silicon layer diffuse into the intrinsic layer, i.e. the intrinsic body, during the epitaxy process to affect the device performance.
S120, depositing an etching barrier layer on the surface of the top silicon layer of the wafer; an etching barrier layer is deposited on the surface of the whole wafer and used as an etching stop layer of polysilicon, and the top silicon layer is monocrystalline silicon and has similar chemical properties with the polysilicon material, so that the etching selectivity of the monocrystalline silicon and the polysilicon material is relatively low, and in the process of etching the polysilicon, in order to ensure that polysilicon in other areas except the polysilicon cone 152 is completely etched, and simultaneously avoid damaging the top silicon layer, the etching barrier layer needs to be deposited as the etching stop layer, and the thickness of the etching barrier layer depends on the thickness of the polysilicon and the etching selectivity ratio of the polysilicon and the etching barrier layer. Typically, the etch selectivity of polysilicon to etch stop layer is not less than 100. For dry etching processes, a certain time of over-etching is typically required to ensure that the etched film is completely etched. For example, etching polysilicon 200nm thick, assuming a constant etching rate of 20nm/min, theoretically requires an etching time of 10min (main etching time). However, in practice, there is a fluctuation in the thickness of the polysilicon film on the whole wafer, some positions are 200nm, some positions are 210nm, some positions are 195nm, and the etching rate is not constant, so that to ensure that the polysilicon film on each position of the wafer is completely etched, it is necessary to continue etching for a period of time (this process is also called overetching) after the theoretical etching time arrives, for example, 20% of the main etching time is 2min, during the overetching, the thickness of the theoretically etched polysilicon is 40nm, and if the etching selectivity of the polysilicon to the etching barrier layer at the bottom thereof is 100, the etched amount of the etching barrier layer at some positions on the wafer during the overetching is 40 nm/100=0.4 nm. The specific etch selectivity depends on the actual etch conditions and is dependent on a number of factors such as the pressure, temperature, plasma power of the etch chamber.
S130, depositing a polysilicon layer on one side of the etching barrier layer away from the top silicon layer;
and S140, etching a polysilicon cone 152 on the polysilicon-containing layer, and etching a grating 141, a waveguide and a monocrystalline silicon cone 152 on the top silicon layer. The polysilicon is etched completely in the areas other than the polysilicon cones 152 by photolithography, etching, etc. And etching part of the top silicon layer of the area where the grating 141 is positioned downwards by photoetching, etching and other technologies to form the grating 141 with a certain duty ratio and period. The top silicon layer in the specific region is etched down by photolithography, etching, etc. to form the core layer of the optical waveguide 151 and the silicon taper 152.
In any embodiment of the present invention, the material of the etching barrier layer includes at least one of silicon dioxide, silicon nitride and silicon oxynitride. By adopting at least one of the materials of the etching barrier layer, the polysilicon of other areas except the polysilicon cone can be completely etched without damaging the top silicon layer below the polysilicon cone.
In any embodiment of the present invention, step S210 includes:
s2101, etching a ridge waveguide on the substrate 1, and etching the top silicon layer in the specific area downwards by using technologies such as photoetching, etching and the like to form the ridge waveguide.
S2102, a silicon dioxide film layer is formed on the surface of the first side of the substrate 1, a silicon dioxide film with a certain thickness is deposited on the whole wafer surface, and then the wafer surface is polished by utilizing a CMP technology to form a flat surface so as to ensure that the subsequent photoetching process is smoothly carried out.
S2103, etching a silicon dioxide film layer and part of the ridge waveguide in the middle of the ridge waveguide to form a concave part, and carrying out photoetching, etching and other technologies to enable SiO in a specific area of the wafer surface 2 And completely removing the material, and defining a subsequent Ge selective epitaxial growth window, namely a concave part. The intrinsic layer such as Ge epitaxy takes the surface of the silicon layer of the SOI wafer dome layer as a growth template, is very sensitive to the surface roughness, and therefore damage to the surface of the silicon layer of the SOI wafer dome layer is avoided as much as possible in the process of forming an epitaxial growth window. To achieve the above object, siO is removed 2 Possible means of (a) include, but are not limited toIn the following steps: (1) employing only an optimized dry etching process; (2) Removing most of SiO by dry etching process 2 Then removing the residual thin SiO layer by wet etching process 2 And (3) a film.
It should be noted that in some embodiments of the present invention, the SiO in the epitaxial growth window may also be formed during the epitaxial growth window forming process 2 After all the silicon layers are etched, the top silicon layer with a certain thickness is removed through an etching process to form a groove with a certain depth, and the inner wall of the groove is smoothened through a process means including but not limited to sacrificial oxidation to meet the requirement of Ge epitaxy, so that the optical coupling mode of the photoelectric detector is changed from evanescent coupling to butt coupling, and the responsivity of the detector is improved.
And S2104, growing a Ge layer in the concave part by a heteroepitaxy method to obtain the substrate 1 containing the intrinsic layer. And growing Ge with a certain thickness in the treated epitaxial growth window through a heteroepitaxy process. In the Ge-selective epitaxial growth process, the thickness of the epitaxial Ge is typically greater than the depth of the defined epitaxial growth window, so CMP techniques are required to thin the Ge film to a specified thickness while planarizing the wafer surface. Most of the Ge in the specific region will be etched away by photolithography, etching, etc. while only a thinner layer remains, the thickness of the remaining Ge thin layer in the first direction is typically 50-100 nm.
In any embodiment of the invention, the heteroepitaxy process comprises at least one of reduced pressure chemical vapor deposition (RPCVD, reduced Pressure Chemical Vapor Deposition), ultra high vacuum chemical vapor deposition (UHVCVD, ultra-High Vacuum Chemical Vapor Deposition), and molecular beam epitaxy (MBE, molecule Beam Epitaxy).
In any of the embodiments of the present invention,
step S220 includes:
s221, coating photoresist on the whole wafer surface, exposing and developing the photoresist on the surface of the second side in the second direction by using a photoetching plate (also called a photomask), and etching a concave part on the second side, wherein the concave part is correspondingly arranged at one end of the intrinsic part, which is opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
step S240 includes: removing photoresist on the surface of the whole wafer, recoating the photoresist on the surface of the whole wafer, exposing and developing the photoresist on the surface of the first side by using a photoetching plate, and etching a concave part on the first side, wherein the concave part is correspondingly arranged through one end of the intrinsic part opposite to the substrate so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body close to the substrate.
The photoresist is used as an ion implantation mask to implant ions into the two concave parts which are arranged at intervals, so that alignment errors of alignment of the photoetching process before ion implantation in the traditional process can be avoided, the photoresist after the etching process is hardened to a certain extent, and the hardened photoresist is reused as a masking layer in the ion implantation process after ion implantation, so that the preparation cost of the device is reduced.
In any embodiment of the present invention, the thickness of the photoresist in the first direction is 1 to 5 μm. Within this thickness range, it can be ensured that a sufficient thickness of photoresist remains after the completion of the entire layer etching as an ion implantation masking layer in the subsequent ion implantation process.
In any embodiment of the present invention, the angle of the first type ion implantation of the side protrusions 2112 of the first type semiconductor layer is 7 to 10 °; the ion beam needs to be implanted at an angle to ensure that the Ge sidewalls can be ion implanted. Within this angle range, it is ensured that the N-type semiconductor side protruding portion can be doped uniformly.
The first type ion implantation of the side protrusions 2112 of the first type semiconductor layer has an energy of 40 to 80KeV, preferably 50KeV, in which an excellent ohmic electrical contact can be ensured to be formed later. Too low an ion implantation energy results in the vast majority of the ions implanted in a thin layer near the surface, which may be etched away during the over-etch phase of the dielectric (typically silicon dioxide) etch process required for subsequent contact hole formation, resulting in eventually failing to form an effective electrical contact.
The second type ion implantation angle of the side protrusions 2112 of the second type semiconductor layer is 7 to 10 °, and within this angle range, it is ensured that the N type semiconductor side protrusions can be uniformly doped.
The second type ion implantation of the side protrusions 2112 of the second type semiconductor layer has an energy of 40 to 80KeV, preferably 50KeV, and can be performed within this energy range to ensure good ohmic electrical contact to be formed later. Too low an ion implantation energy results in the vast majority of the ions implanted in a thin layer near the surface, which may be etched away during the over-etch phase of the dielectric (typically silicon dioxide) etch process required for subsequent contact hole formation, resulting in eventually failing to form an effective electrical contact.
After forming the N-type semiconductor layer 213 and the P-type semiconductor layer 214, a layer of SiO may be deposited on the side of the entire wafer remote from the substrate silicon layer 11 as shown in fig. 4 (a) to 4 (r) 2 The film is then planarized by CMP techniques on the wafer surface. To SiO in a specific area 2 And completely etching and exposing the n-type and p-type doped Ge at the bottom to form an electrical contact hole, then depositing tungsten metal on the surface of the whole wafer to fully fill the contact hole, and finally grinding all tungsten metal except the contact hole region by a CMP technology. A first metal layer is then deposited to a certain thickness on the side of the entire wafer surface remote from the substrate silicon layer 11, and then all metal except for the specific area is removed by photolithography, etching, etc. The first layer of metal can be any one of aluminum, aluminum silicon alloy and aluminum copper alloy, and multiple layers of metal wiring can exist according to the electrical wiring requirements in specific applications, and the performance of the photoelectric detector is less influenced by the multiple layers of metal wiring.
The invention also provides a photoelectric communication device which comprises the photoelectric detector or the photoelectric detector prepared by the preparation method of the photoelectric detector. The photoelectric communication device has all technical schemes of the photoelectric detector, so that the photoelectric communication device also has all beneficial effects of the photoelectric detector, and the photoelectric communication device is not described in detail herein.
In any embodiment of the present invention, the optical communication device includes any one of an optical receiver in an optical module used for optical fiber communication and data, and an optical receiving unit in a high-speed optoelectronic integrated chip.
Various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the scope of the patent protection of the present application.
Claims (18)
1. A photodetector, comprising:
a substrate having two sides in a first direction; and
the photoelectric conversion part is arranged on one side of the substrate and comprises an intrinsic body, the intrinsic body is provided with a middle area in the second direction and two side parts positioned on two sides of the middle area, and N-type doped ions and P-type doped ions are correspondingly embedded in the two side parts of the intrinsic body so as to correspondingly form an N-type semiconductor layer and a P-type semiconductor layer;
Wherein the first direction and the second direction are arranged in an intersecting manner.
2. The photodetector of claim 1 wherein the photodetector comprises a photodetector array,
the size of the middle region of the intrinsic body in the first direction is 20-80 nm; and/or the number of the groups of groups,
the size of the middle region of the intrinsic body in the second direction is 100-200 nm; and/or the number of the groups of groups,
the size of the middle region of the intrinsic body in the third direction is 10-50 mu m; and/or the number of the groups of groups,
the N-type semiconductor layer comprises an N-type semiconductor layer formed by doping phosphorus or arsenic atoms in Ge, or an N-type semiconductor layer formed by doping tellurium or tin or silicon atoms in InGaAs, or an N-type semiconductor layer formed by doping tellurium or tin or silicon atoms in InGaAsP; and/or the number of the groups of groups,
the material of the P-type semiconductor layer comprises a P-type semiconductor layer formed by doping boron atoms in Ge, or a P-type semiconductor layer formed by doping zinc atoms in InGaAs, or a P-type semiconductor layer formed by doping zinc atoms in InGaAsP;
wherein the third direction intersects the first direction and the second direction, respectively.
3. The photodetector of claim 1 wherein each of said side portions includes a side body extending in a first direction and a side tab extending outwardly from an end of said side body adjacent said substrate;
The side body and the side convex part of one side are embedded with N-type doped ions, so that the N-type semiconductor layer is L-shaped;
the side body and the side convex part of the other side are embedded with P-type doped ions, so that the P-type semiconductor layer is arranged in an L-type mode.
4. The photodetector of claim 3 wherein the detector comprises,
the side body of the N-type semiconductor layer has a dimension of 1-3 μm in the second direction;
the dimension of the side convex part of the N-type semiconductor layer in the first direction is 20-80 nm;
the side body and the side convex part of the N-type semiconductor layer have a size of 10-50 μm in the third direction;
the side body of the P-type semiconductor layer has a dimension in the second direction of 1-3 μm;
the dimension of the side convex part of the P-type semiconductor layer in the first direction is 20-80 nm;
the side body and the side convex part of the P-type semiconductor layer have a size of 10-50 μm in the third direction;
wherein the third direction intersects the first direction and the second direction, respectively.
5. The photodetector of claim 1 wherein the intrinsic body material comprises at least one of Ge, inGaAs, and InGaAsP.
6. The photodetector of claim 1 wherein said substrate comprises:
a substrate silicon layer;
a buried silicon dioxide layer located on one side of the substrate silicon layer; and
a top silicon layer, which is positioned at one side of the buried silicon dioxide layer away from the substrate silicon layer, and part of the substrate silicon layer, the buried silicon dioxide layer and the top silicon layer form an optical coupling region and a waveguide region;
the optical coupling area comprises any one of a grating and an end surface coupler;
the waveguide region includes an optical waveguide and a silicon taper, the optical waveguide being located between the silicon taper and the optical coupling region.
7. The photodetector of claim 6 wherein the silicon taper comprises a first silicon taper and a second silicon taper and an etch stop taper disposed between the first silicon taper and the second silicon taper, wherein:
the first silicon taper comprises a monocrystalline silicon taper;
the second silicon taper comprises any one of a polysilicon taper and an amorphous silicon taper.
8. A method of manufacturing a photodetector according to any one of claims 1 to 7, comprising the steps of:
s10, providing a substrate;
s20, forming a photoelectric conversion part on a first side of a substrate, wherein the photoelectric conversion part comprises an intrinsic body, the intrinsic body is provided with a middle area in a second direction and two side parts positioned at two sides of the middle area, and N-type doped ions and P-type doped ions are correspondingly embedded in the two side parts of the intrinsic body so as to correspondingly form an N-type semiconductor layer and a P-type semiconductor layer;
Wherein the first direction and the second direction are arranged in an intersecting manner.
9. The method of manufacturing a photodetector of claim 8, wherein step S20 comprises:
s210, forming an intrinsic body on one side of a substrate;
s220, etching a concave part on a first side of the intrinsic layer body in a second direction, wherein the concave part is correspondingly arranged through one end of the intrinsic part, which is opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
s230, implanting ions which enable the intrinsic layer to form first type doping into the side body and the side protruding part to form a first type semiconductor layer;
s240, etching a concave part on a second side of the intrinsic layer body in a second direction, wherein the concave part is correspondingly arranged through one end of the intrinsic part, which is opposite to the substrate, so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
s250, implanting ions which enable the intrinsic layer to form second type doping into the side body and the side protruding part to form a second type semiconductor layer;
Wherein one of the first type doped ions and the second type doped ions is an N type doped ion, and the other is a P type doped ion;
one of the first type semiconductor layer and the second type semiconductor layer is an N type semiconductor layer, and the other is a P type semiconductor layer.
10. The method of manufacturing a photodetector of claim 8, wherein step S10 comprises:
s110, providing a wafer containing a top silicon layer;
s120, depositing an etching barrier layer on the surface of the top silicon layer of the wafer;
s130, depositing a polysilicon layer on one side of the etching barrier layer away from the top silicon layer;
and S140, etching a polysilicon cone on the polysilicon-containing layer, and etching a grating, a waveguide and a monocrystalline silicon cone on the top silicon layer.
11. The method of claim 10, wherein the material of the etch stop layer comprises at least one of silicon dioxide, silicon nitride, or silicon oxynitride.
12. The method of manufacturing a photodetector of claim 9, wherein step S210 comprises:
s2101, etching a ridge waveguide on a substrate;
s2102, forming a silicon dioxide film layer on the surface of the first side of the substrate;
S2103, etching a silicon dioxide film layer and part of the ridge waveguide in the middle of the ridge waveguide to form a concave part;
and S2104, growing the Ge layer in the concave part by a heteroepitaxy method to obtain the substrate containing the intrinsic layer.
13. The method of claim 12, wherein the heteroepitaxy process comprises at least one of reduced pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, and molecular beam epitaxy.
14. The method of manufacturing a photodetector of claim 9, wherein step S220 comprises:
s221, coating photoresist on the whole wafer surface, exposing and developing the photoresist on the surface of the second side in the second direction by utilizing a photoetching plate, and etching a concave part on the second side, wherein the concave part is correspondingly arranged at one end of the intrinsic part, which is opposite to the substrate, and correspondingly penetrates through the intrinsic part, so that a side part is correspondingly formed by the concave part, and comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body, which is close to the substrate;
step S240 includes: removing photoresist on the surface of the whole wafer, recoating the photoresist on the surface of the whole wafer, exposing and developing the photoresist on the surface of the first side by using a photoetching plate, and etching a concave part on the first side, wherein the concave part is correspondingly arranged through one end of the intrinsic part opposite to the substrate so that the concave part correspondingly forms a side part, and the side part comprises a side part main body extending along the first direction and a side convex part extending outwards from one end of the side part main body close to the substrate.
15. The method of manufacturing a photodetector of claim 14, wherein said photoresist has a thickness in the first direction of 1 to 5 μm.
16. A method of fabricating a photodetector as defined in claim 9, wherein,
the angle of the first type ion implantation of the side convex part of the first type semiconductor layer is 7-10 degrees;
the energy of the first type ion implantation of the side convex part of the first type semiconductor layer is 40-80 KeV;
the angle of the second type ion implantation of the side convex part of the second type semiconductor layer is 7-10 degrees;
the energy of the second type ion implantation of the side convex part of the second type semiconductor layer is 40-80 KeV.
17. A photoelectric communication device comprising a photodetector according to any one of claims 1 to 7 or a photodetector produced by the method of producing a photodetector according to any one of claims 8 to 16.
18. The optoelectronic communications device of claim 17, wherein the optoelectronic communications device comprises any one of an optical receiver in an optical module used in fiber optic communications and data centers, and an optical receiving unit in a high-speed optoelectronic integrated chip.
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