CN117766561A - P-channel gallium nitride heterojunction transistor and preparation method thereof - Google Patents
P-channel gallium nitride heterojunction transistor and preparation method thereof Download PDFInfo
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- CN117766561A CN117766561A CN202310526901.3A CN202310526901A CN117766561A CN 117766561 A CN117766561 A CN 117766561A CN 202310526901 A CN202310526901 A CN 202310526901A CN 117766561 A CN117766561 A CN 117766561A
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 5
- 229910002601 GaN Inorganic materials 0.000 title abstract description 47
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 12
- 230000010287 polarization Effects 0.000 claims abstract description 8
- 238000003780 insertion Methods 0.000 claims description 26
- 230000037431 insertion Effects 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 20
- 230000000694 effects Effects 0.000 claims description 11
- 229910002704 AlGaN Inorganic materials 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 230000001939 inductive effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000004047 hole gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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Abstract
The invention discloses a p-channel gallium nitride heterojunction transistor and a preparation method thereof, wherein the transistor comprises a substrate, and a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier inserting layer and a p-channel layer which are sequentially laminated on the substrate, wherein a grid electrode, a source electrode and a drain electrode are positioned on the p-channel layer, the forbidden band width of the barrier inserting layer is larger than that of the hole providing layer and the p-channel layer, so that the barrier inserting layer can depress the energy band of the hole providing layer to enable holes in the layer to be completely ionized, and the completely ionized holes are transferred into the top p-channel layer, and the top p-channel layer acts as a p-type conducting channel, thereby increasing the carrier density and further realizing the increase of the current density. The invention can realize the enhanced device by controlling the etching depth, and can realize relatively high current density by inducing the complete ionization of bottom holes by the polarization of the barrier insert layer.
Description
Technical Field
The invention relates to a GaN device, in particular to a potential barrier insert layer p-channel heterojunction transistor, and belongs to the field of power electronic devices.
Background
Due to the characteristics of high breakdown field strength, high electron saturation velocity, high heterojunction mobility and the like of the GaN material, the microwave power device based on the wide band gap GaN semiconductor material is expected to break through the limitation of Si-based devices, and becomes a candidate of a next-generation power conversion system.
GaN devices can be classified into n-type and p-type according to the conductivity type of carriers, n-type devices are mainly electron-conductive, and p-type devices are mainly hole-conductive. Due to the advantages of high two-dimensional electron gas (2 DEG) density and high electron mobility, gaN High Electron Mobility Transistors (HEMTs) are suitable for high power and high frequency applications, and with the development of technology, gaN HEMT devices have been increasingly commercialized. The rapid development of n-channel based power switching devices has stimulated the development of p-channel based GaN transistors. Implementing complementary n-channel and p-channel GaN transistors can reduce the design complexity and static power consumption of the power integrated circuit. As a key element in Complementary Metal Oxide Semiconductor (CMOS) structures, we greatly expect that p-channel GaN transistors can have current densities comparable to n-channel devices on the basis of achieving enhancement. For the enhancement type realization of p-channel transistors, trench gate technology has become the mainstream gradually, namely, the p-type GaN under the gate is partially etched, so that the depletion region under the gate fills the channel under zero gate voltage, and enhancement type is realized. However, as the etching depth increases, on-resistance under the gate electrode greatly increases, and at the same time, plasma in the etching process damages the p-type GaN surface of the etched portion, thereby reducing the mobility of surface carriers.
Guowang Li et al, university of Santa Clay in 2013, utilized a method of GaN/AlN epitaxial layer polarization induced two-dimensional hole gas (2 DHG) to increase carrier density and mobility, and achieved a current density of 100mA/mm [1]. However, this epitaxial layer does not provide an n-channel, which in turn has an impact on the complementary integration of n-type and p-type GaN transistors.
Zheyang Zheng et al, university of hong kong, proposed the OPT technique in 2020, and performed the OPT process [2] on the basis of retaining more p-type GaN under the gate, i.e., oxygen treatment and high temperature annealing of the surface, aiming at realizing an enhanced operation mode on the basis of low on-resistance, but this did not fundamentally solve the problem of low current density and increased the complexity of the process.
The Nadim Chordhury et al, the university of Massa, 2022, reduced the on-resistance of the device by gate scaling and increased the current density of the device, however, as the gate length was reduced, the drain-induced barrier lowering effect of the device became significant and the device fabricated in this operation was in depletion mode [3].
Reference is made to:
[1]G.Li et al.,“Polarization-Induced GaN-on-Insulator E/D Mode p-Channel Heterostructure FETs,”IEEE Electron Device Lett.,vol.34,no.7,pp.852–854.
[2]Z.Zheng,W.Song,L.Zhang,S.Yang,J.Wei,and K.J.Chen,“High I ON and I ON /I off Ratio Enhancement-Mode Buried p-Channel GaN MOSFETs on p-GaN Gate Power HEMT Platform,”
IEEE Electron Device Lett.,vol.41,no.1,pp.26–29.
[3]N.Chowdhury,Q.Xie,and T.Palacios,“Tungsten-Gated GaN/AlGaN p-FET With I max>120mA/mm on GaN-on-Si,”IEEE Electron Device Lett.,vol.43,no.4,pp.545–548.
disclosure of Invention
The invention aims to provide a novel p-channel GaN device structure which is used for solving the problems of small on-current and large on-resistance of a device. According to the device structure provided by the invention, while enhancement is realized, a barrier layer is inserted into the p-type GaN at the top to transfer holes in the p-type GaN below the barrier layer into the p-type GaN above the barrier layer, and due to a strong polarization effect, the holes in the p-type GaN below the barrier layer are completely ionized above the barrier insertion layer, so that the carrier density is increased, and the current density is increased.
Specifically, the technical scheme of the invention is as follows:
a p-channel GaN heterojunction transistor comprises a substrate, and a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier inserting layer and a p-channel layer which are sequentially laminated on the substrate, wherein a grid electrode, a source electrode and a drain electrode are positioned on the p-channel layer, and the forbidden band width of the barrier inserting layer is larger than that of the hole providing layer and the p-channel layer.
Further, the p-channel GaN heterojunction transistor may employ a MIS gate structure or a schottky gate structure. In the MIS gate structure, a gate dielectric layer is arranged between the gate and the p-channel layer.
In the above p-channel GaN heterojunction transistor, the substrate may be a Si substrate, a sapphire substrate, a GaN substrate, or the like.
The n-channel layer can be an epitaxial layer such as a GaN layer and an InGaN layer which can generate polarization effect with the barrier layer, and has smaller forbidden band width relative to the barrier layer; the barrier layer may be an epitaxial layer such as AlGaN, alN, alInGaN which can generate polarization effect with the n-channel layer, and has a larger forbidden bandwidth than the n-channel layer.
The hole providing layer may be an epitaxial layer which is doped with Mg or C and can provide holes, such as a p-type GaN layer and an InGaN layer, and has a small forbidden band width relative to the barrier insertion layer; the barrier insertion layer may be a barrier layer of AlGaN, alN, alInGaN or the like having a large forbidden bandwidth with respect to the hole providing layer; the p-channel layer may be an Mg or C doped p-type GaN layer, inGaN layer, or the like epitaxial layer that can provide holes with a small band gap relative to the barrier insertion layer. The hole providing layer/barrier insertion layer/p-channel layer has various combinations with each other, such as combinations of various epitaxial layers of p-GaN/AlN/p-GaN, p-GaN/AlGaN/p-InGaN, p-InGaN/AlN/p-GaN, etc.
The gate dielectric layer may be Al 2 O 3 、SiO 2 、HfO 2 And a dielectric layer.
The invention also provides a preparation method of the p-channel GaN heterojunction transistor, which comprises the following steps:
1) Sequentially epitaxially growing a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier insertion layer and a p-channel layer on a substrate;
2) Etching a grid electrode concave region on the p-channel layer by utilizing a photoetching process;
3) Epitaxially growing a gate dielectric layer and then preparing a source drain electrode, or directly preparing the source drain electrode on the p-channel layer;
4) A gate electrode is fabricated on the gate dielectric layer or directly on the p-channel layer.
In summary, the key point of the present invention is that the forbidden band width of the barrier insertion layer is larger than the forbidden band widths of the hole providing layer and the p-channel layer, so that the barrier insertion layer will depress the energy band of the hole providing layer to fully ionize the holes in the layer, and the top p-channel layer acts as a p-type conduction channel. The top p-channel layer is not limited to a single epitaxial layer material, but may be a combination of other conductive materials of different doping, composition, etc. In addition, the variation of parameters such as the length, thickness, doping concentration, electrode type and the like of each region is the scope of the invention, which depends on different design requirements and manufacturing processes. It is noted that the present invention focuses on the insertion of the barrier insertion layer, so that the hole concentration at the interface on the barrier insertion layer is increased, and the device is enabled to achieve an enhanced operation mode by controlling the etching depth of the gate region or by other gate processing methods, and of course, the present invention proposes to increase the conductivity through the barrier insertion layer is equally applicable to depletion mode devices (generally, the etching depth of the depletion mode device is shallower than that under the gate of the enhanced device). It is to be understood that other structural and other examples of changes may be made without departing from the scope of the invention. Moreover, different examples, structures and processes may be combined with each other to achieve the same purpose.
The invention has the beneficial effects that:
the prior art can achieve an enhanced working mode by controlling the etching depth or the gate post-treatment process, but the problems of low carrier mobility, large on-resistance and the like of a channel region are not solved effectively. Therefore, the invention provides a structure that holes in the lower hole providing layer are fully ionized through the insertion of the barrier insertion layer, and the fully ionized holes in the bottom layer are transferred to the upper interface of the barrier insertion layer by virtue of polarization effect, because the surface carrier mobility is lower due to the damage of the GaN surface caused by etching, and a channel inserted by the barrier insertion layer is positioned at the bottom, so that the problem of low channel carrier mobility is precisely avoided. For the above reasons, the current density of the device prepared by the invention is higher than that of other devices. In summary, the invention can realize enhancement by controlling the etching depth, and can realize relatively high current density by inducing complete ionization of bottom holes by polarization of the barrier insertion layer.
Drawings
Fig. 1 is a two-dimensional cross-sectional view of a MIS gate p-channel GaN device with a barrier insertion layer prepared in example 1 of the present invention.
Fig. 2 is a two-dimensional cross-sectional view of a schottky gate p-channel GaN device with a barrier insert layer prepared in example 2 of the present invention.
Fig. 3 is a diagram showing the effect of step 1 completion of examples 1 and 2.
Fig. 4 is a diagram showing the effect of step 2 completion of examples 1 and 2.
Fig. 5 is a diagram showing the effect of step 3 in example 1.
Fig. 6 is a diagram showing the effect of step 3 in example 2.
Fig. 7 is a graph comparing the current densities of the device (a) prepared in example 1 and the device (b) without the barrier interposed layer.
Detailed Description
The invention will be described in further detail by way of examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1 preparation of MIS Gate p-channel GaN device
1. A substrate 1 is selected, on which a buffer layer 2, an n-channel layer 3, a barrier layer 4, a hole providing layer 5, a barrier insertion layer 6, and a top p-channel layer 7 are epitaxially grown in this order, as shown in fig. 3;
the substrate 1 is a Si substrate, and a GaN buffer layer, an n-channel layer i-GaN, a barrier layer AlGaN, a hole providing layer p-GaN, a barrier inserting layer AlN and a p-channel layer p-GaN are sequentially grown by adopting an epitaxial growth method;
2. etching a grid recessed region in the p-GaN of the p-channel layer by using a photoetching process, as shown in fig. 4;
3. epitaxially growing a gate dielectric layer SiO 2 Then, manufacturing source and drain Ni/Au by photoetching and stripping processes and performing an annealing process, as shown in FIG. 5;
4. and manufacturing grid Ti/Au by using photoetching and stripping processes to obtain the MIS grid p-channel GaN device shown in figure 1.
The effect of the barrier insertion layer structure on the current density is shown in fig. 7, in which (a) shows the device with the barrier insertion layer structure fabricated in this example, and (b) shows the device without the AlN insertion layer structure, compared with the device with the conventional structure. The introduction of the barrier insertion layer may increase the p-FET current density by at least a factor of two for devices of the same size.
Example 2 preparation of Schottky Gate p-channel GaN device
1. A substrate 1 is selected, on which a buffer layer 2, an n-channel layer 3, a barrier layer 4, a hole providing layer 5, a barrier insertion layer 6, and a top p-channel layer 7 are epitaxially grown in this order, as shown in fig. 3;
the substrate 1 is a Si substrate, and a GaN buffer layer, an n-channel layer i-GaN, a barrier layer AlGaN, a hole providing layer p-GaN, a barrier inserting layer AlN and a p-channel layer p-GaN are sequentially grown by adopting an epitaxial growth method;
2. etching a grid recessed region in the p-GaN of the p-channel layer by using a photoetching process, as shown in fig. 4;
3. epitaxially growing a gate dielectric layer SiO 2 Then, manufacturing source and drain Ni/Au by photoetching and stripping processes and performing an annealing process, as shown in FIG. 6;
4. and manufacturing grid Ti/Au by using photoetching and stripping processes to obtain the Schottky grid p-channel GaN device shown in figure 2.
Claims (9)
1. A p-channel GaN heterojunction transistor comprises a substrate, and a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier inserting layer and a p-channel layer which are sequentially laminated on the substrate, wherein a grid electrode, a source electrode and a drain electrode are positioned on the p-channel layer, and the forbidden band width of the barrier inserting layer is larger than that of the hole providing layer and the p-channel layer.
2. The p-channel GaN heterojunction transistor of claim 1, wherein the p-channel GaN heterojunction transistor employs a MIS gate structure or a schottky gate structure.
3. The p-channel GaN heterojunction transistor of claim 1, wherein the substrate is a Si substrate, a sapphire substrate, or a GaN substrate.
4. The p-channel GaN heterojunction transistor of claim 1, wherein the n-channel layer is GaN or InGaN and the barrier layer is AlGaN, alN or AlInGaN, with a polarization effect between the two, wherein the barrier layer has a large forbidden band width relative to the n-channel layer.
5. The p-channel GaN heterojunction transistor of claim 1, wherein the hole-providing layer is Mg-or C-doped p-type GaN or InGaN; the barrier insert layer is AlGaN, alN or AlInGaN; the p-channel layer is Mg or C doped p-type GaN or InGaN.
6. The p-channel GaN heterojunction transistor of claim 1, wherein the material of the hole providing layer/barrier insertion layer/p-channel layer is selected from one of the following combinations: p-GaN/AlN/p-GaN, p-GaN/AlGaN/p-InGaN, p-InGaN/AlN/p-GaN.
7. The p-channel GaN heterojunction transistor of claim 1, wherein the p-channel GaN heterojunction transistor adopts an MIS gate structure, a gate dielectric layer is arranged between the gate and the p-channel layer, and the gate dielectric layer is Al 2 O 3 、SiO 2 Or HfO 2 。
8. The p-channel GaN heterojunction transistor of claim 1, wherein the p-channel GaN heterojunction transistor is an enhancement-mode or depletion-mode device.
9. The method for manufacturing a p-channel GaN heterojunction transistor as claimed in any one of claims 1 to 8, comprising the steps of:
1) Sequentially epitaxially growing a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier insertion layer and a p-channel layer on a substrate;
2) Etching a grid electrode concave region on the p-channel layer by utilizing a photoetching process;
3) Epitaxially growing a gate dielectric layer and then preparing a source drain electrode, or directly preparing the source drain electrode on the p-channel layer;
4) A gate electrode is fabricated on the gate dielectric layer or directly on the p-channel layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118553765A (en) * | 2024-07-31 | 2024-08-27 | 西交利物浦大学 | Semiconductor device and preparation method thereof |
| CN118630013A (en) * | 2024-08-12 | 2024-09-10 | 西交利物浦大学 | Semiconductor device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118553765A (en) * | 2024-07-31 | 2024-08-27 | 西交利物浦大学 | Semiconductor device and preparation method thereof |
| CN118630013A (en) * | 2024-08-12 | 2024-09-10 | 西交利物浦大学 | Semiconductor device and preparation method thereof |
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