CN117766561A - P-channel gallium nitride heterojunction transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a p-channel gallium nitride heterojunction transistor and a preparation method thereof, wherein the transistor comprises a substrate, and a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier inserting layer and a p-channel layer which are sequentially laminated on the substrate, wherein a grid electrode, a source electrode and a drain electrode are positioned on the p-channel layer, the forbidden band width of the barrier inserting layer is larger than that of the hole providing layer and the p-channel layer, so that the barrier inserting layer can depress the energy band of the hole providing layer to enable holes in the layer to be completely ionized, and the completely ionized holes are transferred into the top p-channel layer, and the top p-channel layer acts as a p-type conducting channel, thereby increasing the carrier density and further realizing the increase of the current density. The invention can realize the enhanced device by controlling the etching depth, and can realize relatively high current density by inducing the complete ionization of bottom holes by the polarization of the barrier insert layer.

Description

A p-channel gallium nitride heterojunction transistor and its preparation method

Technical field

The invention relates to GaN devices, in particular to a barrier insertion layer p-channel heterojunction transistor, and belongs to the field of power electronic devices.

Background technique

Due to the characteristics of GaN material itself such as high breakdown field strength, high electron saturation velocity and high heterojunction mobility, microwave power devices based on wide bandgap GaN semiconductor materials are expected to break through the limitations of Si-based devices and become the next generation of power conversion system candidate.

According to the conductivity type of carriers, GaN devices can be divided into two types: n-type and p-type. N-type devices are mainly conductive by electrons, and p-type devices are mainly conductive by holes. Due to the advantages of high density and high electron mobility of two-dimensional electron gas (2DEG), GaN high electron mobility transistor (HEMT) is suitable for high power and high frequency applications, and with the development of technology, GaNHEMT devices have gradually been commercialized. The rapid development of n-channel-based power switching devices has stimulated the development of p-channel-based GaN transistors. Implementing complementary n-channel and p-channel GaN transistors can reduce design complexity and static power consumption of power integrated circuits. As a key element in the complementary metal oxide semiconductor (CMOS) structure, we very much expect that p-channel GaN transistors can have a current density comparable to n-channel devices based on the realization of enhancement mode. For the realization of enhancement mode of p-channel transistors, trench gate technology has gradually become mainstream, that is, the p-type GaN under the gate is partially etched so that the depletion region under the gate fills the channel under zero gate voltage. And then achieve enhanced. However, as the etching depth increases, the on-resistance under the gate will greatly increase. At the same time, the plasma during the etching process will cause damage to the p-type GaN surface of the etched part, thereby reducing the surface current carrying capacity. Mobility of electrons. In addition, due to the high activation energy of Mg doped in typical p-type GaN, the impurities have incomplete ionization characteristics. These factors greatly reduce the current of p-channel GaN transistors to a certain extent. density.

In 2013, Guowang Li and others from the University of Notre Dame used the method of polarization-induced two-dimensional hole gas (2DHG) in the GaN/AlN epitaxial layer to increase carrier density and mobility, and achieved a current density of 100mA/mm[1] . However, this epitaxial layer does not provide an n-channel, thereby affecting the complementary integration of n-type and p-type GaN transistors.

Zheyang Zheng and others from the Hong Kong University of Science and Technology proposed OPT technology in 2020. On the basis of retaining more p-type GaN under the gate, the OPT process [2] was performed, that is, oxygen treatment and high-temperature annealing were performed on the surface, aiming to On the basis of achieving low on-resistance, it also has an enhanced operating mode. However, this does not fundamentally solve the problem of low current density and increases the complexity of the process.

In 2022, Nadim Chowdhury and others from the Massachusetts Institute of Technology used gate scaling to reduce the on-resistance of the device and thereby increase the current density of the device. However, as the gate length continues to decrease, the drain-induced barrier lowering effect of the device will change. The results are significant, and the device produced in this work is a depletion mode operating mode [3].

references:

[1]G.Li et al., "Polarization-Induced GaN-on-Insulator E/D Mode p-Channel Heterostructure FETs," IEEE Electron Device Lett., vol.34, no.7, pp.852–854.

[2]Z.Zheng, W.Song, L.Zhang, S.Yang, J.Wei, and KJChen, “High I _ON and I _ON /I _off Ratio Enhancement-Mode Buried p-Channel GaN MOSFETs on p-GaN Gate PowerHEMT Platform,”

IEEE Electron Device Lett., vol.41, no.1, pp.26–29.

[3] N.Chowdhury, Q.Xie, and T.Palacios, "Tungsten-Gated GaN/AlGaN p-FETWith I max>120mA/mm on GaN-on-Si," IEEE Electron Device Lett., vol.43, no.4, pp.545–548.

Contents of the invention

The purpose of the present invention is to propose a new p-channel GaN device structure to solve the problems of low device conduction current and high conduction resistance. While realizing enhancement mode, the device structure proposed by the present invention inserts a barrier layer into the top p-type GaN to transfer the holes in the p-type GaN below it to the p-type GaN above it, and because Due to the strong polarization effect, the holes in the lower p-type GaN are completely ionized to the top of the barrier insertion layer, increasing the carrier density, thus achieving an increase in current density.

Specifically, the technical solutions of the present invention are as follows:

A p-channel GaN heterojunction transistor, including a substrate and a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier insertion layer and a p-channel layer stacked sequentially on the substrate, and a gate electrode , the source electrode and the drain electrode are located on the p-channel layer, wherein the bandgap width of the barrier insertion layer is larger than the bandgap width of the hole providing layer and the p-channel layer.

Furthermore, the above-mentioned p-channel GaN heterojunction transistor can adopt an MIS gate structure or a Schottky gate structure. In the MIS gate structure, there is a gate dielectric layer between the gate electrode and the p-channel layer.

In the above p-channel GaN heterojunction transistor, the substrate may be a Si substrate, a sapphire substrate, a GaN substrate, etc.

The n-channel layer may be a GaN layer, an InGaN layer, or other epitaxial layer that can produce a polarization effect with the barrier layer, which has a smaller bandgap width than the barrier layer; the barrier layer may be AlGaN, AlN, Epitaxial layers such as AlInGaN that can produce polarization effects with the n-channel layer have a larger bandgap than the n-channel layer.

The hole providing layer may be a Mg- or C-doped p-type GaN layer, an InGaN layer, or other epitaxial layer that can provide holes, and its bandgap width is smaller than that of the barrier insertion layer; the barrier insertion layer may be AlGaN , AlN, AlInGaN and other materials barrier layer, which has a larger band gap than the hole providing layer; the p channel layer can be a Mg or C-doped p-type GaN layer, InGaN layer, etc., which can provide the epitaxy of holes layer, whose bandgap width is smaller than that of the barrier insertion layer. The hole providing layer/barrier insertion layer/p channel layer has various combinations, such as p-GaN/AlN/p-GaN, p-GaN/AlGaN/p-InGaN, p-InGaN/AlN/ The mutual combination of various epitaxial layers such as p-GaN.

The above-mentioned gate dielectric layer may be a dielectric layer such as Al ₂ O ₃ , SiO ₂ , HfO ₂ or the like.

The present invention also provides a method for preparing the above-mentioned p-channel GaN heterojunction transistor, which includes the following steps:

1) Epitaxially grow a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier insertion layer and a p-channel layer on the substrate in sequence;

2) Use photolithography process to etch the gate recessed area on the p-channel layer;

3) Epitaxially grow the gate dielectric layer and then prepare the source and drain electrodes, or directly prepare the source and drain electrodes on the p-channel layer;

4) Prepare the gate electrode on the gate dielectric layer, or directly prepare the gate electrode on the p-channel layer.

In short, the key point of the present invention is that the bandgap width of the barrier insertion layer is larger than the bandgap width of the hole providing layer and the p-channel layer. In this way, the barrier insertion layer will suppress the energy bandgap of the hole providing layer. Then the holes in this layer are completely ionized, and the top p-channel layer acts as a p-type conductive channel. Here, the top p-channel layer is not limited to a single epitaxial layer material, and can also be a combination of other conductive materials with different doping, composition, etc. In addition, changes in parameters such as the length, thickness, doping concentration, and electrode type of each region are within the scope of the present invention, which depends on different design requirements and preparation processes. It is worth noting that the focus of the present invention lies in the insertion of the barrier insertion layer, which increases the hole concentration at the interface on the barrier insertion layer, and controls the etching depth of the gate region or other gate processing methods to enable the device to achieve Enhancement mode working mode, of course, the method of inserting a barrier layer to improve conductivity proposed by the present invention is also applicable to depletion mode working mode devices (generally, depletion mode devices have a shallower etching depth below the gate than enhancement mode devices). ). It is understood that other structures and other modified examples are possible without departing from the scope of the present invention. Furthermore, different examples, structures and processes can be combined with each other to achieve the same purpose.

Beneficial effects of the present invention:

The existing technology can already achieve enhanced working mode by controlling the etching depth or gate post-processing process, but problems such as low carrier mobility in the channel region and high on-resistance have not been effectively solved. To this end, the present invention proposes a structure in which the holes in the hole providing layer below are all ionized through the insertion of the barrier insertion layer, and the fully ionized holes in the bottom layer are transferred to the barrier insertion layer by means of the polarization effect. At the interface above the layer, etching will cause damage to the GaN surface, resulting in low surface carrier mobility. However, the channel after the barrier insertion layer is inserted is located at the bottom, which avoids the problem of low channel carrier mobility. . Based on the above reasons, the current density of the device prepared by the present invention is higher than that of other devices. In short, the present invention can not only achieve enhancement mode by controlling the etching depth, but also can achieve relatively high current density by inducing complete ionization of bottom holes through barrier insertion layer polarization.

Description of the drawings

Figure 1 is a two-dimensional cross-sectional view of a MIS gate p-channel GaN device with a barrier insertion layer prepared in Embodiment 1 of the present invention.

Figure 2 is a two-dimensional cross-sectional view of a Schottky gate p-channel GaN device with a barrier insertion layer prepared in Embodiment 2 of the present invention.

Figure 3 is a diagram showing the completion effect of step 1 in Embodiments 1 and 2.

Figure 4 is a diagram showing the completion effect of step 2 in Embodiments 1 and 2.

Figure 5 is a diagram showing the completion effect of step 3 of Embodiment 1.

Figure 6 is a diagram of the completion effect of step 3 in Embodiment 2.

Figure 7 is a current density comparison diagram of the device (a) prepared in Example 1 and the device (b) without barrier insertion layer.

Detailed ways

The present invention will be further described in detail through examples below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

Example 1. Preparation of MIS gate p-channel GaN device

1. Select substrate 1, and sequentially epitaxially grow buffer layer 2, n-channel layer 3, barrier layer 4, hole providing layer 5, barrier insertion layer 6 and top p-channel layer 7, as shown in Figure 3 shown;

Among them, the substrate 1 is a Si substrate, and the epitaxial growth method is used to sequentially grow a GaN buffer layer, an n-channel layer i-GaN, a barrier layer AlGaN, a hole providing layer p-GaN, a barrier insertion layer AlN, and a p-channel layer. Channel layer p-GaN;

2. Use the photolithography process to etch the gate recessed area in the p-GaN layer of the p-channel layer, as shown in Figure 4;

3. Epitaxially grow the gate dielectric layer SiO ₂ , then use photolithography and stripping processes to make the source and drain Ni/Au and perform an annealing process, as shown in Figure 5;

4. Use photolithography and lift-off processes to make the gate Ti/Au to obtain the MIS gate p-channel GaN device as shown in Figure 1.

Comparing the device prepared by the above method with the traditional structural device, the influence of the barrier insertion layer structure on the current density is shown in Figure 7, in which (a) shows the device with the barrier insertion layer structure produced in this embodiment, (b) ) shows a traditional device without an AlN insertion layer structure. For devices of the same size, the introduction of the barrier insertion layer can at least double the p-FET current density.

Example 2. Preparation of Schottky gate p-channel GaN device

1. Select substrate 1, and sequentially epitaxially grow buffer layer 2, n-channel layer 3, barrier layer 4, hole providing layer 5, barrier insertion layer 6 and top p-channel layer 7, as shown in Figure 3 shown;

Among them, the substrate 1 is a Si substrate, and the epitaxial growth method is used to sequentially grow a GaN buffer layer, an n-channel layer i-GaN, a barrier layer AlGaN, a hole providing layer p-GaN, a barrier insertion layer AlN, and a p-channel layer. Channel layer p-GaN;

2. Use the photolithography process to etch the gate recessed area in the p-GaN layer of the p-channel layer, as shown in Figure 4;

3. Epitaxially grow the gate dielectric layer SiO ₂ , then use photolithography and stripping processes to make the source and drain Ni/Au and perform an annealing process, as shown in Figure 6;

4. Use photolithography and lift-off processes to make the gate Ti/Au to obtain the Schottky gate p-channel GaN device as shown in Figure 2.

Claims (9)

1. A p-channel GaN heterojunction transistor, including a substrate and a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier insertion layer and a p-channel layer stacked sequentially on the substrate, The gate electrode, the source electrode and the drain electrode are located on the p-channel layer, wherein the bandgap width of the barrier insertion layer is large relative to the bandgap widths of the hole providing layer and the p-channel layer. 2. The p-channel GaN heterojunction transistor according to claim 1, wherein the p-channel GaN heterojunction transistor adopts a MIS gate structure or a Schottky gate structure. 3. The p-channel GaN heterojunction transistor according to claim 1, wherein the substrate is a Si substrate, a sapphire substrate or a GaN substrate. 4. The p-channel GaN heterojunction transistor according to claim 1, wherein the n-channel layer is GaN or InGaN, and the barrier layer is AlGaN, AlN or AlInGaN, and there is a gap between the two. Polarization effect, in which the barrier layer has a larger bandgap than the n-channel layer. 5. The p-channel GaN heterojunction transistor according to claim 1, wherein the hole providing layer is Mg- or C-doped p-type GaN or InGaN; the barrier insertion layer is AlGaN, AIN Or AlInGaN; the p-channel layer is Mg- or C-doped p-type GaN or InGaN. 6. The p-channel GaN heterojunction transistor according to claim 1, wherein the material of the hole providing layer/barrier insertion layer/p-channel layer is selected from one of the following combinations: p-GaN/AlN/p-GaN, p-GaN/AlGaN/p-InGaN, p-InGaN/AlN/p-GaN. 7. The p-channel GaN heterojunction transistor according to claim 1, characterized in that the p-channel GaN heterojunction transistor adopts a MIS gate structure, and a gate dielectric is between the gate electrode and the p-channel layer. layer, and the gate dielectric layer is Al ₂ O ₃ , SiO ₂ or HfO ₂ . 8. The p-channel GaN heterojunction transistor according to claim 1, wherein the p-channel GaN heterojunction transistor is an enhancement mode or a depletion mode device. 9. The method for preparing a p-channel GaN heterojunction transistor according to any one of claims 1 to 8, comprising the following steps: 1) Epitaxially grow a buffer layer, an n-channel layer, a barrier layer, a hole providing layer, a barrier insertion layer and a p-channel layer on the substrate in sequence; 2) Use photolithography process to etch the gate recessed area on the p-channel layer; 3) Epitaxially grow the gate dielectric layer and then prepare the source and drain electrodes, or directly prepare the source and drain electrodes on the p-channel layer; 4) Prepare the gate electrode on the gate dielectric layer, or directly prepare the gate electrode on the p-channel layer.