CN117730407A

CN117730407A - Semiconductor device with asymmetric integrated lumped gate resistors for balancing on/off behavior and/or multiple spaced apart lumped gate resistors for improved power handling

Info

Publication number: CN117730407A
Application number: CN202280051016.8A
Authority: CN
Inventors: 池寅焕; 朴宰亨; E·R·范布伦特; E·乌格尔; 柳世衡
Original assignee: Wofu Semiconductor Co ltd
Current assignee: Wofu Semiconductor Co ltd
Priority date: 2021-07-22
Filing date: 2022-07-11
Publication date: 2024-03-19

Abstract

A power semiconductor device (50) includes a wide bandgap semiconductor layer structure, a gate pad (52) on the wide bandgap semiconductor layer structure, a plurality of gate fingers (66) on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors (72, 82) electrically coupled between the gate pad and the gate fingers.

Description

Semiconductor device with asymmetric integrated lumped gate resistors for balancing on/off behavior and/or multiple spaced apart lumped gate resistors for improved power handling

Cross Reference to Related Applications

The present application claims priority from U.S. patent application Ser. No.17/382,407, filed on 22 at 7 at 2021, and U.S. patent application Ser. No.17/843,010, filed on 6 at 2022, each of which is incorporated by reference in its entirety as if fully set forth herein.

Technical Field

The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having lumped gate resistors.

Background

A variety of power semiconductor devices are known in the art including, for example, power metal oxide semiconductor field effect transistors ("MOSFETs"), insulated gate bipolar transistors ("IGBTs"), and various other devices. These power semiconductor devices are often made of a wide bandgap semiconductor material, such as silicon carbide or gallium nitride based materials, and the term "wide bandgap semiconductor" herein encompasses any semiconductor having a bandgap of at least 1.4 eV. The power semiconductor device is designed to selectively block or pass large voltages and/or currents. For example, in the blocking state, the power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts.

A power semiconductor device such as a power MOSFET may have a lateral structure or a vertical structure. A power MOSFET having a lateral structure has the source and drain regions of the MOSFET on the same major surface (i.e., upper or lower) of the semiconductor layer structure of the device. In contrast, a power MOSFET having a vertical structure has its source region on one major surface of its semiconductor layer structure and its drain region on the other (opposite) major surface. Vertical device structures are typically used for very high power applications because the vertical structure allows for a thick semiconductor drift layer that can support high current densities and prevent high voltages. Herein, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers in which a p-n junction is formed. The semiconductor layer structure generally includes a semiconductor substrate on which a plurality of semiconductor epitaxial layers are formed. A wide bandgap semiconductor layer structure refers to a semiconductor layer structure in which a p-n junction is formed in one or more wide bandgap semiconductor materials.

Conventional vertical silicon carbide power MOSFETs include a silicon carbide drift region formed on a silicon carbide substrate, such as a silicon carbide wafer. A so-called "well" region having a conductivity type opposite to that of the drift region is formed in an upper portion of the drift region, and a silicon carbide source region having the same conductivity type as that of the drift region is formed within the well region. The silicon carbide substrate, the silicon carbide drift region, the silicon carbide well region, and the silicon carbide source region form a semiconductor layer structure of the power MOSFET. The gate finger is formed in or on the semiconductor layer structure to form an individual unit cell transistor.

The unit cell transistor is formed in a so-called "active region" of the MOSFET. The MOSFET also includes one or more inactive regions, such as termination regions that may surround the active region and/or the gate bond pad region. The active region acts as a main junction for blocking voltage during reverse bias operation and providing current during forward bias operation. Power MOSFETs typically have a unit cell (unit cell) structure, meaning that the active region includes a large number of individual "unit cell" MOSFETs electrically connected in parallel to act as a single power MOSFET. In high power applications, such devices may include thousands or tens of thousands of unit cells.

Many power semiconductor devices, such as power MOSFETs and IGBTs, have a gate structure. These devices may be turned on and off by applying different bias voltages to their gate structures. The gate structure has a distributed gate resistance that is a function of the electrical path length from the gate bond pad (or other gate terminal) to the gate finger of each individual unit cell, as well as the sheet resistance of the material forming the gate structure. The gate structure may include, for example, a gate bond pad, a plurality of gate fingers in an active region of the device, a gate pad, and one or more gate buses extending between the gate pad and the gate fingers. In many applications, it may be desirable to increase the amount of gate resistance by, for example, adding one or more discrete or "lumped" gate resistors within the gate structure. The increased gate resistance may be used, for example, to limit the switching speed of the device or reduce electrical ringing and/or noise that may generate vibrations that may cause the device to fail.

Disclosure of Invention

According to an embodiment of the present invention, a semiconductor device is provided that includes a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch coupled between the gate pad and the gate fingers.

In some embodiments, the first switch may be a diode. In some embodiments, the diode may be implemented within the first gate resistor.

In some embodiments, the semiconductor device further includes a second gate resistor and a second switch, such as a diode, coupled between the gate pad and the gate finger. The first diode allows current to flow from the gate pad to the gate finger when forward biased and the second diode allows current to flow from the gate finger to the gate pad when forward biased.

The semiconductor device may have a first total gate resistance value for gate current flowing from the gate pad to the gate finger, and may have a second total gate resistance value for gate current flowing from the gate finger to the gate pad, wherein the second total gate resistance value is different from the first total gate resistance value.

The first gate resistor may include a first section and a second section forming a first diode, wherein the first section includes an n-type semiconductor material and the second section includes a p-type semiconductor material. In some embodiments, the first gate resistor further comprises a third section comprising a p-type semiconductor material, wherein the first section is located between the second section and the third section. In some embodiments, the second gate resistor includes a fourth section, a fifth section, and a sixth section, the fourth section including an n-type semiconductor material, and the fifth and sixth sections including a p-type semiconductor material, wherein the fourth section is interposed between the fifth and sixth sections, and wherein the fourth section and the sixth section form the second diode. In some embodiments, the second section is closer to the gate pad than the third section and the fifth section is closer to the gate pad than the sixth section. In some embodiments, the semiconductor device further includes a first metal connector shorting the first section to the third section and a second metal connector shorting the fourth section to the fifth section.

In some embodiments, the first gate resistor includes a first section of n-type semiconductor material and a second section of p-type semiconductor material, wherein the first section may directly contact the second section. The first gate resistor may further include a third section of p-type semiconductor material, wherein the first section is located between the second section and the third section. The n-type semiconductor material may be n-type polysilicon and the p-type semiconductor material may be p-type polysilicon. The semiconductor device may further include a metal connector shorting the first section to the third section. The metal connector may include a metallization extending through a via in a dielectric layer formed on an upper surface of the first gate resistor.

According to a further embodiment of the present invention, a semiconductor device is provided comprising a gate pad, a plurality of gate fingers, and a gate resistor electrically interposed between the gate pad and the gate fingers, wherein the gate resistor comprises a first section of n-type semiconductor material and a second section of p-type semiconductor material.

In some embodiments, the first section may directly contact the second section.

In some embodiments, the n-type semiconductor material comprises n-type polysilicon and the p-type semiconductor material comprises p-type polysilicon.

In some embodiments, the gate resistor further comprises a third section of p-type semiconductor material, wherein the first section is located between the second section and the third section.

In some embodiments, the semiconductor device further includes a metal connector shorting the first section to the second section. The metal connector may include a metallization extending through a via in a dielectric layer formed on an upper surface of the gate resistor.

In some embodiments, the n-type semiconductor material and the p-type semiconductor material form a diode within the gate resistor.

In some embodiments, the gate resistor is a first gate resistor and the junction between the first section and the second section forms a first diode, the semiconductor device further comprising a second gate resistor and a second diode electrically coupled in parallel with the first gate resistor and the first diode.

In some embodiments, the first diode is configured to allow current to flow from the gate pad to the gate finger when forward biased, and the second diode is configured to allow current to flow from the gate finger to the gate pad when forward biased.

According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, and a first gate resistor and a first circuit element electrically interposed between the gate pad and the gate fingers. The first circuit element is configured to conduct current in only a first direction between the gate pad and the gate finger.

In some embodiments, the first circuit element includes a first diode. In some embodiments, the first diode is implemented within a first gate resistor.

In some embodiments, the semiconductor device further includes a second gate resistor and a second diode electrically interposed between the gate pad and the gate finger, wherein the second diode is configured to conduct current between the gate pad and the gate finger in only a second direction, the second direction being opposite the first direction. In some embodiments, the second diode is implemented within a second gate resistor.

In some embodiments, the first gate resistor includes a first section of n-type semiconductor material and a second section of p-type semiconductor material.

In some embodiments, the semiconductor device further includes a first metal connector shorting a first section of the first gate resistor to a second section of the first gate resistor. In some embodiments, the metal connector includes a metallization extending through a via formed in a dielectric layer on an upper surface of the first gate resistor.

In some embodiments, the first section of the first gate resistor directly contacts the second section of the first gate resistor, and the n-type semiconductor material comprises n-type polysilicon and the p-type semiconductor material comprises p-type polysilicon.

In some embodiments, the semiconductor device further comprises a wide bandgap semiconductor layer structure, and the first gate resistor is located on an upper side of the wide bandgap semiconductor layer structure.

In some embodiments, the semiconductor device further includes an internal dielectric pattern directly on an upper side of the first gate resistor.

According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a gate bus line, and a gate resistor structure electrically interposed between the gate pad and the gate bus line, the gate resistor structure having a first resistance with respect to a current flowing from the gate pad to the gate bus line and a second resistance with respect to a current flowing from the gate bus line to the gate pad, the first resistance being different from the second resistance.

In some embodiments, the semiconductor device further includes a wide bandgap semiconductor layer structure including an active region having a plurality of unit cell transistors, and the gate resistor structure is located on an upper side of the wide bandgap semiconductor layer structure.

In some embodiments, the semiconductor device further includes an internal dielectric pattern directly on an upper side of the gate resistor.

In some embodiments, the gate resistor structure includes a plurality of first gate resistors, a plurality of first switches, a plurality of second gate resistors, and a plurality of second switches.

In some embodiments, each first gate resistor and a respective one of the first switches are coupled between a gate pad and a gate finger, and each second gate resistor and a respective one of the second switches are coupled between a gate pad and a gate finger.

In some embodiments, each first switch includes a first diode and each second switch includes a second diode.

In some embodiments, each first diode is implemented within a respective one of the first gate resistors, and each second diode is implemented within a respective one of the second gate resistors.

In some embodiments, the first diode is configured to allow current to flow from the gate pad to the gate bus when forward biased, and the second diode is configured to allow current to flow from the gate bus to the gate pad when forward biased.

In some embodiments, the number of first gate resistors is different from the number of second gate resistors.

In some embodiments, each first gate resistor is directly adjacent to at least one second gate resistor.

In some embodiments, each first gate resistor and each second gate resistor includes a first section of n-type semiconductor material, a second section of p-type semiconductor material, and a third section of p-type semiconductor material forming an n-p-n junction.

In some embodiments, the semiconductor device further comprises a plurality of first metal connectors each shorting a first section of a respective one of the first gate resistors to a third section of the respective first gate resistor and a plurality of second metal connectors each shorting a first section of a respective one of the second gate resistors to a second section of the respective second gate resistor.

According to a further embodiment of the present invention, a semiconductor device is provided that includes a gate pad, a plurality of gate fingers, and a gate resistor structure electrically interposed between the gate pad and the gate fingers, the gate resistor structure having a first resistance during device on and a second resistance during device off, the first resistance being different from the second resistance.

In some embodiments, the semiconductor device further comprises a wide bandgap semiconductor layer structure including an active region, and the gate resistor structure is located on an upper side of the wide bandgap semiconductor layer structure.

In some embodiments, the semiconductor device further includes an internal metal dielectric pattern directly on an upper side of the gate resistor structure.

In some embodiments, the gate resistor structure includes a first gate resistor and a first switch forming a first circuit coupled between the gate pad and the gate finger, and a second gate resistor and a second switch forming a second circuit coupled between the gate pad and the gate finger.

In some embodiments, the first switch includes a first diode that allows current to flow from the gate pad to the gate finger when forward biased, and the second switch includes a second diode that allows current to flow from the gate finger to the gate pad when forward biased.

In some embodiments, the gate resistor structure includes a plurality of first gate resistor circuits, each including a first gate resistor and a first switch coupled between the gate pad and the gate finger, and a plurality of second gate resistor circuits, each including a second gate resistor and a second switch coupled between the gate pad and the gate finger, wherein all of the first gate resistor circuits and all of the second gate resistor circuits are electrically arranged in parallel with each other.

In some embodiments, the combined resistance of all first gate resistors is different from the combined resistance of all second gate resistors.

According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, a plurality of first gate resistors electrically interposed between the gate pad and the gate fingers, and a plurality of second gate resistors electrically interposed between the gate pad and the gate fingers. The gate current flowing between the gate pad and the gate finger flows at least predominantly through the first gate resistor during device on, and the gate current flows at least predominantly through the second gate resistor during device off.

In some embodiments, the semiconductor device further comprises a plurality of first diodes configured to control current flowing through the first gate resistor, wherein the first diodes are configured to conduct current only from the gate pad to the gate finger. The semiconductor device may further include a plurality of second diodes configured to control current flowing through the second gate resistor, wherein the second diodes are configured to conduct only current from the gate fingers to the gate pad.

In some embodiments, the total resistance of the second gate resistor differs from the total resistance of the first gate resistor by at least 10%.

In some embodiments, each first diode is part of a respective one of the first gate resistors.

In some embodiments, the first resistance of the first one of the first gate resistors is different than the second resistance of the first one of the second gate resistors.

According to a further embodiment of the present invention, a semiconductor device is provided that includes a gate pad, a gate bus, a first gate resistor having a first end directly connected to the metal gate pad and a second end directly connected to the gate bus, and a metal connector electrically connecting a first interior portion of the first gate resistor to a second interior portion of the gate resistor.

In some embodiments, the semiconductor device further includes a first diode integrated within the first gate resistor.

In some embodiments, the semiconductor device further includes a second gate resistor and a second diode coupled between the metal gate pad and the gate bus.

In some embodiments, the first diode is configured such that it allows current to flow from the metal gate pad to the gate bus when it is forward biased, and the second diode is configured such that it allows current to flow from the gate bus to the metal gate pad when it is forward biased.

In some embodiments, the semiconductor device has a first resistance between the metal gate pad and the gate bus line for signals traveling from the metal gate pad to the gate bus line, and a second resistance between the metal gate pad and the gate bus line for signals traveling from the gate bus line to the metal gate pad, the second resistance being different from the first resistance.

In some embodiments, the first gate resistor and the second gate resistor each include a first section of n-type semiconductor material and a second section of p-type semiconductor material.

In some embodiments, the metal connector includes a metallization extending through a via in a dielectric layer formed on an upper surface of the first gate resistor.

According to a further embodiment of the present invention, a semiconductor device is provided that includes a gate pad, a plurality of gate fingers, a first conductive path between the gate pad and the gate fingers that conducts current during device on but does not conduct current during device off, and a second conductive path between the gate pad and the gate fingers that conducts current during device off but does not conduct current during device on.

In some embodiments, the first conductive path includes a plurality of first gate resistor circuits disposed electrically in parallel with each other, and the second conductive path includes a plurality of second gate resistor circuits disposed electrically in parallel with each other.

In some embodiments, each first gate resistor circuit includes a first gate resistor and a first diode, and each second gate resistor circuit includes a second gate resistor and a second diode.

In some embodiments, the first resistance of at least one of the first gate resistors is different from the second resistance of at least one of the second gate resistors.

According to a further embodiment of the present invention, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a plurality of gate fingers on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors electrically coupled between the gate pad and the gate fingers.

In some embodiments, the semiconductor device may further include a gate bus, and each lumped gate resistor may be connected between a gate pad and the gate bus.

In some embodiments, at least two of the lumped gate resistors extend outward from a side edge of the gate pad to contact a portion of the gate bus line extending along the first outer edge of the semiconductor device.

In some embodiments, a first subset of the lumped gate resistors extends outward from a first side of the gate pad and a second subset of the plurality of lumped gate resistors extends outward from a second side of the gate pad. In some embodiments, a third subset of the plurality of lumped gate resistors extends outward from a third side of the gate pad, the third side being opposite the first side. In some embodiments, a fourth subset of the plurality of lumped gate resistors extends outward from a fourth side of the gate pad opposite the second side.

In some embodiments, at least a respective one of the plurality of lumped gate resistors extends outwardly from each side (each and every side) of the gate pad when the semiconductor device is viewed in plan. In some embodiments, the lumped gate resistor extends outward from and substantially surrounds the gate pad when the semiconductor device is viewed in plan.

In some embodiments, the plurality of lumped gate resistors may include a first lumped gate resistor, a second lumped gate resistor, and a third lumped gate resistor each extending from the gate pad, wherein the second lumped gate resistor is directly adjacent to and between the first and third lumped gate resistors. The second lumped gate resistor may have a width that is less than a first distance between the first and second lumped gate resistors, and may also have a width that is less than a second distance between the second and third lumped gate resistors.

In some embodiments, the first distance may be greater than twice the width of the second lumped gate resistor and the second distance may be greater than twice the width of the second lumped gate resistor. In other embodiments, the first distance may be greater than three times the width of the second lumped gate resistor and the second distance may be greater than three times the width of the second lumped gate resistor.

In some embodiments, the length of the second lumped gate resistor may be at least twice the width of the second lumped gate resistor. In some embodiments, the length of the second lumped gate resistor is less than five times the width of the second lumped gate resistor. In some embodiments, the length of the second lumped gate resistor is less than the width of the second lumped gate resistor. In some embodiments, each of the plurality of lumped gate resistors has a respective length that is less than three times a width of the respective lumped gate resistor.

In some embodiments, the lumped gate resistors may be spaced apart from one another such that heat generated in adjacent pairs of lumped gate resistors during normal operation of the semiconductor device is substantially dissipated from the semiconductor device through different portions of the semiconductor layer structure.

In some embodiments, the semiconductor layer structure has a thickness D and a thermal diffusion angle α, and facing sides of adjacent lumped gate resistors are spaced apart from each other by at least 2 x D x tan (α).

In some embodiments, the semiconductor device further includes a first switch coupled in series with a first one of the lumped gate resistors between the gate pad and the gate finger and a second switch coupled in series with a second one of the lumped gate resistors between the gate pad and the gate finger. In some embodiments, the first switch may be a diode implemented within the first gate resistor. In some embodiments, the first switch includes a first diode that allows current to flow from the gate pad to the gate finger when forward biased, and the second switch includes a second diode that allows current to flow from the gate finger to the gate pad when forward biased. In some embodiments, the semiconductor device has a first total gate resistance value for gate current flowing from the gate pad to the gate finger and a second total gate resistance value for gate current flowing from the gate finger to the gate pad, wherein the second total gate resistance value is different from the first total gate resistance value.

In some embodiments, the gate pad has an inverted L-shape or L-shape when viewed in plan.

According to yet a further embodiment of the present invention, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a gate bus on the wide bandgap semiconductor layer structure, and a lumped gate resistor extending between the gate pad and a portion of the gate bus that extends adjacent to a first outer edge of the semiconductor device.

According to yet additional embodiments of the present invention, there is provided a semiconductor device comprising a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors, each of the lumped gate resistors being electrically coupled to the gate pad, at least a respective pair of the plurality of lumped gate resistors extending outwardly from each of at least three sides of the gate pad when the semiconductor device is viewed in plan.

Drawings

Fig. 1 is a graph of drain current as a function of drain voltage for a conventional silicon carbide power MOSFET.

Fig. 2A is a circuit diagram of a conventional power MOSFET.

Fig. 2B is a circuit diagram of a power MOSFET according to some embodiments of the invention.

Fig. 3A is a schematic plan view of a power MOSFET according to some embodiments of the invention.

Fig. 3B is a schematic plan view of the power MOSFET of fig. 3A with its top layer removed.

Fig. 3C is a schematic vertical cross-section taken along line 3C-3C of fig. 3A.

Fig. 4A is a schematic horizontal cross-section of the gate pad region of the power MOSFET of fig. 3A-3C, wherein the cross-section is taken through an upper portion of the gate pad.

Fig. 4B is a schematic vertical cross-section of the power MOSFET of fig. 3A-3C taken along line 4B-4B of fig. 4A.

Fig. 4C is a schematic horizontal cross-section of the gate pad region of the power MOSFET of fig. 3A-3C, wherein the cross-section is taken through a lower portion of the gate pad.

Fig. 4D is a schematic vertical cross-sectional view of the power MOSFET of fig. 3A-3C taken along line 4D-4D of fig. 4C.

Fig. 4E is a schematic horizontal cross-section of the gate pad region of the power MOSFET of fig. 3A-3C, wherein the cross-section is taken through the semiconductor layer including the gate resistor.

Fig. 4F is a schematic vertical cross-sectional view of the power MOSFET of fig. 3A-3C taken along line 4F-4F of fig. 4E.

Fig. 4G is a schematic vertical cross-section taken along line 4G-4G of fig. 4E.

Fig. 4H is a schematic vertical cross-section taken along line 4H-4H of fig. 4E.

Fig. 5A is a circuit diagram illustrating the electrical connection between the gate pad and the gate bus of the power MOSFET of fig. 3A-4H.

Fig. 5B is a schematic diagram illustrating one embodiment of the first and second gate resistor circuits of fig. 5A.

Fig. 5C is a schematic perspective view illustrating a via formed through a dielectric layer that includes a metal connector that shorts the p-n junction in the underlying semiconductor layer.

Fig. 6 is a schematic plan view of two of the gate resistor circuits included in a power MOSFET according to a further embodiment of the invention.

Fig. 7 is a circuit diagram of a power MOSFET according to yet a further embodiment of the invention.

Fig. 8 is a schematic vertical cross-section of a gate trench MOSFET that may include a lumped gate resistor structure in accordance with an embodiment of the invention.

Fig. 9 is a schematic diagram illustrating how heat generated in a single large lumped gate resistor is dissipated through a semiconductor layer structure.

Fig. 10A is a schematic diagram illustrating how heat generated in a plurality of smaller lumped gate resistors is dissipated through a semiconductor layer structure.

Fig. 10B is a schematic diagram illustrating how heat generated in a plurality of smaller lumped gate resistors may be dissipated through substantially different regions of the bottom surface of the semiconductor layer structure.

Fig. 11A is a schematic plan view of a conventional power semiconductor device.

Fig. 11B is an enlarged view of a gate pad region of the conventional power semiconductor device of fig. 11A.

Fig. 12A is a schematic plan view of a power semiconductor device according to a further embodiment of the present invention.

Fig. 12B is an enlarged view of a gate pad region of the power semiconductor device of fig. 12A.

Fig. 13A is a schematic plan view of another conventional power semiconductor device.

Fig. 13B is an enlarged view of a gate pad region of the conventional power semiconductor device of fig. 13A.

Fig. 13C is an enlarged view of a portion of a single large lumped gate resistor included in the conventional power semiconductor device of fig. 13A.

Fig. 14A is a schematic plan view of a power semiconductor device according to yet a further embodiment of the present invention.

Fig. 14B is an enlarged view of a gate pad region of the power semiconductor device of fig. 14A.

Fig. 14C is an enlarged view of several smaller lumped gate resistors included in the power semiconductor device of fig. 14A.

Fig. 15A and 15B are schematic diagrams illustrating how the aspect ratio of lumped gate resistors may be changed to modify the spacing between adjacent lumped gate resistors.

Detailed Description

High speed, high power semiconductor switching devices, such as silicon carbide based MOSFETs, IGBTs, gated thyristors, etc., experience a high dV during both device on and device off _ds /dt (i.e. source-drain voltage V per unit time) _ds Large change of (d) and high dI _ds /dt (i.e. source-drain current I per unit time _ds Is a large change of (c). During the on-period of the device, the transconductance (g _m ) V of the device tends to be driven _ds And I _ds In response, during device turn-off, discharge of capacitance within the device dominates V _ds And I _ds And (5) responding. This is illustrated in FIG. 1, which is the V of a conventional high switching speed, high power silicon carbide MOSFET _ds And I _ds Graph of response. In FIG. 1, curves 1-1 through 1-N represent the voltage at different gate voltages (V _gs ) The device response during device on at the level, while curves 2-1 to 2-N represent the device response during device off at the same series of gate voltage levels.

Many applications require relatively balanced switching operations (i.e., require power switching devices to be turned on and off at approximately the same rate). The asymmetric nature of the device on and off responses (see fig. 1) results in unbalanced switching operation. To compensate for this unbalanced behavior, customers may employ an asymmetric gate control scheme that drives the switching devices differently during device on and off to reduce the difference in on and off behavior. For example, circuitry external to the power semiconductor device may be provided that couples different amounts of resistance to the gate bond pad using off-chip resistors and diodes during device on and device off.

As described above, many power semiconductor devices (such as MOSFETs, IGBTs, and gated thyristors) include one or more lumped gate resistors designed to increase the gate resistance to a desired value. "lumped" gate resistors refer to discrete resistors added to a gate structure to increase its resistance. The total resistance of the gate structure is a combination of the lumped gate resistance provided by the one or more lumped gate resistors and the distributed gate resistance of the gate bus line(s) and gate fingers that receive the gate signal from an external source and distribute the gate signal to the gate pad(s) of the individual unit cell transistors of the device. These lumped gate resistors may, for example, improve electromagnetic interference ("EMI") performance of the device. Furthermore, as the length of the gate fingers of the power switching device increases, a long feedback loop is created, which can lead to high instability within the device. The gate resistor makes these feedback loops more lossy, thereby improving stability. Thus, by including additional lumped gate resistances in series with the distributed gate resistances, it may be possible to increase device yield and/or reduce the failure rate of the device in the field.

As described above, the lumped gate resistor is sometimes implemented "off-die", meaning that the lumped gate resistor and the power semiconductor device are mounted separately on a mounting substrate (e.g., on a motherboard). In such embodiments, the lumped gate resistance may be implemented using surface mount resistors. However, this approach takes up valuable space on the mounting substrate, increases cost, and reduces device reliability (because off-die lumped gate resistance is not as efficient as on-die lumped gate resistance). Therefore, lumped gate resistors are often implemented "on-die" as part of the power semiconductor chip.

Conventionally, on-die lumped gate resistors are implemented by routing the current path for the gate signal through a higher resistance material, such as a semiconductor layer (since the semiconductor material has a higher sheet resistance than the metal used to form the gate pad and potentially other portions of the gate structure, such as the gate bus). These gate resistors are typically integrated in the power switching device between the gate pad and the gate bus/gate finger. For example, the electrical path connecting the gate pad to the gate finger may be routed through a portion of the semiconductor layer (and typically through a narrowed portion in order to increase its resistance), and this portion of the electrical path acts as a lumped gate resistor that increases the overall gate resistance. The semiconductor layer may include, for example, a polysilicon layer.

Fig. 2A is a circuit diagram of a conventional power MOSFET 10 including a gate resistor. As shown in fig. 2A, conventional power MOSFET 10 includes, among other things, a gate terminal 12 (e.g., a gate bond pad), a source terminal 14 (e.g., a source bond pad), and a drain terminal 16 (e.g., a drain bond pad). The gate terminal 12 is part of a gate structure 20, the gate structure 20 further including a gate pad 22 and a plurality of gate fingers 26 that form the gates of the respective unit cell transistors. The gate pad 22 is electrically connected to a gate finger 26 through a gate bus 24 (which is also part of the gate structure 20). A gate resistor circuit 30 including a gate resistor 32 is disposed in electrical series between the gate pad 22 and the gate bus 24. As described above, the gate resistor 32 is typically implemented by forcing a gate current to flow through a section of semiconductor material, which may have a higher resistance than at least some portion of the gate current path through the MOSFET 10. Conventionally, the gate resistor 32 is a single relatively large lumped gate resistor for connecting the gate pad 22 to the gate bus 24.

In a conventional power MOSFET, the semiconductor material used to implement resistor 32 may include, for example, polysilicon doped with a dopant of the first conductivity type. Most commonly, the first conductivity type dopant is a p-type dopant, but n-type dopants may alternatively be used. Thus, the gate resistor 32 in the conventional power MOSFET 10 will conduct a gate current flowing in a first direction from the gate pad 22 to the gate finger 26 (i.e., a gate current flowing during device on and on state operation) and a gate current flowing in a second direction from the gate finger 26 to the gate pad 22 (i.e., a gate current flowing during device off when the capacitance in the device is discharging). Thus, the total resistance of the lumped gate resistor 32 has a constant value (i.e., the lumped gate resistance value is the same during device on as during device off).

According to some embodiments of the present invention, a power semiconductor device having an asymmetric gate resistance is provided. In particular, the power semiconductor device according to an embodiment of the present invention may have a first gate resistance for a gate current flowing into the semiconductor device and a different second gate resistance for a gate current flowing out of the semiconductor device. In some embodiments, the first gate resistance may differ from the second gate resistance by at least 5%, at least 10%, at least 20%, at least 30%, or at least 50%. The first gate resistance may be implemented using one or more first gate resistors inserted in series within the gate structure during device on, and the second gate resistance may be implemented using one or more second gate resistors inserted in series within the gate structure during device off. The values of the first and second gate resistances may be selected to improve performance parameters of the device, such as, for example, a balance of on and off switching behavior.

Fig. 2B is a circuit diagram of a power MOSFET 50 including such an asymmetric gate resistance in accordance with an embodiment of the invention. As shown in fig. 2B, power MOSFET 50 includes, among other things, a gate terminal 52 (e.g., a gate bond pad), a source terminal 54 (e.g., a source bond pad), and a drain terminal 56 (e.g., a drain bond pad). The gate terminal 52 is part of a gate structure 60, the gate structure 60 further including a gate pad 62, a gate bus 64, and a plurality of gate fingers 66 forming gates of respective unit cell transistors. The gate pad 62 is electrically connected to a gate finger 66 through a gate bus 64. A first gate resistor circuit 70 is disposed in electrical series between the gate pad 62 and the gate bus 64. The first gate resistor circuit 70 includes a first gate resistor 72 and a first switch 74. A second gate resistor circuit 80 is disposed in electrical series between the gate pad 62 and the gate bus 64. The second gate resistor circuit 80 includes a second gate resistor 82 and a second switch 84. The first and second gate resistor circuits 70, 80 are disposed electrically in parallel with each other. The first and second gate circuits 70, 80 are also part of the gate structure 60.

The power MOSFET 50 is configured such that gate current flowing in a first direction (e.g., in a direction from the gate pad 62 to the gate bus 64) flows through the first gate resistor 72 but not through the second gate resistor 82, and such that gate current flowing in a second direction (e.g., in a direction from the gate bus 64 to the gate pad 62) opposite the first direction flows through the second gate resistor 82 but not through the first gate resistor 72. Thus, current may flow only through the first gate resistor 72 during device on and will flow only through the second gate resistor 82 during device off. Thus, the first gate resistor 72 may be designed to have a resistance value selected to optimize performance during device on and on state operation, while the second gate resistor 82 may be designed to have a resistance value selected to optimize performance during device off.

In some embodiments, the first switch 74 and the second switch 84 may be implemented as diodes electrically in series with the respective first gate resistor 72 and second gate resistor 82 and/or within the respective first gate resistor 72 and second gate resistor 82. In some embodiments, the first gate resistor 72 and the second gate resistor 82 may be implemented as semiconductor patterns, and the diodes 74, 84 may thus be implemented to form p-n junctions within the semiconductor patterns of the first gate resistor 72 and the second gate resistor 82. In one example embodiment, the first gate resistor 72 and the second gate resistor 82 may each be implemented as a semiconductor pattern having a first n-type region located between a second p-type region and a third p-type region such that each semiconductor pattern has a pair of p-n junctions. A metal connector may be used to short one of the p-n junctions of each semiconductor pattern. The other (un-shorted) p-n junction forms a diode. The semiconductor pattern used to form the first gate resistor 72 may have a short circuit between the p-n junction formed between the first n-type region and the second p-type region (where the second p-type region is the p-type region adjacent to the gate pad 62). Thus, the un-shorted p-n junction in the semiconductor pattern used to form the first gate resistor 72 forms a diode 74, which diode 74 passes current from the gate pad 62 to the gate bus 64 when forward biased. The semiconductor pattern used to form the second gate resistor 82 may have a short circuit between the p-n junction formed between the first n-type region and a third p-type region (where the third p-type region is a p-type region spaced apart from the gate pad 62). Thus, the un-shorted p-n junction in the semiconductor pattern used to form the second gate resistor 82 forms a diode 84, which diode 84 passes current from the gate bus 64 to the gate pad 62 when forward biased.

In some embodiments, a plurality of first gate resistor circuits 70 and a plurality of second gate resistor circuits 80 may be provided. This may further improve the balance of the switching operation.

According to some embodiments, a semiconductor device is provided that includes a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch coupled between the gate pad and the gate fingers. The first switch may be a diode. The devices may also include a second gate resistor and a second diode coupled between the gate pad and the gate finger. The first diode is configured to allow current to flow from the gate pad to the gate finger when forward biased, and the second diode is configured to allow current to flow from the gate finger to the gate pad when forward biased. The semiconductor device may have a first total gate resistance value for gate current flowing from the gate pad to the gate pad and a second total gate resistance value for gate current flowing from the gate finger to the gate pad, wherein the second total gate resistance value is different from the first total gate resistance value.

According to a further embodiment of the present invention, a semiconductor device is provided that includes a gate pad, a plurality of gate fingers, and a gate resistor electrically interposed between the gate pad and the gate fingers. The gate resistor includes a first section comprising an n-type semiconductor material (e.g., n-type polysilicon), a second section comprising a p-type semiconductor material (e.g., p-type polysilicon), and optionally a third section of p-type semiconductor material. A metal connector may be provided that shorts the first section to the second section.

According to additional embodiments of the present invention, a semiconductor device is provided that includes a gate pad, a plurality of gate fingers, and a first gate resistor and a first circuit element (e.g., a diode) electrically interposed between the gate pad and the gate fingers. The first circuit element is configured to conduct current in a first direction only between the gate pad and the gate finger. The semiconductor device may further include a second gate resistor electrically interposed between the gate pad and the gate finger and a second circuit element, wherein the second circuit element is configured to conduct current in a second direction only between the gate pad and the gate finger, the second direction being opposite to the first direction.

According to a further embodiment of the present invention, a semiconductor device is provided that includes a gate pad, a gate bus, and a gate resistor structure electrically interposed between the gate pad and the gate bus. The gate resistor structure has a first resistance relative to current flowing from the gate pad to the gate bus line and a second resistance relative to current flowing from the gate bus line to the gate pad. The first resistance is different from the second resistance. In some embodiments, the gate resistor structure may include a plurality of first gate resistors, a plurality of first switches, a plurality of second gate resistors, and a plurality of second switches.

As discussed above, a single large lumped gate resistor is conventionally used to connect the gate pad of a power semiconductor device to its gate bus. According to an embodiment of the invention, this single large lumped gate resistor may be divided into a plurality of smaller lumped gate resistors spaced apart from each other. As discussed above, this allows at least some of the gate resistors to be designed to allow current flow in only one direction, which allows the total amount of gate resistance to be set to an optimal value for both device on and device off. Another advantage of this approach (whether or not some or all of the lumped gate resistors are designed to conduct current in only one direction) is that it can be used to improve the heat dissipation characteristics of the power semiconductor device. Improving heat dissipation may increase device robustness, which means that the device may operate at higher currents/voltages and/or may operate for longer periods of time without device failure.

When current flows through the gate resistor, energy is dissipated in the resistor and converted to heat. Thus, whenever the gated power semiconductor device is turned on or off, heat is generated in the gate resistor, and the amount of heat generated is especially a function of the switching speed of the device. When a single large lumped gate resistor is used, the generated heat is concentrated in a small area, and thus the temperature of the portion of the semiconductor layer structure under the gate resistor can be significantly raised. Replacing a single large lumped gate resistor used in conventional power semiconductor devices with a plurality of smaller, spaced apart lumped gate resistors may spread the generated heat to a larger portion of the semiconductor layer structure, thereby reducing the temperature increase that occurs in any given portion of the semiconductor layer structure. Test results indicate that this approach can increase the robustness of the power semiconductor device by a factor of four or more. The smaller lumped gate resistors may be dispersed by an amount such that heat dissipated by any pair of adjacent lumped gate resistors will substantially pass through different portions of the semiconductor layer structure in order to improve and/or optimize heat dissipation.

Thus, according to a further embodiment of the present invention, there is provided a semiconductor device comprising a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a plurality of gate fingers on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors electrically coupled between the gate pad and the gate fingers.

In other embodiments, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a gate bus on the wide bandgap semiconductor layer structure, and a lumped gate resistor extending between the gate pad and a portion of the gate bus extending adjacent a first outer edge of the semiconductor device.

In still other embodiments, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors, each electrically coupled to the gate pad, having at least a respective pair of lumped gate resistors extending outwardly from each of at least three sides of the gate pad when the semiconductor device is viewed in plan.

A power semiconductor device according to an embodiment of the present invention will now be described in more detail with reference to fig. 3A-14C.

Fig. 3A is a schematic plan view of a power MOSFET 100 according to an embodiment of the invention. Fig. 3B is a schematic plan view of power MOSFET 100 with the passivation layer, the topside source metallization structure, the gate bond pad and its inter-metal dielectric pattern omitted. Fig. 3C is a schematic cross-sectional view taken along line 3C-3C of fig. 3A, illustrating portions of one complete unit cell and two additional unit cells in the active region of power MOSFET 100. It should be appreciated that the thicknesses of the various layers, patterns and elements in fig. 3A-3C and other figures herein are not drawn to scale and that the figures are schematic in nature.

The power MOSFET 100 includes a wide bandgap semiconductor layer structure 120 (fig. 3C) and a plurality of semiconductor, dielectric, and/or metal layers formed on either side of the semiconductor layer structure 120. Referring first to fig. 3A, a gate pad 110 and one or more source landing pads 112-1, 112-2 are formed on the upper side (fig. 3C) of the semiconductor layer structure 120, and a drain pad 114 (fig. 3C) is provided on the bottom side of the MOSFET 100. Each of the gate pad 110 and the source pad 112 may be formed of a metal such as aluminum to which a bonding wire may be easily attached via conventional techniques such as hot pressing or soldering. The drain pad 114 may be formed of metal that may be connected to an underlying base such as a leadframe, heat spreader, power substrate, etc., via soldering, brazing, direct compression, etc.

The MOSFET 100 includes a source metallization structure 160, which source metallization structure 160 electrically connects the source region 128 in the semiconductor layer structure 120 of the MOSFET 100 to an external device or voltage source, which is electrically connected to the source landing pads 112-1, 112-2. The source metallization structure 160 is indicated in fig. 3A by a dashed box, because a significant portion of the top side metallization structure 160 is covered by a protective layer 116, such as a polyimide layer. In some embodiments, the source bond pads 112-1, 112-2 may be portions of the source metallization structure 160 exposed through openings in the protective layer 116. Shown in fig. 3A are bond wires 118 that may be used to connect the gate and source bond pads 110, 112-1, 112-2 to external circuitry, and the like. The drain pad 114 may be connected to an external circuit through a lower base (not shown) on which the MOSFET 100 is mounted.

Referring to fig. 3B to 3C, a gate structure 130 is formed on the semiconductor layer structure 120. The gate structure 130 includes a plurality of gate insulating fingers 132 (fig. 3C), a plurality of gate fingers 134 (fig. 3B-3C), a gate pad 136 (fig. 3B), and a gate bus structure 138 (fig. 3B) electrically connecting the gate fingers 134 to the gate pad 136. In some embodiments, gate bus 138 may be implemented as a multi-layer structure. The electrical connection between the gate finger 134 and the gate bus 138 may be conventional and will not be described herein. The gate insulating fingers 132 may comprise, for example, silicon oxide, and may insulate the gate fingers 134 from the underlying semiconductor layer structure 120. In some embodiments, the gate finger 134 may include, for example, a polysilicon pattern, but other conductive patterns may alternatively be used. The gate finger 134 may extend horizontally through the device (as shown in fig. 3B), or may alternatively include a planar layer extending through the upper surface of the semiconductor layer structure 120 having an opening therein through which a topside source metallization structure 160 (discussed below) is connected to the source region 128 in the semiconductor layer structure 120. Other configurations may be used (e.g., a unit cell may have a hexagonal configuration, gate fingers 134 may extend vertically instead of horizontally, both vertically and horizontally, etc.). In some embodiments, the gate fingers 134 may be formed within trenches in the upper surface of the semiconductor layer structure 120, as forming the gate fingers 134 within such trenches may improve carrier mobility of, for example, the MOSFET 100 (see fig. 8). The gate pad 136 may be located directly under the gate bonding pad 110 and electrically connected to the gate bonding pad 110. In some embodiments, the gate pad 136 and the gate bond pad 110 may comprise a single monolithic structure. In an example embodiment, the gate pad 136 and the gate bus 138 may comprise metal structures.

Referring to fig. 3C, the semiconductor layer structure includes an n-type silicon carbide semiconductor substrate 122, such as, for exampleHeavily doped with n-type impurities (e.g., at 1x10 ¹⁸ Atoms/cm ³ And 1x10 ²¹ Atoms/cm ³ Between) single crystal 4H silicon carbide semiconductor substrate. The substrate 122 may have any suitable thickness (e.g., between 100 and 500 microns in thickness) and may be partially or completely removed in some embodiments. It should be appreciated that the thicknesses of the substrate 122 and other layers are not drawn to scale in the figures.

The drain pad 114 may be formed on a lower surface of the semiconductor substrate 122. The drain pad 114 may serve as an ohmic contact to the semiconductor substrate 122 and as a pad providing an electrical connection between the drain terminal of the MOSFET 100 and an external device. The drain liner 114 may include, for example, a metal such as nickel, titanium, tungsten, and/or aluminum, and/or alloys and/or thin layer stacks of these and/or similar metals.

The semiconductor layer structure further includes a lightly doped n-type (n ^- ) Silicon carbide drift region 124. The n-type silicon carbide drift region 124 may be formed, for example, by epitaxial growth on the silicon carbide substrate 122. The n-type silicon carbide drift region 124 may have, for example, a 1x10 ¹⁴ To 5x10 ¹⁶ Dopant/cm ³ Is a doping concentration of (c). The n-type silicon carbide drift region 124 may be a thick region having a vertical height above the substrate 122 of, for example, 3-100 microns. It should be appreciated that the thickness of the drift region 124 in fig. 3C is not drawn to scale. Although not shown in fig. 3C, in some embodiments, the upper portion of the n-type silicon carbide drift region 124 may be more heavily doped than the lower portion thereof (e.g., 1x10 ¹⁶ Up to 1x10 ¹⁷ Dopant/cm ³ To provide a current spreading layer on top of the n-type silicon carbide drift region 124).

A P-type well region 126 is formed in the upper portion of n-type drift region 124 by, for example, ion implantation. A heavy doping (n) may then be formed in the upper portion of well region 126 by, for example, ion implantation ⁺ ) n-type silicon carbide source region 128. Channel region 127 is defined in a side of well region 126. The substrate 122, the drift region 124, the well region 126, and the source region 128 may together comprise the semiconductor layer structure 120 of the MOSFET 100. Semiconductor layer structure 120 may be a wide bandgap semiconductor layerStructure 120 (i.e., semiconductor layer structure 120 formed of a wide bandgap semiconductor material).

After forming the n-type source region 128, a plurality of gate insulating fingers 132 (which collectively include a gate insulating pattern) may be formed on an upper surface of the semiconductor layer structure 120. Each gate insulating finger 132 may comprise an elongated strip of dielectric material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like. A gate finger 134, such as a doped polysilicon gate finger 134, is formed on each gate insulating finger 132. The gate fingers 134 and gate insulating fingers 132, along with the gate bond pad 110, gate pad 136, gate bus 138, and gate resistor (discussed below), may collectively comprise a gate structure 130. As described above, the vertically extending portion of well region 126 between source region 128 and the portion of drift region 124 directly below each gate finger 134 includes channel region 127. When a sufficient bias voltage is applied to the gate finger 134, the channel region 127 electrically connects the n-type source region 128 to the drift region 124. When a bias voltage is applied to the gate finger 134, current may flow from the n-type source region 128, through the channel region 127, to the drift region 124, and then to the drain pad 114.

As shown in fig. 3C, an inter-metal dielectric pattern 150 is formed to cover the upper and side surfaces of the gate insulating fingers 132 and the gate fingers 134 in order to electrically isolate the gate fingers 134 from the source metallization structure 160. Although not shown in fig. 3C, the inter-metal dielectric pattern 150 may also electrically insulate the gate pad 136 and/or the gate bus 138 from the source metallization structure 160. The inter-metal dielectric pattern 150 may include a plurality of individual dielectric fingers that cover the respective gate fingers 134, as well as additional dielectric structures in the gate pad region of the device. The inter-metal dielectric pattern 150 may, for example, include one or more of a silicon oxide pattern, a silicon nitride pattern, aluminum oxide, magnesium oxide, or a mixture of these or other oxides and nitrides with silicon dioxide to form a silicate or oxynitride alloy dielectric.

Source metallization structure 160 may be formed on inter-metal dielectric pattern 150. The source metallization structure 160 may include one or more layers such as, for example, a diffusion barrier layer (e.g., one or more titanium and/or tungsten containing layers) and a bulk metal layer (e.g., an aluminum layer).

Fig. 4A-4F are horizontal and vertical cross-sectional views of the gate pad region of the power MOSFET 100 of fig. 3A-3C, illustrating the design of its gate resistor structure. The horizontal cross-section of fig. 4A corresponds to the gate pad region "a" shown in fig. 3A, with the passivation layer 116 and the gate bonding pad 110 removed. Fig. 4B is a schematic vertical cross-section taken along line 4B-4B of fig. 4A. For completeness, the gate bond pad 110 and passivation layer 116 omitted from fig. 4A are shown in fig. 4B. The dotted lines extending between fig. 4A and 4B illustrate the correspondence between the structures in the two figures. Line 4A-4A in FIG. 4B illustrates a vertical "slice" of MOSFET 100, with the horizontal cross-section of FIG. 4A taken.

As shown in fig. 4A-4B, a gate pad 136 is formed under the gate bond pad 110. An inter-metal dielectric layer 150 electrically isolates the gate pad 136 from the source metallization 160. A field oxide layer 140 (e.g., a thick silicon oxide layer) is formed on the semiconductor layer structure 120 under the gate pad 136. A polysilicon layer 170 is formed on the upper surface of the field oxide layer 140. The polysilicon layer 170 may be a continuous layer under the gate pad 136. The polysilicon layer 170 may also extend into the active region of the device (as shown at the side edges of fig. 4B) and may be patterned to form gate fingers 134 on top of the respective gate insulating fingers 132. A gate pad 136 is formed on an upper surface of the polysilicon layer 170, and a gate bonding pad 110 is formed on an upper surface of the gate pad 136. The gate pad 136 and the gate bond pad 110 may comprise a monolithic structure or two or more separate layers. Gate bus 138 is formed on top of inter-metal dielectric layer 150 and polysilicon layer 170. The gate bus 138 does not extend as far above the semiconductor layer structure 120 as the gate pad 136 so that the inter-metal dielectric layer 150 covers the top surface of the gate bus 138. An inter-metal dielectric layer 150 electrically isolates the gate pad 136 and gate bus 138 from the source metallization structure 160.

The polysilicon layer 170 may be a doped polysilicon layer and may be formed in any suitable manner. For example, in some embodiments, the doped polysilicon layer 170 may be formed by deposition (e.g., in a low pressure chemical vapor deposition furnace, with dopant species introduced during growth). In other embodiments, the doped polysilicon layer 170 may be deposited as an undoped polysilicon layer 170, and may then be doped via ion implantation. In still other embodiments, the polysilicon layer 170 may be deposited as an undoped polysilicon layer 170 and may then be doped via diffusion.

Fig. 4C is a schematic horizontal cross-sectional view of region "a" of power MOSFET 100, wherein the cross-section is taken at a level in the device structure of gate bus 138. As shown in fig. 4C, an inner portion 152 of the inter-metal dielectric pattern 150 separates the gate pad 136 from the gate bus line 138. The gate bus 138 may surround the gate pad 136 and, as shown in fig. 3B, may extend through the MOSFET 100 to carry the gate signal applied to the gate bond pad 110 to the gate finger 134. An outer portion 154 of the inter-metal dielectric pattern 150 separates the gate bus 138 from the source metallization 160. In some embodiments, the inner portion 152 and the outer portion 154 of the inter-metal dielectric layer 150 may be monolithic structures (see fig. 4D).

Fig. 4D is a schematic vertical cross-sectional view taken along line 4D-4D of fig. 4C. The cross-section of fig. 4D is similar to the cross-section of fig. 4B, but the vertical cross-section of fig. 4D is taken at a different location in fig. 4D (i.e., a long section through the inter-metal dielectric pattern 150 instead of through the gate pad 136). Fig. 4A-4D together illustrate how the inter-metal dielectric pattern 150 electrically isolates the gate pad 136 from the gate bus 138 such that gate current cannot flow directly from the gate pad 136 to the gate bus 138. Line 4C-4C in FIG. 4D illustrates the level of MOSFET 100, with the horizontal cross section of FIG. 4C taken.

Fig. 4E is a schematic horizontal cross-sectional view of region "a" of power MOSFET 100, wherein the cross-section is taken at a level in the device structure of the portion of polysilicon semiconductor layer 170 that is located below gate pad 136. Fig. 4F is a schematic vertical cross-section taken along line 4F-4F of fig. 4E. Lines 4E-4E in FIG. 4F illustrate the layers of MOSFET 100, with the horizontal cross section of FIG. 4E taken.

As shown in fig. 4E-4F, the inter-metal dielectric pattern 150 includes downward protrusions 156 that extend into the polysilicon layer 170 below the gate pad 136 and gate bus 138 to form dielectric islands therein. These dielectric islands 156 separate the polysilicon layer 170 into an inner region 172 and an outer region 174. A polysilicon pattern 176 exists in the openings 158 between adjacent dielectric islands 156 so that current can flow between the inner portion 172 and the outer portion 174 of the polysilicon layer 170 through the polysilicon pattern 176. Thus, the polysilicon pattern 176 in each opening 158 provides a corresponding current path that allows gate current applied to the gate bond pad 110 to flow through the gate pad 136 and then through the polysilicon pattern 176 located in the opening 158 to the outer portion 174 of the polysilicon layer 170 where the gate current may then flow into the gate bus 138. The polysilicon pattern 176 in the opening 158 (i.e., the polysilicon region between the inner portion 172 and the outer portion 174) acts as a lumped gate resistor 176 that can be used to increase the resistance of the gate structure 130.

Fig. 4G and 4H are vertical cross-sections taken through MOSFET 100 at the locations of lines 4G-4G and 4H-4H of fig. 4E, respectively.

Referring to fig. 4G, when a bias voltage is applied to the gate bonding pad 110, gate current flows down the gate pad 136 and into the inner portion 172 of the polysilicon layer 170. The gate current flows through the gate resistor 176 and then into the gate bus 138 along the path of least resistance. The gate current will flow primarily at or near the upper surface of the portion of the polysilicon layer 170 connecting the inner portion 172 to the outer portion 174 and will leave the polysilicon layer 170 once current can flow into the gate bus 138. The polysilicon layer 170 has a much higher resistance than the metal used to form the gate bond pad 110, the gate pad 136, and the gate bus 138, so that the portion of the gate current path that flows through the polysilicon layer 170 can act as a lumped gate resistor 176 that is interposed on the gate current path between the gate pad 136 and the gate bus 138.

Referring to fig. 4H, it can be seen that in some positions, the inter-metal dielectric layer 150 extends all the way through the polysilicon pattern 170 to the underlying field oxide layer 140. Thus, in the portion of the device shown in the cross-section of fig. 4H, current cannot flow from the inner portion 172 to the outer portion 174 of the polysilicon layer 170. In other words, gate current can only flow from the inner portion 172 of the polysilicon layer 170 to the outer portion 174 thereof through the openings 158 between the dielectric islands 156 shown in fig. 4E. Accordingly, a plurality of lumped gate resistors 176 are formed in the polysilicon layer 170. The resistance of each lumped gate resistor 176 is a function of the dimensions of the opening 158 (i.e., its length and width) and the sheet resistance of the polysilicon material (or other material of the gate resistor layer). The number of openings and/or the dimensions of the openings 158 may be varied such that the total aggregate resistance of the lumped gate resistor 176 may have a desired resistance value.

Referring again to fig. 2A, the conventional power MOSFET 10 includes a lumped gate resistor 32. The lumped gate resistor 32 is typically implemented as a polysilicon pattern electrically disposed in series along the gate current path between the gate pad 22 and the gate bus 24. The polysilicon pattern is doped with a first conductivity type dopant (e.g., p-type dopant). The lumped gate resistor 32 will conduct gate current flowing in both directions (i.e., from the gate pad 22 to the gate bus 24 and from the gate bus 24 to the gate pad 22). Accordingly, the lumped gate resistance provided by the lumped gate resistor 32 in the conventional power MOSFET 10 of fig. 2A has a constant value (i.e., the lumped gate resistance value is the same during device on as during device off).

As discussed above with reference to fig. 2B, a power MOSFET in accordance with an embodiment of the invention may include both one or more first gate resistor circuits and one or more second gate resistor circuits, each of which is electrically disposed in series between a gate pad and a gate bus. Fig. 5A is a circuit diagram illustrating the electrical connection between gate pad 136 and gate bus 138 of power MOSFET 100 of fig. 3A-4H.

As shown in fig. 5A, the gate pad 136 is coupled to the gate bus 138 through a plurality of first gate resistor circuits 180 and through a plurality of second gate resistor circuits 190. Each first gate resistor circuit 180 and each second gate resistor circuit 190 are disposed in electrical series between the gate pad 136 and the gate bus 138. The first gate resistor circuit 180 and the second gate resistor circuit 190 are disposed electrically in parallel with each other. Each first gate resistor circuit 180 includes a first gate resistor 182 and a first diode 184. Each second gate resistor circuit 190 includes a second gate resistor 192 and a second diode 194. In the depicted embodiment, the first diode 184 is implemented within the first gate resistor 182 and the second diode 194 is implemented within the second gate resistor 192, as shown in fig. 5A. It should be appreciated that in other embodiments, the first and/or second diodes 184, 194 may be implemented separately from the first/second gate resistors 182, 192 and may be disposed in electrical series with the respective first and/or second gate resistors 182, 192. It should be appreciated that the first diode 184 and the second diode 194 may be located on either or both sides of the respective first and second gate resistors 182, 184.

Fig. 5B is a schematic diagram illustrating one embodiment of the first and second gate resistor circuits 180, 190 of fig. 5A. As shown in fig. 5B, each first gate resistor circuit 180 may include a first section 185 of n-type semiconductor material disposed between a second section 186 of p-type semiconductor material and a third section 187 of p-type semiconductor material. The first segment 185 of n-type semiconductor material may directly contact the second segment 186 of p-type semiconductor material and the third segment 187 of p-type semiconductor material. The first through third segments 185-187 of semiconductor material may form a first gate resistor 182. A p-n junction between a first segment 185 of n-type semiconductor material and a second segment 186 of p-type semiconductor material may form a first diode 184. When forward biased, the first diode 184 will conduct current from left to right (i.e., from the gate pad 136 to the gate bus 138). The first diode 184 will block current flow from right to left (i.e., from the gate bus 138 to the gate pad 136).

A first metal connector 188 is provided that shorts the first segment 185 of n-type semiconductor material to the third segment 187 of p-type semiconductor material. Current traveling between the first segment 185 of n-type semiconductor material and the third segment 187 of p-type semiconductor material will flow through the first metal connector 188 and thus the p-n junction formed at the intersection of the first segment 185 of n-type semiconductor material and the third segment 187 of p-type semiconductor material is effectively bypassed. For example, the first metal connection 188 may be formed by forming a dielectric layer (e.g., the inter-metal dielectric layer 150 discussed above) over the first gate resistor circuit 180 and then forming a via 159 through the inter-metal dielectric layer 150 and depositing metal forming the first metal connection 188 at the bottom of the via 159. This is schematically illustrated in fig. 5C. The metal connector 188 electrically connects the first interior portion of the first gate resistor 182 to the second interior portion of the gate resistor 182.

Referring again to fig. 5B, each second gate resistor circuit 190 can include a first section 195 of n-type semiconductor material disposed between a second section 196 of p-type semiconductor material and a third section 197 of p-type semiconductor material. The p-n junction between the first region 195 of n-type semiconductor material and the third region 197 of p-type semiconductor material may form a second diode 194. When forward biased, the second diode 194 will conduct current from right to left (i.e., from the gate bus 138 to the gate pad 136). The second diode 194 will prevent current from flowing from left to right (i.e., from the gate pad 136 to the gate bus 138). A second metal connector 198 is provided that shorts the first section 195 of n-type semiconductor material to the second section 196 of p-type semiconductor material. Current traveling between the first section 195 of n-type semiconductor material and the second section 196 of p-type semiconductor material will flow through the second metal connector 198 and thus the p-n junction formed at the intersection of the first section 195 of n-type semiconductor material and the second section 196 of p-type semiconductor material is effectively bypassed. The second metal connector 198 may be formed in the same manner as the first metal connector 188.

In an example embodiment, the semiconductor material used to form segments 185-187 and 195-197 may be polysilicon. It should also be appreciated that in other embodiments, the conductivity of each segment 185-187 and 195-197 may be reversed.

As is clear from the above discussion, during device on and device operation, gate current will flow only through the first gate resistor circuit 180 and will not flow through the second gate resistor circuit 190. During device off, gate current will flow only through the second gate resistor circuit 190 and will not flow through the first gate resistor circuit 180. Referring again to fig. 4E, a plurality of gate resistor circuits 176 are formed under the gate pads 136 in the MOSFET 100. Some of the gate resistor circuits 176 may include a first gate resistor circuit 180, while other gate resistor circuits 176 may include a second gate resistor circuit 190. In some embodiments, each of the first gate resistor circuit 180 and the second gate resistor circuit 190 may have the same shape/size, and the number of first gate resistor circuits 180 may be different from the number of second gate resistor circuits 190 in order to configure the MOSFET 100 to have different lumped gate resistance values during on-operations than during off-operations. In other embodiments, the MOSFET 100 may have the same number of first and second gate resistor circuits 180, 190, but at least some of the first and second gate resistor circuits 180, 190 may have different sizes/shapes such that the resistance values during the on operation will be different than during the off operation. In still further embodiments, the number of first gate resistor circuits may be different from the number of second gate resistor circuits, and the size/shape of the first gate resistor circuit 180 and the second gate resistor circuit 190 may vary. It should also be appreciated that additional or other parameters may be changed to configure the MOSFET 100 to have a different lumped gate resistance value, such as semiconductor materials, doping levels, etc., during on operation than during off operation. Gate resistors without associated switches may be provided such that gate current will flow through these gate resistors during device on and device off. In some embodiments, the gate resistance during device on may differ from the gate resistance during device off by at least 5%, at least 10%, at least 20%, at least 30%, or at least 50%.

In some embodiments, the first gate resistor circuits 180 and the second gate resistor circuits 190 may be "interdigitated," which means that each first gate resistor circuit 180 (except for any first gate resistor circuit 180 that is directly adjacent to an edge of the device) may be directly adjacent to two second gate resistor circuits 190 (i.e., a second gate resistor circuit 190 is located on each side of each first gate resistor circuit 180), and as such each second gate resistor circuit 190 (except for any second gate resistor circuit 190 that is directly adjacent to an edge of the device) may be directly adjacent to two first gate resistor circuits 180 (i.e., a first gate resistor circuit 180 is located on each side of each second gate resistor circuit 190), which may help further improve the balance of the device. It should be appreciated that other interdigital designs may be employed (e.g., a pair of first gate resistor circuits 180 interposed between two pairs of second gate resistor circuits 190, and vice versa). In some embodiments, each first gate resistor circuit 180 may be directly adjacent to at least one second gate resistor circuit 190.

Fig. 6 is a schematic diagram illustrating another possible implementation of the first and second gate resistor circuits 180, 190 of fig. 5A. As shown in fig. 6, each first gate resistor circuit 180 may include only a first section 185 of n-type semiconductor material and a second section 186 of p-type semiconductor material, and each second gate resistor circuit 190 may include only a first section 195 of n-type semiconductor material and a third section 197 of p-type semiconductor material. For example, if portions of the polysilicon layer 170 below the gate pad 136 and gate bus 138 (see fig. 4A-4H) are removed and the gate pad 136 and gate bus 138 are extended to replace the omitted corresponding portions of the polysilicon layer 170 (i.e., the gate pad 136 and gate bus 138 are extended to directly contact the top surface of the field oxide layer 140), then the first and second gate resistor circuit 180, 190 designs shown in fig. 6 may be used. Since in this design the first and second gate resistor circuits 180, 190 directly contact the metal gate pad 136 on one side and the metal gate bus 138 on the other side, a single p-n junction may be provided in each of the first and second gate resistor circuits 180, 190. This design eliminates any need for the first metal connector 188 and the second metal connector 198 because there is no second p-n junction that needs to be shorted.

Fig. 7 is a circuit diagram illustrating a power MOSFET 200 having a different design for the first and second gate resistor circuits according to a further embodiment of the invention. Power MOSFET 200 may be the same as power MOSFET 100 discussed above, except that first gate resistor circuit 180 and second gate resistor circuit 190 of power MOSFET 100 are replaced with first gate resistor circuit 280 and second gate resistor circuit 290 in power MOSFET 200. As can be seen by comparing fig. 2B with fig. 7, in the power MOSFET 200, the first gate resistor circuit 280 and the second gate resistor circuit 290 include respective first gate resistor 282 and second gate resistor 292 and respective first transistor 284 and second transistor 294 in place of the first and second diodes 184, 194 included in the power MOSFET 100. The first and second gate resistors 282, 292 may, for example, have the same design as the first and second gate resistors 182, 192 shown in fig. 5B, and the gates of the transistors 284, 294 may be formed over the first sections 185, 195 of n-type semiconductor material (and extending over the edges of the second and third sections 186-187, 196-197 of p-type semiconductor material) with a gate insulating layer (not shown) disposed therebetween. A signal may be applied to the gates of transistors 284, 294 to allow gate current to flow through first gate resistor circuit 280 only during device on and device operation and to allow gate current to flow through second gate resistor circuit 290 only during device off.

While the above examples of the present invention are all directed to power MOSFET designs, it should be appreciated that embodiments of the present invention are not so limited. In particular, it should be appreciated that the integrated asymmetric gate resistor designs disclosed herein may be used in any gated device, including MOSFET, IGBT, JFET, thyristor, GTO, or any other gated device.

While the above discussion has focused primarily on planar MOSFETs, it should be appreciated that all of the disclosed embodiments may equally be used in MOSFETs (or other gate-controlled power semiconductor devices) in which the gate fingers are formed within trenches in the semiconductor layer structure. For example, fig. 8 is a schematic cross-sectional view of a MOSFET 300 as a modified version of MOSFET 100. The MOSFET 300 of fig. 8 includes gate fingers 334 formed in trenches 321 within the semiconductor layer structure 320, rather than having planar gate fingers formed on the semiconductor layer structure. As shown in fig. 8, MOSFET 300 may be very similar to MOSFET 100 of fig. 3C, except that trenches 321 are etched (or otherwise formed) in semiconductor layer structure 320 and gate insulating fingers 332 and gate fingers 334 are then formed in respective trenches 321. In addition, a p-type shield region 329 may be formed under all or part of each trench 321 to protect the gate insulating fingers 332 during a reverse bias operation, and a p-shield connection region 331 may be provided that electrically connects the p-type shield region 329 to the source metallization 160. Thus, it should be appreciated that gate resistors according to embodiments of the present invention may be implemented in gate controlled devices having gate trenches (such as the device of fig. 8) as well as in devices having planar gate fingers.

As discussed above, various gated power semiconductor devices may exhibit unbalanced switching behavior due to asymmetric device behavior during device on and device off. According to an embodiment of the present invention, there is provided a power semiconductor device including an integrated gate resistor circuit that exhibits different resistance values during device on and off. By applying such different resistance values, the balance of the switch can be improved.

As discussed above, the use of asymmetric gate resistances may advantageously improve the balance of on and off switching behavior of the power semiconductor device. The asymmetric gate resistance may be achieved by implementing the lumped gate resistor of the power semiconductor device as a plurality of discrete lumped gate resistors having relatively small resistance values instead of using a single lumped gate resistor having relatively large resistance values. Each smaller lumped gate resistor may be coupled in series with a switch such as a diode, with some diodes configured to allow current to flow from the gate pad to the gate finger in a first direction and others configured to allow current to flow from the gate finger to the gate pad in a second (opposite) direction. In this way, current flowing from the gate pad to the gate finger will flow through a first subset of the lumped gate resistors providing a first gate resistance value for current flowing into the power semiconductor device and current flowing from the gate finger to the gate pad will flow through a second (different) subset of the lumped gate resistors providing a second gate resistance value for current flowing out of the power semiconductor device. The first gate resistance and the second gate resistance may be set to different values to optimize performance parameters of the power semiconductor device.

An additional advantage of replacing a single lumped gate resistor having a relatively large resistance value with a plurality of discrete lumped gate resistors having a relatively small resistance value is that this technique allows the gate resistors to be spaced apart from one another. Each time a gated power semiconductor device (such as a MOSFET or IGBT) transitions from an off state to an on state, or vice versa, a fixed amount of gate current is required to flow into the gate structure of the device. Such gate currents are designed to flow through lumped gate resistors in order to control the switching speed of the device and/or to reduce electrical ringing and noise that may occur due to undesired loop behavior in case of insufficient gate resistance. The total gate resistance includes the resistance of the lumped gate resistor as well as the distributed gate resistance, which is provided by the sheet resistance of the gate finger (typically polysilicon) and the gate bus line(s) that electrically connect the gate finger to the gate pad (the gate bus line is typically metal, but could alternatively be polysilicon or other material). It can be seen that when charging the gate of a power semiconductor device such as a MOSFET, the energy lost due to the total gate resistance is equal to the energy required to charge the MOSFET, i.e.:

Energy loss=0.5×q _{g_total} *ΔV _gs

Wherein Q is _{g_total} Is the total gate charge, and DeltaV _gs Is a change in gate-to-source voltage that occurs through the charging of the gate.

The same amount of energy is lost each time the gate of the power semiconductor device discharges to transition the device from the on state to the off state.Thus, for a complete switching cycle, the energy loss is equal to Q _{g_total} *ΔV _gs . The occurrence of such energy loss is equal to the switching frequency (F _sw ). Thus, the average power consumption of the total series gate resistance can be determined as follows:

average power consumption=q _{g_total} *ΔV _gs *F _sw

In general, the lumped gate resistance represents a significant portion of the total series gate resistance, and thus a significant portion of the power consumption may occur in the lumped gate resistor. The power is dissipated in the form of heat which must then be removed from the semiconductor device to ensure that the temperature of the power semiconductor device is maintained within the desired operating temperature range of the device.

As described above, lumped gate resistors can be formed on the power semiconductor die because this can reduce part count and improve device performance. The power semiconductor device may be designed to operate at high temperatures, such as, for example, 200 ℃ or higher. The performance of the device may degrade at higher temperatures and, on average, operation at sufficiently high temperatures may cause the power semiconductor device to fail prematurely.

In conventional power semiconductor devices, the lumped gate resistance is typically implemented as a single lumped gate resistor formed by forcing a gate current through a piece of polysilicon material whose length and width are selected to achieve the desired lumped gate resistance value. The lumped gate resistance may be determined as ρl/(w×t), where ρ is the resistivity of the material (here polysilicon), W is the width, L is the length, and t is the thickness. As mentioned above, a significant portion of the power loss that occurs during the charging and discharging of the gate is dissipated in the lumped gate resistor, which converts the power into heat, which must then be removed from the device. This is typically accomplished by providing a heat dissipation path through the device to a cooling medium, such as a heat sink. Typically, heat sinks are mounted on the bottom or "back" side of the semiconductor layer structure, while lumped gate resistors are formed on the top side of the semiconductor layer structure. Thus, the heat generated in the lumped gate resistor is dissipated from the device primarily by conducting this heat through the semiconductor layer structure to the heat sink.

As heat from the lumped gate resistor passes through the semiconductor layer structure, it increases the temperature of the semiconductor layer structure. The increase in temperature can be calculated using the law of thermal conduction as follows:

ΔT＝P _g *R _th

Wherein P is _g Is a heat flow, and R _th Is the thermal resistance of the semiconductor layer structure.

The thermal resistance of a medium, such as the semiconductor layer structure of a power semiconductor device, may be derived based on the cross-sectional area of the medium (i.e., for a medium having a rectangular cross-section, the length of the medium multiplied by the width of the medium), the thickness of the medium, and the thermal conductivity of the medium. However, in the case of a lumped gate resistor, the surface area of the lumped gate resistor that contacts the heat sink medium (here, the semiconductor layer structure) is much smaller than the surface area of the heat sink medium. Thus, heat will enter the semiconductor layer structure through the portion of the first surface having the small surface area and leave the semiconductor layer structure through the portion of the second surface having the much larger surface area. In this way, heat may not only travel in the thickness direction of the semiconductor layer structure, but may also be laterally dispersed. The lateral heat dissipation serves to enlarge the heat flow area. The expansion of the heat flow area reduces the effective thermal resistance of the heat dissipating medium, which results in an improvement of heat dissipation. The net effect of the increased heat flow area is that more heat can be removed while keeping the temperature increase of the semiconductor layer structure constant, or alternatively, the net increase in temperature of the semiconductor layer structure can be reduced while keeping the removed heat constant.

Fig. 9 is a diagram illustrating a lumped gate resistor R _L Schematic illustration of how the heat generated in (c) is dissipated through the semiconductor layer structure SLS. As shown in fig. 9, a semiconductor layer structure SLS having a width W is formed on an upper surface thereof _L And length L _L Is a single lumped-gate resistor R of (2) _L . As shown in fig. 9, from the lumped gate resistor R _L The heat injected into the semiconductor layer structure SLS will depend on and be used to form the semiconductorThe material-associated thermal diffusion angle α of the conductor layer structure SLS diffuses in the semiconductor layer structure SLS and will leave the bottom surface of the semiconductor layer structure with a width W _E And length L _E Is defined in the above-described specification). Thus, heat passes through the heat exchanger having a surface area A _out ＝W _E *L _E Is separated from the semiconductor layer structure. As can be seen from fig. 9, by a single lumped gate resistor R _L The surface area a of the portion of the bottom surface of the semiconductor layer structure SLS through which the generated heat leaves the semiconductor layer structure SLS _out Is a function of the thermal diffusion angle α and the thickness T of the semiconductor layer structure SLS and can be much larger than the lumped gate resistor R _L Surface area of bottom surface (A) _in ＝W _L *L _L )。

The above discussed single lumped gate resistor R provided in conventional power semiconductor devices according to embodiments of the invention _L Can be divided into a plurality of smaller lumped gate resistors R spaced apart from each other _g In order to improve the heat dissipation characteristics of the power semiconductor device. As discussed above, a conventional single lumped gate resistor R is assumed _L Occupies only a small area on the top surface of the semiconductor layer structure SLS, then the lumped gate resistor R when heat is dissipated therethrough _L The heat generated during operation of the device can only spread laterally to the semiconductor layer structure SLS and thus all heat is eventually dissipated through a relatively small area of the semiconductor layer structure SLS, thereby significantly increasing the temperature of this portion of the semiconductor layer structure SLS. By using a plurality of spaced-apart smaller lumped gate resistors R _g Instead of a single large lumped gate resistor R used in conventional power semiconductor devices _L The heat dissipation of the power semiconductor device can be significantly improved. Preliminary test results indicate that this approach can increase the "robustness" of the power semiconductor device by about four times, where robustness refers to the ability of the device to operate at higher power levels.

In some embodiments, a smaller lumped gate resistor R _g May be dispersed by an amount such that the capacitor is formed by any pair of adjacent lumped gate resistors R _g The dissipated heat will pass through the semiconductor layer structureDifferent parts of the SLS. This is illustrated with respect to fig. 10A, fig. 10A being a graph illustrating the placement of a plurality of smaller lumped gate resistors R _g1 To R _g3 Schematic illustration of how the heat generated in (c) is dissipated through the semiconductor layer structure SLS. As shown in fig. 10A, three relatively small lumped gate resistors R _g1 To R _g3 Formed on the upper surface of the semiconductor layer structure having a thickness T. Each smaller lumped gate resistor R _g May have a larger single lumped gate resistor R as shown in fig. 9 _L 1/3 of the resistance of (c). Preferably, each smaller lumped gate resistor R _g Spaced apart so that their respective heat output areas A _out And do not overlap. As can be readily seen by comparing fig. 9 with fig. 10A, the area a occupied by the three regions in fig. 10A _out Can be significantly larger than the single lumped gate resistor R in fig. 10A _L Associated corresponding area A _out 。

In other embodiments, smaller lumped gate resistors R _g May be dispersed by an amount such that the capacitor is formed by any pair of adjacent lumped gate resistors R _g The dissipated heat will substantially pass through different parts of the semiconductor layer structure SLS. Fig. 10B illustrates such an embodiment. In fig. 10B, two smaller lumped gate resistors R are shown _g1 And R is _g2 . By lumped gate resistors R _g1 The generated heat passes through the first area A ₁ Away from the bottom surface of the semiconductor layer structure SLS and formed by a lumped gate resistor R _g2 The generated heat passes through the second area A ₂ Away from the bottom surface of the semiconductor layer structure SLS. First area A ₁ And a second area A ₂ Partially overlap, wherein the overlapping region is designated as overlapping area A _O . As described above, in some embodiments, the lumped gate resistor R _g1 、R _g2 It is possible to separate by an amount such that the heat dissipated by the two resistors will substantially pass through different parts of the semiconductor layer structure SLS. In this context, "substantially" means the first area a shown in fig. 10B ₁ And a second area A ₂ At least overlap area A _O Ten times (i.e., A ₁ +A ₂ ≥10*A _O ). In other words, from the lumped gate resistor R _g1 、R _g2 The heat of both leaves the semiconductor layer structure by no more than 10% of the area of the semiconductor layer structure from the heat of the first and second gate resistors in the pair. First area A ₁ For example, can be determined as A ₁ ＝W _E *L _E ＝(2*T*tan(α)+W _L )*(2*T*tan(α)+L _L )。

It should be appreciated that although the first area A ₁ And a second area A ₂ Having little or no overlap may provide the greatest improvement in heat dissipation, but improved performance may still be achieved with a greater amount of overlap. Thus, in other embodiments, the first area A shown in FIG. 10B ₁ And a second area A ₂ The sum of (a) may be the overlapping area A _O At least eight times (i.e., A ₁ +A ₂ ≥8*A _O ) Area of overlap A _O At least five times (i.e., A ₁ +A ₂ ≥5*A _O ) Overlapping area A _O At least twice (i.e., A) ₁ +A ₂ ≥2*A _O ) Or overlapping area A _O At least 1.5 times (i.e., A ₁ +A ₂ ≥1.5*A _O )。

The number of smaller lumped gate resistors used to replace a single lumped gate resistor in a conventional device may be selected based on a variety of considerations. In general, increasing the number of smaller lumped gate resistances (while keeping the total value of the lumped gate resistances constant) will decrease the effective thermal resistance (and thus improve heat dissipation) until the available area for heat dissipation at the bottom of the semiconductor layer structure has been fully utilized. At this point, further subdivision of the lumped gate resistance does not have any effect on the effective thermal resistance. As shown in fig. 10A-10B, in order for the heat generated by the first lumped gate resistor not to be separated by the same area as the heat generated by the second, adjacent lumped gate resistor of the semiconductor layer structure SLS, the facing side edges of the first and second lumped gate resistors should be separated by a distance of at least 2 x t x tan (α).

Fig. 11A is a schematic plan view (top view) of a conventional power semiconductor device 400. Fig. 11B is an enlarged view of a gate pad region of the conventional power semiconductor device 400 of fig. 11A.

As shown in fig. 11A, the power semiconductor device 400 includes a gate pad 410, a gate bus 420, a lumped gate resistor 430, a gauge pad 440, and a source metallization 450. The dummy pad 440 is not actually part of the conventional power semiconductor device 400, but represents an additional feature included to allow accurate measurement of gate resistance. In this particular device, gate pad 410 is located in the upper left corner of device 400. The gate bus 420 includes a plurality of gate bus segments 422-1 through 422-7, which gate bus segments 422-1 through 422-7 interconnect to form a continuous gate bus 420 that extends around a majority of the periphery of the power semiconductor device 400 and also extends into the interior of the device. The first segment 422-1 and the second segment 422-2 of the gate bus 420 are spaced apart from the gate pad 410 by respective first gaps 424-1 and second gaps 424-2. The gate resistor 430 is inserted in a portion of the first gap 424-1 between the gate pad and the first gate bus segment 422-1 to electrically connect the gate pad 410 to the first gate bus segment 422-1. The gate resistor 430 represents the only electrical connection between the gate pad 410 and the gate bus 420. Thus, when gate current is applied to gate pad 410 from an external source, the entire gate current will flow through gate resistor 430, then to gate bus 420, and from the gate bus to the gate finger (not shown). The current path from the gate pad 410 through the gate resistor 430 to the gate bus 420 can best be seen in the enlarged view of fig. 11B.

A measurement pad 440 is provided to allow for an accurate measurement of the lumped gate resistance 430. Probes may be placed on the gate pad 410 and the gauge pad 440 to measure the resistance of the lumped gate resistor 430.

Fig. 12A is a schematic plan view of a power semiconductor device 500 according to a further embodiment of the invention. Fig. 12B is an enlarged view of a gate pad region of the power semiconductor device 500 of fig. 12A.

Referring to fig. 12A-12B, it can be seen that power semiconductor device 500 is very similar to power semiconductor device 400 of fig. 11A-11B. Special purposeIn addition, the power semiconductor device 500 includes a gate pad 510, a gate bus 520 including gate bus segments 522-1 through 522-7, a gauge pad 540, and a source metallization 550, all of which are located in the same location as corresponding elements of the power semiconductor device 400. The power semiconductor device 500 differs from the power semiconductor device 400 in that the large lumped gate resistor 430 of the power semiconductor 400 is replaced in the power semiconductor device 500 by a plurality of smaller lumped gate resistors 530-1 to 530-10. A smaller lumped gate resistor 530 extends between the gate pad 510 and the gate bus 520 across either the first gap 524-1 or the second gap 524-2 between the gate pad 510 and the gate bus segments 522-1, 522-2, respectively. The gate resistor 530 electrically connects the gate pad 510 to the gate bus 520. The gate resistors 530 are spaced apart from each other by a dielectric pattern (i.e., the gaps 524-1, 524-2 are filled with the gate resistors 530 and a dielectric material (not shown)). Each gate resistor 530 has a length L _g Width W _g And thickness T _g . The length refers to the distance that the gate resistor 530 extends along an axis parallel to the major surface of the semiconductor layer structure of the device and perpendicular to the edge of the gate pad 510 from which the gate resistor 530 extends. In other words, the length direction of each gate resistor 530 is the direction extending through the gap 524. Since the first gap 524-1 and the second gap 524-2 extend in different vertical directions, a length direction of the gate resistor 530 extending through the first gap 524-1 is perpendicular to a length direction of the gate resistor 530 extending through the second gap 524-2. The width of each gate resistor 530 refers to the distance that the gate resistor 530 extends along an axis parallel to the major surface of the semiconductor layer structure of the device and perpendicular to the length of the gate resistor 530. The thickness of the gate resistor 530 refers to the extent of the gate resistor in a direction perpendicular to the main surface of the semiconductor layer structure. In the embodiment of fig. 12A-12B, each gate resistor 530 is approximately the same length as it is wide.

When a gate current is applied to the gate pad 510 from an external source, the gate current will split such that a corresponding portion of the gate current flows through the corresponding gate resistor 530 to the gate bus 520 and from the gate bus 520 to the gate finger (not shown). Since the dimensions of each gate resistor 530 are approximately the same, a similar amount of gate current will flow through each gate resistor 530, but the amount of current will have some variation due to the difference in resistance of the gate bus 520 seen at each gate resistor 530.

Fig. 13A is a schematic plan view of another conventional power semiconductor device 600. Fig. 13B is an enlarged view of a gate pad region of the conventional power semiconductor device 600 of fig. 13A. Fig. 13C is an enlarged view of a portion of the lumped gate resistor 630 included in the conventional power semiconductor device 600 of fig. 13A.

Referring to fig. 13A-13B, a conventional power semiconductor device 600 includes a gate pad 610, a gate bus 620, a single lumped gate resistor 630, a metering pad 640, and a source metallization 650. The metering pad 640 is not actually part of the conventional power semiconductor device 600, but represents an additional feature that is included to allow accurate measurement of gate resistance. In device 600, gate pad 610 is located beside a first side edge of device 600, approximately midway between two other side edges of device 600. The gate bus 620 includes a plurality of gate bus segments 622-1 through 622-10 that are interconnected to form a continuous gate bus structure that extends around a majority of the periphery of the power semiconductor device 600 and also extends into the interior of the device when viewed in plan. The first through fifth segments 622-1 through 622-5 of the gate bus 620 are spaced apart from the gate pad 610 by respective first through fifth gaps 624-1 through 624-5. A single lumped gate resistor 630 is inserted in a portion of the first gap 624-1 between the gate pad 610 and the first gate bus segment 622-1 to electrically connect the gate pad 610 to the gate bus 620. The gate resistor 630 is the only electrical connection between the gate pad 610 and the gate bus 620, so all of any gate current applied to the gate pad 610 from an external source will flow through the gate resistor 630 to the gate bus 620 and from the gate bus 620 to the gate finger (not shown).

The lower portion of the gate pad 610 is wider than the upper portion of the gate pad 610 such that the gate pad 610 has an inverted L shape (and may alternatively have an L shape, for example). Referring to fig. 13C, an enlarged plan view of the gate resistor 630 is shown. As can be seen, in an example embodiment, the gate resistor has a length of X microns and a width of about 4X to 8X microns.

Fig. 14A is a schematic plan view of a power semiconductor device 700 according to yet a further embodiment of the invention. Fig. 14B is an enlarged view of a gate pad region of the power semiconductor device 700 of fig. 14A. Fig. 14C is an enlarged view of several smaller lumped gate resistors 730 included in the power semiconductor device 700 of fig. 14A.

Referring to fig. 14A-14B, it can be seen that power semiconductor device 700 is similar to power semiconductor device 600 of fig. 13A-13C. In particular, power semiconductor device 700 includes gate pad 710, gate bus 720 including gate bus segments 722-1 through 722-10, gauge pad 740, and source metallization 750, all located in the same location as the corresponding elements of power semiconductor device 600. The power semiconductor device 700 differs from the power semiconductor device 600 in that a single large lumped gate resistor 630 of the power semiconductor 600 is replaced in the power semiconductor device 700 by a large number of smaller lumped gate resistors 730. Each smaller lumped gate resistor 730 extends between the gate pad 710 and the gate bus 720. Notably, the lumped gate resistor 730 extends from all six sides of the gate pad 710. It can also be seen from fig. 14A-14B that the lumped gate resistor 730 substantially encloses the gate pad 710 when the semiconductor device 700 is viewed in plan. The gate pad 710 is separated from the gate bus 720 by a continuous gap 724, the continuous gap 724 extending all the way around the gate pad 710. A lumped gate resistor 730 extends across this gap 724. The lumped gate resistor 730 electrically connects the gate pad 710 to the gate bus 720. It should be appreciated that in other embodiments, the lumped gate resistor 730 may extend outward from less than all sides of the gate pad 710. For example, in other embodiments, the lumped gate resistor 730 may extend from one, two, three, four, or five sides of the gate pad 710. As can be seen, the lumped gate resistor 730 may extend outward from opposite sides of the gate pad 710. For example, in the view of fig. 14A, lumped gate resistors 730 extend from the top and bottom sides of the gate pad 710 and/or may extend from the right and left sides of the gate pad 710.

As shown in fig. 14A-14B, some of the lumped gate resistors 730 extend outward from the side edges of the gate pad 710 to contact a portion of the gate bus 720 extending along a first outer edge of the semiconductor device 700 (here, the top outer edge in the plan view of fig. 14A-14B). The lumped gate resistor is typically not located in this position. In some embodiments, a first lumped gate resistor 730 may contact a portion of the gate bus 720 extending along a first outer edge of the semiconductor device 700, while a second lumped gate resistor 730 may contact a second linear segment of the gate bus 720 that contacts the gate bus 720, the second linear segment of the gate bus 720 extending through the active region of the semiconductor device 700 perpendicular to the first linear segment of the gate bus 720. For example, referring to fig. 14A-14B, a first lumped gate resistor 730 (which is one of four lumped gate resistors 730) extends from a side edge of the gate pad 710 to contact a portion of the gate bus segment 722-3 that extends along an outer edge of the semiconductor device 700, while a second lumped gate resistor 730 (which is one of six lumped gate resistors 730) contacts the gate bus segment 722-1, the gate bus segment 722-1 in turn contacts the gate bus segment 722-2, wherein the gate bus segment 722-2 extends perpendicular to the gate bus segment 722-1 and extends through an active region of the semiconductor device 700.

In some embodiments, the semiconductor device 700 may include at least four lumped gate resistors 730. In other embodiments, the semiconductor device 700 may include at least eight lumped gate resistors 730, at least twelve lumped gate resistors 730, at least sixteen lumped gate resistors 730, at least twenty lumped gate resistors. 730, or at least thirty-two lumped gate resistors 730.

The lumped gate resistors 730 are spaced apart from each other by a dielectric pattern. In other words, a dielectric material (e.g., silicon dioxide) is deposited on each pair of adjacent lumped gatesResistor 730 is provided between. The lumped gate resistors 730 may be spaced apart from each other by approximately equal amounts to improve heat dissipation. By having the lumped gate resistor 730 extend from all six sides of the gate pad 710, the heat dissipation performance of the power semiconductor device 700 may be improved. Each gate resistor 730 has a length L _g Width W _g And thickness T _g These are defined in the manner discussed above with reference to gate resistor 530. Length L of each gate resistor 730 _g Can be greater than its width W _g (in the depicted embodiment, the length is greater than four times the width).

In some embodiments, the lumped gate resistors 730 may be substantially uniformly spaced apart from adjacent lumped gate resistors 730. Moreover, in some embodiments, the lumped gate resistors 730 may have a width that is less than the spacing between adjacent lumped gate resistors 730. This may enhance heat dissipation. For example, referring to fig. 14C, first, second and third lumped gate resistors 730-1 to 730-3 may extend from a first side of the gate pad 710, wherein the second lumped gate resistor 730-2 is directly adjacent to the first and third lumped gate resistors 730-1 and 730-3 and is located between the first and third lumped gate resistors 730-1 and 730-3. Width W of second lumped gate resistor 730-2 _g (where each lumped gate resistor 730 has the same width) may be less than a first distance D between the first and second lumped gate resistors 730-1 and 730-2 ₁ And the width W of the second lumped gate resistor 730-2 _g Also less than a second distance D between the second 730-2 and third 730-3 lumped gate resistors ₂ . In some embodiments, D ₁ Can be equal to D ₂ . In an example embodiment, L _g May be W _g Three to six times larger. In some embodiments, the first distance D ₁ May be the width W of the second lumped gate resistor 730-2 _g More than two times, more than three times or even more than four times, and/or a second distance D ₂ May be the width W of the second lumped gate resistor 730-2 _g More than two times, more than three times or even four timesThe above.

Fig. 15A and 15B are schematic plan views generally corresponding to fig. 14C, which illustrate how the selection of the aspect ratio of the lumped gate resistor may improve heat dissipation. As shown in fig. 15A, the power semiconductor device 800 has a plurality of lumped gate resistors 830 extending between the gate pad 810 and the gate bus 820. Each gate lumped resistor has a length L of 50 arbitrary units (e.g., microns) _g And a width W of 20 arbitrary units _g And adjacent lumped gate resistors 830 are spaced apart from each other by a distance D _g =70 arbitrary units. Fig. 15B shows a power semiconductor device 800' having the same overall lumped gate resistance as the power semiconductor device 800, but in the power semiconductor device 800', each lumped gate resistor 830' has a length L of 100 arbitrary units (e.g., microns) _g And a width W of 50 arbitrary units _g And adjacent lumped gate resistors 830' are spaced apart from each other by a distance D _g =50 arbitrary units.

As described above, the heat generated in each lumped gate resistor 830 will spread laterally as it propagates through the semiconductor layer structure of the power semiconductor device 800. To maximize heat dissipation, the heat generated by the first lumped gate resistor 830 should not leave through the same portion of the semiconductor layer structure as the heat generated by the second, adjacent lumped gate resistor 830. It is therefore advantageous to arrange adjacent lumped gate resistors sufficiently spaced apart from each other so as to meet this condition.

As can be seen by comparing fig. 15A and 15B, if the total lumped gate resistance is to be kept constant, it is necessary to reduce the length of each lumped gate resistor 830 in order to increase the distance between adjacent lumped gate resistors 830. In the example shown in fig. 15A-15B, by halving the length of the gate resistor 830 'in the power semiconductor device 800', the distance between adjacent gate resistors can be increased from 50 to 70. While tolerances and other considerations may reduce the ability to make the length of the lumped gate resistors too small, in general, in some embodiments it may be advantageous to keep the length not significantly greater than the width of each gate resistor, and in some cases it may be advantageous to have gate resistors with widths greater than their lengths.

Thus, in some embodiments, some or all of the length L of the lumped gate resistor 730 _g May be smaller than the width W of the corresponding lumped gate resistor 730 _g Five times more than before. In other embodiments, some or all of the lumped gate resistors 730 may have a length less than the width W of the corresponding lumped gate resistor 730 _g Is less than or equal to three times that of the above. In some embodiments, substantially all of the lumped gate resistors 730 may have a width W less than their respective widths W _g Length L twice _g . In some embodiments, at least one lumped gate resistor 730 may have a width W less than it _g Length L of (2) _g 。

Referring again to fig. 14A-14C, when a gate current is applied to the gate pad 710 from an external source, the overall gate current will split such that a corresponding portion of the gate current flows through the corresponding gate resistor 730 to the gate bus 720 and from the gate bus 720 to the gate finger (not shown). Since the dimensions of each gate resistor 730 are approximately the same, a similar amount of gate current will flow through each gate resistor 730, but the amount of current will have some variation due to the difference in resistance of the gate bus 720 seen at each gate resistor 730.

To compare the performance of a single large lumped gate resistor with the performance of a plurality of smaller lumped gate resistors, the devices shown in fig. 13A-13C and 14A-14C were fabricated and then subjected to various tests. These tests include dc tests, ripple tests and high frequency tests. During testing, the test device is mounted on the active heatsink.

For DC testing, five DC voltage pulses were applied to the gate, with the pulses applied for 5 seconds and then removed for 5 seconds. It was determined that a 5 second pulse was sufficient to allow the lumped gate resistor(s) to reach a steady state during the heating (on) and cooling (off) intervals. The applied DC voltage is gradually increased until each of the test power semiconductor devices fails. For the pulse test, pulses each of 10 microseconds in duration are applied to the gate of the device under test. The magnitude of the pulse is increased until the device fails.

The power semiconductor device 600 of fig. 13A-13C failed the DC test at an applied voltage of 27.5 volts and a current of 1.5 amps, and therefore failed at a power level of 41.25 watts. In contrast, the power semiconductor device 700 of fig. 14A-14C failed the DC test at an applied voltage of 45 volts and a current of 4.9 amps, and therefore failed at a power level of 220 watts. With respect to the ripple test, the power semiconductor device 600 of fig. 13A-13C failed at a power level between 55 watts and 160 watts over a plurality of samples, while the samples of the power semiconductor device 700 of fig. 14A-14C failed at a power level of approximately 700 watts at all times. These test results indicate that the power semiconductor device 700 of fig. 14A-14C is about four times better robust than the power semiconductor device 600 of fig. 13A-13C.

For high frequency testing, a high frequency pulse is applied to the gate for ten minutes, with the pulse on time being equal to the off time. The test was performed at a switching frequency between 500kHz and 2.5 MHz. The samples of the power semiconductor device 600 of fig. 13A-13C failed at a switching frequency of 2MHz at a temperature between 400-410 ℃. In contrast, the samples of the power semiconductor device 700 of fig. 14A-14C still function at temperatures of 450-500 ℃ at switching frequencies of 2.25-2.5 MHz. Because of the high device temperature, testing of these samples ends after some of the devices become desoldered.

It will be appreciated that a semiconductor device according to embodiments of the present invention may have a gate electrode extending on top of the wide bandgap semiconductor layer structure or may have a gate electrode extending within a trench formed in the wide bandgap semiconductor layer structure.

Replacing a single lumped gate resistor with multiple lumped gate resistors is not intuitive for several reasons. When a single large lumped gate resistor is used, etch variations that may occur due to unexpected variations and/or tolerances in the photomask and actual etches will only occur along the outer boundaries of the single lumped gate resistor. Thus, the total amount of variation from the desired value can be reduced or minimized. When a plurality of smaller lumped gate resistors are used instead, the amount of variation increases due to the increase in the total outer boundary. This increase results in a greater variation in the amount of resistance and also increases the likelihood of device failure. Furthermore, the goal of the lumped gate resistor is to provide a pure lumped resistance. The distributed lumped gate resistance gives rise to the possibility that multiple lumped gate resistors will exhibit distributed resistive behavior. Accordingly, those skilled in the art may deviate from the design concept of the present invention. However, the use of a single large lumped gate resistor can significantly raise the temperature of a small region of the semiconductor layer structure, which can lead to premature device failure. Thus, by replacing a single large lumped gate resistor with a plurality of smaller, spaced apart lumped gate resistors, the overall performance of the power semiconductor device may be improved.

The doped polysilicon layer(s) included in a power semiconductor device according to embodiments of the present invention may be used, for example, to form gate fingers, gate resistors, and in some cases, gate bus lines. These layers may be doped during epitaxial growth, by ion implantation, and/or via a diffusion process. Doping these layers via ion implantation may improve the uniformity of the doping profile because the ion implantation process tends to break the polycrystalline layer into smaller crystals and may improve the uniformity of sheet resistance with smaller crystal sizes. Heavily doped ions, such as BF2, may be used because they may break the crystal well into smaller units. Doping via ion implantation with a heavy dopant can improve the uniformity of the gate resistance from a range of 10-20% to a range of 5-10%.

The gate resistor designs disclosed herein may be used for any gate controlled device, including MOSFET, IGBT, JFET, thyristors, GTOs, etc.

A gate metal (e.g., gate pad, gate bus) contacting the lumped gate resistor according to embodiments of the invention may form an ohmic contact with the lumped gate resistor. Suitable metals for forming such ohmic contacts include aluminum, titanium, and/or titanium nitride.

While the semiconductor device discussed above is an n-type device with the source bond pad on its upper side and the drain pad on its bottom side, it should be appreciated that these positions are reversed in a p-type device. Furthermore, while the power MOSFETs described above and other devices described herein are shown as silicon carbide based semiconductor devices, it should be appreciated that embodiments of the present invention are not so limited. Instead, the semiconductor device may include any wide bandgap semiconductor suitable for use in power semiconductor devices, including, for example, gallium nitride-based semiconductor devices, and II-VI compound semiconductor devices.

As used herein, the term "horizontal cross section" refers to a cross section taken along a plane parallel to a plane defined by the bottom surface of the semiconductor layer structure.

The invention has been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout unless explicitly stated otherwise.

It will be understood that, although the terms first and second are used herein to describe various regions, layers and/or elements, these regions, layers and/or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Accordingly, a first region, layer, or element discussed below could be termed a second region, layer, or element, and, similarly, a second region, layer, or element could be termed a first region, layer, or element without departing from the scope of the present invention.

Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the "lower" side of another element would then be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" may include the orientations of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" the other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Herein, the term "plurality" means "at least two". In this context, two elements of a semiconductor device "vertically" overlap if an axis perpendicular to a main surface of the semiconductor layer structure of the semiconductor device extends through the two elements.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

It will be appreciated that the embodiments disclosed herein may be combined. Thus, features depicted and/or described with respect to the first embodiment may be included in the second embodiment as well, and vice versa.

Although the above embodiments have been described with reference to particular figures, it should be understood that some embodiments of the invention may include additional and/or intervening layers, structures, or elements, and/or that a particular layer, structure, or element may be deleted. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. As such, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims

1. A semiconductor device, comprising:

a wide bandgap semiconductor layer structure;

a gate pad on the wide bandgap semiconductor layer structure;

a plurality of gate fingers on the wide bandgap semiconductor layer structure; and

a plurality of lumped gate resistors electrically coupled between the gate pads and the gate fingers.

2. The semiconductor device of claim 1, further comprising a gate bus, wherein each lumped gate resistor is connected between a gate pad and the gate bus.

3. The semiconductor device of claim 2, wherein at least two of the plurality of lumped gate resistors extend outwardly from a side edge of the gate pad to contact a portion of the gate bus line extending along the first outer edge of the semiconductor device.

4. The semiconductor device of claim 1, wherein a first subset of the plurality of lumped gate resistors extend outward from a first side of the gate pad and a second subset of the plurality of lumped gate resistors extend outward from a second side of the gate pad.

5. The semiconductor device of claim 4, wherein a third subset of the plurality of lumped gate resistors extend outward from a third side of the gate pad opposite the first side.

6. The semiconductor device of claim 5, wherein a fourth subset of the plurality of lumped gate resistors extend outward from a fourth side of the gate pad opposite the second side.

7. The semiconductor device of any of claims 1-6, wherein at least a respective one of the plurality of lumped gate resistors extends outwardly from each side of the gate pad when the semiconductor device is viewed in plan.

8. The semiconductor device of any of claims 1-6, wherein the lumped gate resistor extends outwardly from and substantially surrounds the gate pad when the semiconductor device is viewed in plan.

9. The semiconductor device of any of claims 1-6, wherein the plurality of lumped gate resistors includes a first lumped gate resistor, a second lumped gate resistor, and a third lumped gate resistor each extending from a gate pad, wherein the second lumped gate resistor is directly adjacent to and between the first and third lumped gate resistors, wherein a width of the second lumped gate resistor is less than a first distance between the first and second lumped gate resistors, and a width of the second lumped gate resistor is also less than a second distance between the second and third lumped gate resistors.

10. The semiconductor device of claim 9, wherein the first distance is greater than twice a width of the second lumped gate resistor and the second distance is greater than twice the width of the second lumped gate resistor.

11. The semiconductor device of claim 9, wherein the first distance is greater than three times a width of the second lumped gate resistor and the second distance is greater than three times the width of the second lumped gate resistor.

12. A semiconductor device as claimed in any one of claims 9 to 11, wherein the length of the second lumped gate resistor is at least twice the width of the second lumped gate resistor.

13. A semiconductor device as claimed in any one of claims 9 to 12, wherein the length of the second lumped gate resistor is less than five times the width of the second lumped gate resistor.

14. A semiconductor device as claimed in any one of claims 9 to 13, wherein the length of the second lumped gate resistor is less than the width of the second lumped gate resistor.

15. The semiconductor device of any of claims 3-6, wherein each of the plurality of lumped gate resistors has a respective length that is less than three times a width of the respective lumped gate resistor.

16. The semiconductor device of any of claims 1-15, wherein the semiconductor device comprises a trench MOSFET, and each of the gate fingers is formed in a respective one of a plurality of gate trenches.

17. The semiconductor device of any of claims 1-6, wherein the lumped gate resistors are spaced apart from one another such that heat generated in adjacent pairs of lumped gate resistors during normal operation of the semiconductor device is substantially dissipated from the semiconductor device through different portions of the semiconductor layer structure.

18. The semiconductor device of any of claims 1-6, wherein the semiconductor layer structure has a thickness D and a thermal diffusion angle α, and wherein facing sides of adjacent lumped gate resistors are spaced apart from each other by at least 2 x D x tan (α).

19. The semiconductor device of any of claims 1-6, further comprising a first switch coupled in series with a first one of the lumped gate resistors between a gate pad and a gate finger, and a second switch coupled in series with a second one of the lumped gate resistors between a gate pad and a gate finger.

20. The semiconductor device of claim 19, wherein the first switch comprises a diode implemented within the first gate resistor.

21. The semiconductor device of claim 19, wherein the first switch comprises a first diode that allows current to flow from the gate pad to the gate finger when forward biased, and the second switch comprises a second diode that allows current to flow from the gate finger to the gate pad when forward biased.

22. The semiconductor device of claim 19, wherein the semiconductor device has a first total gate resistance value for gate current flowing from the gate pad to the gate finger and has a second total gate resistance value for gate current flowing from the gate finger to the gate pad, wherein the second total gate resistance value is different from the first total gate resistance value.

23. The semiconductor device of any one of claims 1-22, wherein the gate pad has an inverted L-shape or an L-shape when viewed in plan.

24. A semiconductor device, comprising:

a wide bandgap semiconductor layer structure;

a gate pad on the wide bandgap semiconductor layer structure;

a gate bus on the wide bandgap semiconductor layer structure; and

A lumped gate resistor extending between the gate pad and a portion of the gate bus line extending adjacent the first outer edge of the semiconductor device.

25. The semiconductor device of claim 24, wherein at least two of the plurality of lumped gate resistors extend outwardly from the first outer edge of the semiconductor device.

26. The semiconductor device of claim 24, wherein the lumped gate resistor is one of a plurality of lumped gate resistors extending between the gate pad and the gate bus, and wherein a first subset of the plurality of lumped gate resistors extends outward from a first side of the gate pad facing the first outer edge of the semiconductor device and a second subset of the plurality of lumped gate resistors extends outward from a second side of the gate pad.

27. The semiconductor device of claim 26, wherein a third subset of the plurality of lumped gate resistors extend outward from a third side of the gate pad opposite the first side.

28. The semiconductor device of claim 27, wherein a fourth subset of the plurality of lumped gate resistors extend outward from a fourth side of the gate pad opposite the second side.

29. The semiconductor device of claim 26, wherein at least a respective one of the plurality of lumped gate resistors extends outwardly from each side of the gate pad when the semiconductor device is viewed in plan.

30. The semiconductor device of claim 26, wherein the lumped gate resistor extends outwardly from and substantially surrounds the gate pad when the semiconductor device is viewed in plan.

31. The semiconductor device of any of claims 24-30, wherein the lumped gate resistor is a fourth lumped gate resistor of a plurality of lumped gate resistors extending between the gate pad and the gate bus line, and wherein the plurality of lumped gate resistors further comprises a first lumped gate resistor, a second lumped gate resistor, and a third lumped gate resistor each extending from the gate pad, wherein the second lumped gate resistor is directly adjacent to and between the first and third lumped gate resistors, wherein a width of the second lumped gate resistor is less than a first distance between the first and second lumped gate resistors, and a width of the second lumped gate resistor is also less than a second distance between the second and third lumped gate resistors.

32. The semiconductor device of claim 31, wherein the first distance is greater than twice a width of the second lumped gate resistor and the second distance is greater than twice the width of the second lumped gate resistor.

33. The semiconductor device of claim 31, wherein the first distance is greater than three times a width of the second lumped gate resistor and the second distance is greater than three times the width of the second lumped gate resistor.

34. The semiconductor device of claim 31 wherein a length of the second lumped gate resistor is less than five times a width of the second lumped gate resistor.

35. The semiconductor device of claim 31, wherein a length of the second lumped gate resistor is less than a width of the second lumped gate resistor.

36. A semiconductor device as claimed in any one of claims 24 to 35, wherein the semiconductor layer structure has a thickness D and a thermal diffusion angle α, and wherein facing sides of the first and second lumped gate resistors are spaced apart from each other by at least 2 x D x tan (α).

37. The semiconductor device of any of claims 24-36, wherein the lumped gate resistor is one of a plurality of lumped gate resistors extending between the gate pad and the gate bus line and the lumped gate resistors are spaced apart from one another such that heat generated in adjacent pairs of lumped gate resistors during normal operation of the semiconductor device is substantially dissipated from the semiconductor device through different portions of the semiconductor layer structure.

38. The semiconductor device of any of claims 24-37, wherein the lumped gate resistor is one of a plurality of lumped gate resistors extending between a gate pad and a gate bus, the semiconductor device further comprising a first switch coupled in series with a first one of the lumped gate resistors between a gate pad and a gate finger, and a second switch coupled in series with a second one of the lumped gate resistors between a gate pad and a gate finger.

39. The semiconductor device of claim 38, wherein the first switch comprises a first diode that allows current to flow from the gate pad to the gate finger when forward biased, and the second switch comprises a second diode that allows current to flow from the gate finger to the gate pad when forward biased.

40. The semiconductor device of claim 38, wherein the semiconductor device has a first total gate resistance value for gate current flowing from the gate pad to the gate finger and has a second total gate resistance value for gate current flowing from the gate finger to the gate pad, wherein the second total gate resistance value is different from the first total gate resistance value.

41. A semiconductor device, comprising:

a wide bandgap semiconductor layer structure;

a gate pad on the wide bandgap semiconductor layer structure; and

a plurality of lumped gate resistors, each electrically coupled to the gate pad, at least a respective pair of the plurality of lumped gate resistors extending outwardly from each of at least three sides of the gate pad when the semiconductor device is viewed in plan.

42. The semiconductor device of claim 41, further comprising a gate bus, wherein each lumped gate resistor is connected between a gate pad and the gate bus.

43. The semiconductor device of claim 42, wherein at least two of the plurality of lumped gate resistors extend outwardly from a side edge of the gate pad to contact a portion of the gate bus line extending along the first outer edge of the semiconductor device.

44. The semiconductor device of claim 41, wherein another one of the plurality of lumped gate resistors extends outward from the fourth side of the gate pad.

45. The semiconductor device of claim 41 wherein at least a respective one of the plurality of lumped gate resistors extends outwardly from each side of the gate pad when the semiconductor device is viewed in plan.

46. The semiconductor device of any of claims 41-45, wherein the plurality of lumped gate resistors includes a first lumped gate resistor, a second lumped gate resistor, and a third lumped gate resistor each extending from a gate pad, wherein the second lumped gate resistor is directly adjacent to and between the first and third lumped gate resistors, wherein a width of the second lumped gate resistor is less than a first distance between the first and second lumped gate resistors, and the second lumped gate resistor is also less than a second distance between the second and third lumped gate resistors.

47. The semiconductor device of claim 46 wherein the first distance is greater than three times the width of the second lumped gate resistor and the second distance is greater than three times the width of the second lumped gate resistor.

48. The semiconductor device of claim 46 wherein a length of the second lumped gate resistor is less than a width of the second lumped gate resistor.

49. The semiconductor device of claim 46 wherein each of the plurality of lumped gate resistors has a respective length that is less than three times a width of the respective lumped gate resistor.

50. The semiconductor device of any of claims 41-49, further comprising a first switch coupled in series with a first one of the lumped gate resistors between a gate pad and a gate finger, and a second switch coupled in series with a second one of the lumped gate resistors between a gate pad and a gate finger.

51. A semiconductor device, comprising:

a gate pad;

a plurality of gate fingers;

a first gate resistor and a first switch coupled between the gate pad and the gate finger.

52. The semiconductor device of claim 51, wherein the first switch comprises a diode.

53. The semiconductor device of claim 52, wherein the diode is implemented within the first gate resistor.

54. The semiconductor device of any of claims 51-53, further comprising a second gate resistor and a second switch coupled between the gate pad and the gate finger.

55. The semiconductor device of claim 54, wherein the first switch comprises a first diode that allows current to flow from the gate pad to the gate finger when forward biased, and the second switch comprises a second diode that allows current to flow from the gate finger to the gate pad when forward biased.

56. The semiconductor device of claim 54, wherein the semiconductor device has a first total gate resistance value for gate current flowing from the gate pad to the gate finger and has a second total gate resistance value for gate current flowing from the gate finger to the gate pad, wherein the second total gate resistance value is different from the first total gate resistance value.

57. The semiconductor device of claim 55 wherein the first gate resistor comprises a first section and a second section forming a first diode, wherein the first section comprises an n-type semiconductor material and the second section comprises a p-type semiconductor material.

58. The semiconductor device of claim 57 wherein the first gate resistor further comprises a third section comprising a p-type semiconductor material, wherein the first section is located between the second section and the third section.

59. The semiconductor device of claim 58, wherein the second gate resistor comprises a fourth section, a fifth section, and a sixth section, the fourth section comprising an n-type semiconductor material, and the fifth section and the sixth section comprising a p-type semiconductor material, wherein the fourth section is located between the fifth section and the sixth section, and wherein the fourth section and the sixth section form the second diode.

60. The semiconductor device of claim 59, wherein the second section is closer to the gate pad than the third section and the fifth section is closer to the gate pad than the sixth section.

61. The semiconductor device of claim 60, further comprising:

a first metal connector shorting the first section to the third section; and

and a second metal connector shorting the fourth section to the fifth section.

62. The semiconductor device of any of claims 51-61, wherein the first gate resistor comprises a first section of n-type semiconductor material and a second section of p-type semiconductor material.

63. The semiconductor device of claim 62, wherein the first section directly contacts the second section.

64. The semiconductor device of claim 63 wherein the first gate resistor further comprises a third section of p-type semiconductor material, wherein the first section is located between the second section and the third section.

65. The semiconductor device of claim 64 wherein the n-type semiconductor material comprises n-type polysilicon and the p-type semiconductor material comprises p-type polysilicon.

66. The semiconductor device of claim 65, further comprising a metal connector shorting the first section to the third section.

67. The semiconductor device of claim 66, wherein the metal connector comprises metallization in a via extending through a dielectric layer formed on an upper surface of the first gate resistor.

68. A semiconductor device, comprising:

a gate pad;

a plurality of gate fingers;

a gate resistor electrically interposed between the gate pad and the gate finger, wherein the gate resistor includes a first section of n-type semiconductor material and a second section of p-type semiconductor material.

69. The semiconductor device of claim 68, wherein the first section directly contacts the second section.

70. The semiconductor device of claim 69 wherein the n-type semiconductor material comprises n-type polysilicon and the p-type semiconductor material comprises p-type polysilicon.

71. The semiconductor device of claim 69 or 70, wherein the gate resistor further comprises a third section of p-type semiconductor material, wherein the first section is located between the second section and the third section.

72. The semiconductor device of claim 71, further comprising a metal connector shorting the first section to the second section.

73. The semiconductor device of claim 72, wherein the metal connector comprises metallization in a via extending through a dielectric layer formed on an upper surface of the gate resistor.

74. The semiconductor device of any of claims 68-73, wherein the n-type semiconductor material and the p-type semiconductor material form a diode within the gate resistor.

75. The semiconductor device of claim 73, wherein the gate resistor is a first gate resistor and the junction between the first section and the second section forms a first diode, the semiconductor device further comprising a second gate resistor and a second diode electrically coupled in parallel with the first gate resistor and the first diode.

76. The semiconductor device of claim 75, wherein the first diode is configured to allow current to flow from the gate pad to the gate finger when forward biased and the second diode is configured to allow current to flow from the gate finger to the gate pad when forward biased.

77. A semiconductor device, comprising:

a gate pad;

a plurality of gate fingers;

a first gate resistor and a first circuit element electrically interposed between the gate pad and the gate finger,

wherein the first circuit element is configured to conduct current only in a first direction between the gate pad and the gate finger.

78. The semiconductor device of claim 77 wherein the first circuit element comprises a first diode.

79. The semiconductor device as defined in claim 78, wherein the first diode is implemented within a first gate resistor.

80. The semiconductor device of any of claims 77-79, further comprising a second gate resistor and a second diode electrically interposed between the gate pad and the gate finger, wherein the second diode is configured to conduct current only in a second direction between the gate pad and the gate finger, the second direction being opposite the first direction.

81. The semiconductor device of claim 80, wherein the second diode is implemented within a second gate resistor.

82. The semiconductor device of claim 79 wherein the first gate resistor comprises a first section of n-type semiconductor material and a second section of p-type semiconductor material.

83. The semiconductor device of claim 82, further comprising a first metal connector shorting a first section of the first gate resistor to a second section of the first gate resistor.

84. The semiconductor device of claim 83 wherein the first section of the first gate resistor directly contacts the second section of the first gate resistor and the n-type semiconductor material comprises n-type polysilicon and the p-type semiconductor material comprises p-type polysilicon.

85. The semiconductor device of claim 83, wherein the metal connector comprises metallization in a via extending through a dielectric layer formed on an upper surface of the first gate resistor.

86. The semiconductor device of claim 82, further comprising:

a wide band gap semiconductor layer structure is provided,

wherein the first gate resistance is located on an upper side of the wide bandgap semiconductor layer structure.

87. The semiconductor device of claim 85 further comprising an internal dielectric pattern directly on an upper side of the first gate resistor.

88. A semiconductor device, comprising:

a gate pad;

a gate bus; and

a gate resistor structure electrically interposed between the gate pad and the gate bus line, the gate resistor structure having a first resistance relative to current flowing from the gate pad to the gate bus line and a second resistance relative to current flowing from the gate bus line to the gate pad, the first resistance being different from the second resistance.

89. The semiconductor device of claim 88, further comprising:

a wide band gap semiconductor layer structure includes an active region having a plurality of unit cell transistors,

wherein the gate pad, gate bus and gate resistor structure are located on the upper side of the wide bandgap semiconductor layer structure.

90. The semiconductor device of claim 89, further comprising an internal dielectric pattern directly on an upper side of the gate resistor.

91. The semiconductor device of any of claims 88-90, wherein the gate resistor structure comprises:

a plurality of first gate resistors;

a plurality of first switches;

a plurality of second gate resistors; and

a plurality of second switches.

92. The semiconductor device of claim 91 wherein each of the first gate resistors and a respective one of the first switches are coupled between a gate pad and a gate finger and each of the second gate resistors and a respective one of the second switches are coupled between a gate pad and a gate finger.

93. The semiconductor device of claim 92 wherein each of the first switches comprises a first diode and each of the second switches comprises a second diode.

94. The semiconductor device of claim 93 wherein each of the first diodes is implemented within a respective one of the first gate resistors and each of the second diodes is implemented within a respective one of the second gate resistors.

95. The semiconductor device defined in claim 94, wherein the first diode is configured to permit current flow from the gate pad to the gate bus line when forward biased and the second diode is configured to permit current flow from the gate bus line to the gate pad when forward biased.

96. The semiconductor device of claim 95, wherein the number of first gate resistors is different than the number of second gate resistors.

97. The semiconductor device of claim 96 wherein each of the first gate resistors is directly adjacent to at least one of the second gate resistors.

98. The semiconductor device of claim 91 wherein each of the first gate resistors and each of the second gate resistors comprises a first section of n-type semiconductor material, a second section of p-type semiconductor material, and a third section of p-type semiconductor material forming an n-p-n junction.

99. The semiconductor device of claim 98, further comprising:

a plurality of first metal connectors, each first metal connector shorting a first section of a respective one of the first gate resistors to a third section of the respective one of the first gate resistors; and

A plurality of second metal connectors, each second metal connector shorting a first section of a respective one of the second gate resistors to a second section of a respective one of the second gate resistors.

100. A semiconductor switching device comprising:

a gate pad;

a plurality of gate fingers; and

a gate resistor structure electrically interposed between the gate pad and the gate finger, the gate resistor structure having a first resistance during device on and a second resistance during device off, the first resistance being different from the second resistance.

101. The semiconductor device of claim 100, further comprising:

a wide bandgap semiconductor layer structure including an active region,

102. The semiconductor device of claim 101, further comprising an internal metal dielectric pattern directly on an upper side of the gate resistor structure.

103. The semiconductor device of claim 100, wherein the gate resistor structure comprises a first gate resistor and a first switch forming a first circuit coupled between the gate pad and the gate finger, and a second gate resistor and a second switch forming a second circuit coupled between the gate pad and the gate finger.

104. The semiconductor device of claim 103 wherein the first switch comprises a first diode that allows current to flow from the gate pad to the gate finger when forward biased and the second switch comprises a second diode that allows current to flow from the gate finger to the gate pad when forward biased.

105. The semiconductor device defined in claim 101, wherein the gate resistor structure comprises a plurality of first gate resistor circuits and a plurality of second gate resistor circuits, each first gate resistor circuit comprising a first gate resistor and a first switch coupled between the gate pad and the gate finger, each second gate resistor circuit comprising a second gate resistor and a second switch coupled between the gate pad and the gate finger, wherein the first gate resistor circuits and the second gate resistor circuits are electrically arranged in parallel with each other.

106. The semiconductor device of claim 103, wherein a combined resistance of all of the first gate resistors is different from a combined resistance of all of the second gate resistors.

107. The semiconductor device of claim 106, wherein the number of first gate resistors is different from the number of second gate resistors.

108. The semiconductor device of claim 106 wherein each of the first gate resistors is directly adjacent to at least one of the second gate resistors.

109. A semiconductor device, comprising:

a gate pad;

a plurality of gate fingers;

a plurality of first gate resistors electrically interposed between the gate pad and the gate finger; and

a plurality of second gate resistors electrically interposed between the gate pad and the gate finger,

wherein during device on time a gate current flowing between the gate pad and the gate finger flows at least predominantly through the first gate resistor and during device off time the gate current flows at least predominantly through the second gate resistor.

110. The semiconductor device of claim 109, further comprising:

a plurality of first diodes configured to control current flowing through the first gate resistor, wherein the first diodes are configured to conduct current only from the gate pad to the gate finger; and

a plurality of second diodes configured to control current flowing through the second gate resistor, wherein the second diodes are configured to conduct current only from the gate fingers to the gate pad.

111. The semiconductor device of claim 109, wherein a total resistance of the second gate resistor differs from a total resistance of the first gate resistor by at least 10%.

112. The semiconductor device of claim 110 wherein each of the first diodes is part of a respective one of the first gate resistors.

113. The semiconductor device of any of claims 109-112, wherein a number of the first gate resistors is different from a number of the second gate resistors.

114. The semiconductor device of any one of claims 109-113, wherein a first resistance of a first one of the first gate resistors is different from a second resistance of a first one of the second gate resistors.

115. The semiconductor device of any one of claims 109-114, wherein each of the first gate resistors is directly adjacent to at least one of the second gate resistors.

116. A semiconductor device, comprising:

a metal gate pad;

a gate bus;

a first gate resistor having a first end directly connected to the metal gate pad and a second end directly connected to the gate bus line; and

A metal connector electrically connects the first interior portion of the first gate resistor to the second interior portion of the gate resistor.

117. The semiconductor device of claim 116, further comprising a first diode integrated within the first gate resistor.

118. The semiconductor device of claim 117, further comprising a second gate resistor and a second diode coupled between the metal gate pad and the gate bus line.

119. The semiconductor device defined in claim 118, wherein the first diode is configured such that it allows current to flow from the metal gate pad to the gate bus line when it is forward biased, and the second diode is configured such that it allows current to flow from the gate bus line to the metal gate pad when it is forward biased.

120. The semiconductor device of claim 119, wherein the semiconductor device has a first resistance between the metal gate pad and the gate bus for signal travel from the metal gate pad to the gate bus, and a second resistance between the metal gate pad and the gate bus for signal travel from the gate bus to the metal gate pad, the second resistance being different from the first resistance.

121. The semiconductor device of claim 119 wherein the first gate resistor and the second gate resistor each comprise a first section of n-type semiconductor material and a second section of p-type semiconductor material.

122. The semiconductor device of any of claims 116-121, wherein the metal connector comprises metallization in a via extending through a dielectric layer formed on an upper surface of the first gate resistor.

123. A semiconductor device, comprising:

a gate pad;

a plurality of gate fingers;

a first conductive path between the gate pad and the gate finger that conducts current during device on, but does not conduct current during device off; and

a second conductive path between the gate pad and the gate finger that conducts current during device off, but does not conduct current during device on.

124. The semiconductor device defined in claim 123, wherein the first conductive path comprises a plurality of first gate resistor circuits disposed electrically in parallel with one another and the second conductive path comprises a plurality of second gate resistor circuits disposed electrically in parallel with one another.

125. The semiconductor device of claim 124, wherein each of the first gate resistor circuits comprises a first gate resistor and a first diode, and each of the second gate resistor circuits comprises a second gate resistor and a second diode.

126. The semiconductor device of claim 125 wherein the number of first gate resistors is different than the number of second gate resistors.

127. The semiconductor device of claim 125 wherein a first resistance of at least one of the first gate resistors is different from a second resistance of at least one of the second gate resistors.

128. The semiconductor device of claim 125 wherein each of the first gate resistors is directly adjacent to at least one of the second gate resistors.

129. The semiconductor device of claim 50, wherein the semiconductor device comprises a trench MOSFET and each of the gate fingers is formed in a respective one of a plurality of gate trenches.

130. The semiconductor device of claim 68, wherein the semiconductor device comprises a trench MOSFET and each of the gate fingers is formed in a respective one of a plurality of gate trenches.

131. The semiconductor device of claim 77, wherein the semiconductor device comprises a trench MOSFET and each of said gate fingers is formed in a respective one of a plurality of gate trenches.