CN117708015A - Control circuit, method and electronic equipment - Google Patents

Abstract

The present disclosure relates to the field of computer technologies, and in particular, to a control circuit, a control method, and an electronic device. The control circuit comprises a first chip and M first devices positioned outside the first chip; the first chip comprises a first chip interface, the first chip interface can transmit data to M first devices based on a first transmission protocol, and the first chip interface can transmit various types of data to a first device D1 in the M first devices. Based on the above, when the first chip performs data transmission by using the first transmission protocol supporting transmission of multiple types of data, a small number of interfaces corresponding to the first transmission protocol can be used to control multiple devices, so that the problem that the bonding pads of the first chip cannot meet requirements is avoided.

Description

Control circuit, method and electronic equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a control circuit, a control method, and an electronic device.

Background

In general, an input/output interface capable of communicating with peripherals controlled by the chip (such as a sensor, a speaker, a camera, a fast-charging chip, and other external devices connected with the chip in a mobile phone) is disposed on the chip in the electronic device. For example, the input/output interface may include a protocol class interface, a general purpose input/output port (General Purpose Input Output, GPIO, also known as a bus expander), and the like. Each GPIO interface has 1 simple control function, so that it not only can transmit GPIO control signals and provide Interrupt (INT) functions, but also can simulate various transmission protocols, so that it can be used as a protocol interface. For example, the GPIO interface may emulate an integrated circuit (Inter-Integrated Circuit, IIC, also known as I2C) interface function, a serial peripheral interface (Serial Peripheral Interface, SPI) function, an integrated circuit built-in audio bus (I2S) interface function, etc., and thus may also be used as an I2C interface, an SPI interface, and an I2S interface.

However, as the characteristics and performance of electronic devices increase, the number of peripherals to which a chip needs to be connected increases, so that the number of input-output interfaces also increases, for example, some chips currently have more than 200 GPIO interfaces, and also increase at an increasing rate of 30 GPIO interfaces per year. However, in a chip, too many input-output interfaces occupy more PADs (PADs). Wherein the bond pads are interfaces that connect the interior of the integrated circuit to the integrated circuit package and are not visible after the package is completed. For example, for GPIO interfaces, each GPIO interface needs to occupy at least one pad for outgoing lines, thereby implementing a simple control function. For another example, for an SPI interface, 4 pads need to be used for outgoing lines for communication transmission with the peripheral devices. And some chips have more than 1000 bonding pads, and the occupied number and area of the bonding pads in the chips are increased along with the increase of the demands of the input and output interfaces, so that the development of the chips is severely restricted. The area of the chip is limited, the area of the chip cannot be infinitely increased, the number of bonding pads and the area requirement are met, and the connection of the chip and more peripheral devices cannot be realized.

Disclosure of Invention

In order to solve the problems, the application provides a control circuit, a control method and an electronic device.

In a first aspect, an embodiment of the present application provides a control circuit, where the control circuit includes a first chip and M first devices located outside the first chip; the first chip comprises a first chip interface, the first chip interface can transmit data to M first devices based on a first transmission protocol, and the first chip interface can transmit various types of data to a first device D1 in the M first devices.

It can be understood that when the first chip performs data transmission by using the first transmission protocol supporting transmission of multiple types of data, a small number of interfaces corresponding to the first transmission protocol can be used to control multiple devices, so that the problem that the bonding pads of the first chip cannot meet requirements is avoided.

In a possible implementation of the first aspect, the device further includes a second chip, where the second chip includes a second chip interface and a third chip interface; the second chip interface is connected with the first chip interface of the first chip, and supports a first transmission protocol; the third chip interface is connected with the first device D1, wherein the interface type of the third chip interface is different from that of the first chip interface.

It is understood that the second chip may be an SPMI extended chip or a SLIMBUS extended chip. For each first device that cannot support the first transmission protocol, the second chip may convert the first data into a data type supported by each device, thereby enabling the first chip to communicate with the plurality of peripherals through a smaller number of pads (e.g., 2).

In a possible implementation of the first aspect, the first transmission protocol includes at least one of a system power management interface protocol and a low power consumption inter-chip serial media bus protocol.

In a possible implementation of the first aspect, the second chip is configured to: and converting the first data received from the second chip interface into second data supported by the third chip interface for transmission, and sending the second data to a first device D1 in the M first devices through the third chip interface.

In a possible implementation manner of the first aspect, the second chip further includes a fourth chip interface, where the fourth chip interface is connected to the first device D2 of the M first devices, and interface types of the fourth chip interface and the first chip interface are different from each other; and the second chip is for: and converting the third data received from the second chip interface into fourth data supported by the fourth chip interface for transmission, and sending the fourth data to the first device D2 through the fourth chip interface.

In a possible implementation of the first aspect, the third chip interface and the fourth chip interface include at least one of the following: an integrated circuit protocol interface, a serial peripheral interface, an integrated circuit built-in audio bus protocol interface, an interrupt interface, a reset interface and a general input/output control interface.

In a possible implementation of the first aspect, the first transmission protocol is a low power consumption inter-chip serial media bus protocol, and the first device is an audio device.

In a possible implementation of the first aspect, the control circuit further includes N second devices located outside the first chip, and

the first chip further comprises a fifth chip interface, and the fifth chip interface can transmit data to N second devices based on a fourth transmission protocol, wherein the fifth chip interface can transmit various types of data to a second device H1 in the N second devices; and the first transmission protocol is a system power management interface protocol, the fourth transmission protocol is a low-power consumption inter-chip serial media bus protocol, and the N second devices comprise audio devices.

In a possible implementation of the first aspect, each first device of the M first devices has a first device interface supporting a first transport protocol; the first chip interface is connected with first device interfaces of the M first devices.

In a second aspect, an embodiment of the present application provides a control method applied to a control circuit, where the control circuit includes a first chip and M first devices located outside the first chip, and the first chip includes a first chip interface; the method comprises the following steps: the first chip interface is capable of transmitting data to the M first devices based on the first transmission protocol, and the first chip interface is capable of transmitting a plurality of types of data to a first device D1 of the M first devices.

In a third aspect, embodiments of the present application provide an electronic device comprising a control circuit as in the first aspect and any of the various possible implementations of the first aspect.

Drawings

Fig. 1 is a schematic diagram showing that a main control chip 01 and peripheral devices in a mobile phone 100 are connected through input and output interfaces respectively according to some embodiments of the present application;

fig. 2 is a schematic diagram of a control circuit of a main control chip 01 and peripheral devices in another mobile phone 100 respectively connected through input/output interfaces according to some embodiments of the present application;

FIG. 3 illustrates a core layer diagram in a software architecture of a handset 100, according to some embodiments of the application;

FIG. 4 is a schematic diagram of a process of a system (software system) of a mobile phone 100 controlling an SPMI interface in a master control chip to communicate with an SPMI extended chip using an SPMI protocol according to some embodiments of the present application;

FIG. 5A illustrates an interrupt handling process schematic diagram according to some embodiments of the present application;

FIG. 5B illustrates a core layer diagram in another software architecture of the handset 100, according to some embodiments of the application;

fig. 6 is a schematic diagram of a control circuit of a main control chip 01 and peripheral devices in a mobile phone 100 directly connected through an input/output interface according to some embodiments of the present application;

fig. 7 is a schematic diagram illustrating a hardware structure of a mobile phone 100 according to some embodiments of the present application.

Detailed Description

Illustrative embodiments of the present application include, but are not limited to, a control circuit, method, and electronic device.

The following description is made in detail with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a connection between a main control chip 01 and peripheral devices in a mobile phone 100 through input/output interfaces. It will be appreciated that different peripherals may be transported using different protocols, thereby implementing different functions. It can be understood that different interface types of the main control chip 01 support corresponding functions. For convenience of understanding, when the GPIO interface supports a specific function, the GPIO interface is considered to be a corresponding function interface. For example, when the GPIO interface supports an interrupt function, the GPIO interface is considered to be an interrupt interface; when the GPIO interface supports the reset function, the GPIO interface is considered as a reset interface; when the GPIO interface supports the I2C function, the GPIO interface is considered as an I2C interface; when the GPIO interface supports the GPIO control function, the GPIO interface is considered to be a GPIO control interface or the like.

It can be understood that the above-mentioned peripheral devices can be specifically various sensors, various display devices, various audio devices, cameras, radio frequency control devices, quick-charging chips, and the like. The sensor may include a pressure sensor, a gyroscope sensor, a barometric sensor, a fingerprint sensor, a temperature sensor, etc., which are not described herein. The display device may include an Organic Light-Emitting Diode (OLED) or the like, and will not be described herein. The audio device may include a speaker, microphone, smart power amplifier (Smart PA), etc., and will not be described in detail herein.

As shown in fig. 1, when the peripheral 1 uses the I2C transmission protocol to transmit, the peripheral 1 needs to be connected with the main control chip 01 by using 4 signal connection lines, wherein, the I2C interface of the main control chip 01 supporting the I2C protocol transmission needs 2 lines to transmit data with the peripheral 1, the Interrupt interface of the main control chip 1 supporting the Interrupt (INT) function needs 1 line to transmit with the peripheral 1, the Reset interface of the main control chip 1 supporting the Reset (RST) function needs 1 line to transmit with the peripheral 1, that is, at least 4 pads are occupied inside the main control chip 01 to realize the I2C data transmission, reset and Interrupt between the main control chip 01 and the peripheral 1. Similarly, when the peripheral 2 and the main control chip 01 transmit by using the SPI transmission protocol, 6 signal connection lines are required to connect the peripheral 2 and the main control chip 01, wherein 4 lines are required for the SPI interface of the main control chip 01 supporting the SPI transmission with the peripheral 2, 1 line is required for the INT interface of the main control chip 01 supporting the INT signal function with the peripheral 2, 1 line is required for the RST interface of the main control chip 01 supporting the RST function with the peripheral 2, and at least 6 pads are also occupied in the main control chip 01 to realize SPI data transmission, reset and interrupt between the main control chip 01 and the peripheral 2. For the peripheral 3, the peripheral 3 and the main control chip 01 communicate through GPIO control interfaces, 3 interfaces are shown in the figure, and each interface is used for supporting a GPIO control function, that is, each interface is a GPIO control interface, so that 3 connection lines are used for transmission. For the peripheral 4, it is necessary to connect it with the main control chip 01 using 6 signal connection lines. It will be appreciated that 3 wires are required for the I2S interface of the main control chip 01 and the peripheral 4 supporting the transmission of the integrated circuit built-in audio bus protocol ((Inter-IC Sound, I2S), 1 wire is required for the reset interface of the main control chip 01 and the peripheral 4 supporting the RST function, and 2 wires are required for the I2C interface of the main control chip 01 and the peripheral 4, if the INT function needs to be generated, 1 wire is required to support the INT signal (not shown in the figure).

It will be appreciated that, for each peripheral device, the main control chip 01 needs to provide a functional interface to connect with the corresponding peripheral device, and for each interface provided by the main control chip 01 (at least 1 signal connection line is required for each interface), at least 1 bonding pad needs to be provided inside the main control chip 01 to connect with the peripheral device. Therefore, for a plurality of peripheral devices, the main control chip 01 needs to occupy a larger number of bonding pads and area. However, the number and the area of the bonding pads are limited, and the area of the main control chip 01 cannot be infinitely increased to meet the number and the area requirement of the bonding pads, so that the main control chip 01 is limited to be connected with more peripheral devices.

It will be appreciated that the SPI interface, I2S interface, I2C interface, and GPIO control interface mentioned above cannot provide interrupt and reset functions, and at least 1 pad is required for each 1 functional interface used in the host chip during transmission, for example, at least 2 pads are required for providing the SPI interface, I2S interface, and I2C interface, and at least 1 pad is required for implementing the integrated interrupt and reset functions. Therefore, when the main control chip provides the SPI interface, the I2S interface and the I2C interface to respectively transmit the SPI protocol, the I2S protocol and the I2C protocol with the peripheral, the main control chip needs to use an additional interface (i.e. an additional signal connecting wire) to realize the interrupt and reset functions besides the signal connecting wire required by the protocol itself, i.e. more bonding pads are required to be used for communication.

Therefore, the present application proposes a technical solution, in which a plurality of peripherals are connected by adopting a protocol capable of integrating a plurality of functions, that is, an interface supporting the protocol transmission can transmit data with a plurality of functions, for example, a system power management interface (System Power Management Interface, SPMI) protocol capable of integrating an interrupt function and a reset function is adopted to realize connection of a main control chip and a plurality of peripherals, so that connection lines of interrupt signals and reset signals required by original transmission of a plurality of peripherals can be reduced. Therefore, the main control chip is connected with more peripheral devices under the condition that fewer bonding pads are occupied.

In some embodiments, the SPMI interface supporting SPMI protocol transmission in the main control chip can realize transmission of multiple types (functions) of data only by connecting two signal connection lines with the peripheral, so that data communication with multiple peripheral can be supported by only two pads, wherein the functions include interrupt and reset.

In addition, when the audio data needs to be transmitted, in order to obtain a better effect, an audio protocol capable of integrating a plurality of interrupt and reset functions can be adopted for transmission, for example, a Serial-power Inter-chip Media Bus (SLIMBUS) protocol is adopted for connecting a plurality of peripherals, so that when the master chip uses the SLIMBUS interface for transmission, the master chip realizes more functions when being connected with more supported audio peripherals under the condition of occupying fewer bonding pads. For example, when the I2S protocol transmission is originally performed, besides the signal connection lines required by the protocol itself, the main control chip is required to provide additional signal connection lines or additional function interfaces to implement the interrupt and reset functions, and at this time, when the SLIMBUS protocol transmission is utilized, the main control chip is not required to provide additional signal connection lines or additional function interfaces to implement the interrupt and reset functions.

It may be appreciated that in some embodiments, when the SPMI protocol and the SLIMBUS protocol are utilized to communicate with the peripheral device, the SPMI extended chip or the SLIMBUS extended chip needs to be used for data conversion, so that for the peripheral device incapable of supporting the SPMI protocol or the SLIMBUS, the SPMI extended chip or the SLIMBUS extended chip may convert SPMI data or SLIMBUS data into data types supported by each peripheral device, respectively, so as to enable the master control chip to communicate with a plurality of peripheral devices through a small number of pads (for example, 2) for transmission, for example, the SPMI extended chip converts SPMI data into I2C data, SPI data, GPIO control data, I2S data, and so on, respectively.

When a certain peripheral is interrupted, the SPMI expansion chip can also transmit an interrupt signal received from the peripheral to the main control chip 01 through an SPMI protocol. When the main control chip 01 needs to reset a certain peripheral, the SPMI data can be converted into reset data by utilizing the SPMI extension chip through the SPMI protocol, so that the corresponding peripheral is reset.

For example, as the control circuit shown in fig. 2, it is assumed that the peripheral 11, the peripheral 21, and the peripheral 31 do not support the SPMI protocol, but support transmission of I2C data, SPI data, and GPIO control data, respectively. An SPMI interface on the main control chip 01 is connected to one end of the SPMI extended chip 02 by using 2 signal connection lines (only 1 is shown in the figure). The other end of the SPMI extended chip 01 is then connected to the peripheral 11, the peripheral 21 and the peripheral 31 by connecting wires, which respectively provide different functional interfaces. Specifically, the SPMI extension chip 02 converts SPMI data into I2C data, and connects and transmits the I2C data with the peripheral device 11 by using an I2C interface; the SPMI expansion chip 02 converts SPMI data into GPIO control data, and is connected and transmitted with the peripheral equipment 21 by using an SPI interface; the SPMI extension chip 02 converts SPMI data into GPIO control data, and connects and transmits the GPIO control data to the peripheral device 31 by using the GPIO control interface. In addition, for each peripheral 11, peripheral 21 and peripheral 31, the spmi extended chip 01 also needs to provide an interrupt interface and a reset interface for transmission with each peripheral, so as to realize interrupt and reset functions. It should be understood that fig. 2 is only a schematic illustration, and does not represent a specific connection manner, for example, the SPMI extended chip 01 may also provide the same interface to each peripheral device supporting the same type of data (not shown in the figure).

For another example, as shown in fig. 2, for a plurality of peripherals not supporting the SLIMBUS protocol, but only an audio class peripheral 41 and an audio class peripheral 42 supporting the I2S protocol, etc., 2 signal connection lines of the SLIMBUS interface on the main control chip 01 are connected to one end of the SLIMBUS expansion chip, and then the other end of the SLIMBUS expansion chip is connected to the plurality of peripherals. It will be appreciated that the connection between the peripheral device and the SLIMBUS expansion chip is various and not illustrated herein. For example, when the peripheral 41 of the audio class and the peripheral 42 of the audio class support the same type of data, the peripheral 41 of the audio class and the peripheral 42 of the audio class may be connected to the same interface (not shown in the figure) of the SLIMBUS extension chip, or may be connected to different interfaces in the SLIMBUS extension chip as shown in the figure, respectively, which is not required. When the audio class peripheral 41 and the audio class peripheral 42 support different types of data, the audio class peripheral 41 and the audio class peripheral 42 need to be connected to different function (type) interfaces (not shown in the figure) of the SLIMBUS expansion chip. It will be appreciated that for the audio class peripheral 41 and the audio class peripheral 42 as shown in fig. 2, the SLIMBUS expansion chip may convert SLIMBUS data into I2S data. It can be appreciated that the SLIMBUS expansion chip may also convert SLIMBUS data into I2C data, etc., which will not be described in detail herein. Since the SLIMBUS interface on the main control chip 01 occupies only 2 pads, the use of pads on the main control chip can be reduced. It will be appreciated that for the audio class peripheral 41, the audio class peripheral 42, the SLIMBUS extension chip also needs to provide an interrupt interface or a reset interface to support the interrupt or reset functions, i.e. an interrupt signal line, a reset signal line (both not shown in the figure) are also required between each peripheral and the SLIMBUS extension chip, respectively, for supporting the interrupt and reset functions.

It can be understood that, by communicating the plurality of peripherals which do not support the SPMI and SLIMBUS protocols with the main control chip 01 through the SPMI extended chip and the SLIMBUS extended chip, the main control chip 01 can adopt the same SPMI interface and SLIMBUS interface to transmit with the plurality of peripherals, so that the pad area of the chip can be reduced, the integration level of the bus can be improved, and the utilization rate of the chip can be improved. And, the software module that drives SPMI and SLIMBUS interface work can set up in normally open (Always On Processor, AOP) subsystem to guarantee that electronic equipment is under the dormancy state, also can make the peripheral hardware controlled normally.

It can be appreciated that the SPMI and SLIMBUS protocols have faster transmission rates and can also support transmissions with multiple devices well. In addition, for the folding machine, because the function is complex, the main and auxiliary boards need more connecting wires, and by adopting the mode, the integration level of the bus can be improved, and the transmission wires between the main and auxiliary boards are reduced.

It can be understood that the number of the SPMI extension chip connected to one SPMI interface and SLIMBUS interface of the main control chip 01 and the number of the peripherals communicated by the SLIMBUS extension chip are not particularly limited herein, and may be 1, 2, 3, or.

The control scheme mentioned in the present application may be applied to electronic devices other than the above-mentioned mobile phone 100, including, but not limited to, mobile phones, tablet computers, vehicle devices, augmented Reality (Augmented Reality, AR)/Virtual Reality (VR) devices, ultra-mobile Personal Computer (UMPC), netbooks, servers, and the like, which are not limited in this disclosure.

It will be appreciated that when the hardware changes, the software architecture of the electronic device changes.

It can be appreciated that the software modules on the main control chip for controlling the SPMI interface and the SLIMBUS interface to perform corresponding protocol transmission, such as the SPMI architecture and the SLIMBUS architecture, may be located in the AOP subsystem, that is, the software modules for controlling the SPMI protocol and the SLIMBUS protocol transmission may still work when the electronic device is in the sleep state.

The following describes an example of the software system structure of the mobile phone 100.

It will be appreciated that in some embodiments, the software structure of the mobile phone 100 is a multi-layer structure, including an application layer, a framework layer, and a kernel layer in order from top to bottom. The application layer may include a series of application packages, among other things. The framework layer provides an application programming interface (Application Programming Interface, API) and programming framework for application programs of the application layer, the application program framework layer including some predefined functions.

For ease of understanding, fig. 3 illustrates some modules included in a kernel layer in a software architecture of a mobile phone 100 according to some embodiments of the present application.

As shown, the kernel layer 31 provides the underlying control for the various hardware of the handset 100. For example, the kernel layer 31 provides underlying control over some peripherals in the handset 100 shown in the hardware layer 32 in fig. 3. The hardware layer 32 may include various peripherals, for example, may include an SPMI interface 321, an SPMI extended chip 322, a SLIMBUS interface 323, a SLIMBUS extended chip 324, display hardware 325, sensor hardware 326, and charging audio hardware 327, wherein the SPMI interface 321, the SPMI extended chip 322, the SLIMBUS interface 323, and the SLIMBUS extended chip 324 are located on a main control chip.

In some embodiments, as shown in fig. 3, the kernel layer 31 includes a display module 311, a sensor module 312, a charging audio module 313, and an AOP subsystem 314. Among other things, AOP subsystem 314 includes SPMI architecture 3141, SLIMBUS architecture 3142, SPMI extended chip driver module 3143, SLIMBUS extended chip driver module 3144, and so forth. The display module 311, the sensor module 312, and the charging audio module 313 are peripheral software modules corresponding to each peripheral.

Wherein the display module 311 is used for controlling the display device. In some embodiments of the present application, display module 311 includes a driver module for each display screen device that is operable to drive each display screen device in display hardware 325 via AOP subsystem 314, e.g., display module 311 includes a driver module for an organic light emitting diode to drive an OLED to emit light.

The sensor module 312 is used to control the operation of the sensor. In some embodiments of the present application, sensor module 312 includes a drive module for each sensor that is operable to drive operation of a corresponding sensor in sensor hardware 326 via AOP subsystem 314. For example, the sensor module 312 includes a pressure sensor driving module, a gyro sensor driving module, a pneumatic sensor driving module, a fingerprint sensor driving module, a temperature sensor driving module, and the like, for driving the sensors such as the pressure sensor, the gyro sensor, the pneumatic sensor, the fingerprint sensor, the temperature sensor, and the like to operate, respectively.

The charging audio module 313 is used for controlling the charging device and the audio device to work. In some embodiments of the present application, the charging audio module 313 includes a driving module of each charging device and audio device, and may be used to drive each charging device and audio device in the charging audio hardware 327 to operate by means of the AOP subsystem 314, for example, the charging audio module 313 includes a fast charging audio chip driving module, a speaker driving module, a microphone driving module, and so on, for driving the fast charging audio chip, the speaker, the microphone, and so on to operate.

AOP subsystem 314 is a normally open subsystem that is also operable in a dormant state of handset 100.

Specifically, in some embodiments, the AOP subsystem includes an SPMI architecture 3141, a SLIMBUS architecture 3142, an SPMI extended chip driver module 3143, a SLIMBUS extended chip driver module 3144, and the like.

The SPMI architecture 3141 includes an SPMI interface driving module, which can be used to drive the SPMI interface in the main control chip and the SPMI extension chip to perform SPMI protocol transmission.

The SLIMBUS architecture 3142 includes a SLIMBUS interface driver module operable to drive a SLIMBUS interface in a master control chip to perform SLIMBUS protocol transmissions with a SLIMBUS extension chip.

The SPMI extended chip driving module 3143 is configured to drive the SPMI extended chip to operate, for example, to drive the SPMI extended chip to perform traffic interaction with the SPMI interface or the connected peripheral.

The SLIMBUS extension chip driver module 3144 is configured to drive the SLIMBUS extension chip to operate, for example, to drive the SLIMBUS extension chip to perform a traffic interaction with the SLIMBUS interface or the connected peripheral device.

In addition, AOP subsystem 314 has an interrupt configuration table. It can be understood that each peripheral software module performs interrupt registration in advance in the AOP, so that a one-to-one correspondence between an interrupt Identity (ID) of a peripheral and each peripheral software module can be realized, that is, an interrupt configuration table can represent a one-to-one correspondence between each peripheral generating an interrupt and a specific peripheral software module. For example, if the display hardware 325 generates an interrupt, the interrupt identifier is 11, and the peripheral software module corresponding to the interrupt identifier 11 in the interrupt configuration table is the display module 311, which indicates that the display hardware corresponding to the display module is interrupted. AOP subsystem 314 may also access corresponding peripheral software modules according to an interrupt configuration table. For example, AOP subsystem 314 accesses the corresponding display module upon determining that the display hardware is interrupted based on interrupt identification 11. It will be appreciated that the interrupt configuration table may be provided in an SPMI architecture to facilitate interaction with various peripheral software modules.

It will be appreciated that the particular structure of the core layer and the corresponding hardware layer of the handset 100 for supporting the connection scheme shown in fig. 3 is only an example.

It is appreciated that in other embodiments, the AOP subsystem may not include SPMI extended chip driver module 3143, SLIMBUS extended chip driver module 3144. At this time, the SPMI extended chip driver module 3143 and the SLIMBUS extended chip driver module 3144 may be provided in other software modules that may also operate in the sleep state. For example, the charging audio module 313 may still be operated when the electronic device is in the sleep state, and at this time, the SPMI extended chip driver module 3143 and the SLIMBUS extended chip driver module 3144 may be disposed in the charging audio module 313. Thus, the SPMI extended chip and the SLIMBUS extended chip are driven to work respectively.

In the following, taking the system architecture shown in fig. 3 as an example, a process for communicating with each peripheral device using the SPMI protocol is provided in some embodiments of the present application.

Fig. 4 is a schematic diagram of a process of implementing normal control of each peripheral device by providing an SPMI interface in a system (software system) control master control chip of a mobile phone 100 to communicate with an SPMI extension chip using an SPMI protocol according to some embodiments of the present application. The specific process is as follows:

S401, a peripheral software module in a mobile phone 100 system accesses an SPMI framework, and the SPMI framework receives a working signal sent by the peripheral software module, wherein the working signal comprises peripheral control content for controlling peripheral corresponding to the peripheral software module.

It is understood that the peripheral software modules may be software modules corresponding to various peripheral devices connected to the main control chip, such as the display module 311, the sensor module 312, the charging audio module 313, and the like shown in fig. 3.

In some embodiments, when the peripheral software module needs to control the peripheral corresponding to the peripheral, the peripheral software module may access the SPMI architecture through the SPMI software interface, where the SPMI architecture receives a working signal sent by the peripheral software module, where the working signal includes peripheral control content for controlling the peripheral corresponding to the peripheral. It will be appreciated that the SPMI software interface may communicate peripheral control information.

For example, in FIG. 3, the display module 311 is shown accessing the SPMI architecture through the SPMI software interface, such that the SPMI architecture 3141 receives a work signal for controlling the display hardware 325 to display.

S402, the SPMI architecture in the mobile phone 100 system controls the SPMI interface to send SPMI data to the SPMI extended chip according to the working signal, wherein the SPMI data comprises peripheral control content.

It is understood that the SPMI architecture can drive SPMI (hardware) interfaces to utilize SPMI protocols for transmission with SPMI extended chips.

In some embodiments, after receiving the working signal of the peripheral software module, the SPMI architecture drives the SPMI interface to send SPMI data to the SPMI extended chip, where the SPMI data includes peripheral control content.

For example, as shown in fig. 3, after the SPMI architecture 3141 receives the working signal sent by the display module 311, and controls the SPMI interface 321 to send SPMI data to the SPMI extended chip 322 according to the working signal, where the SPMI data includes content that controls the display hardware 325 to display.

S403, the SPMI extended chip driving module in the mobile phone 100 system controls the SPMI extended chip to receive the SPMI data and converts the SPMI data into corresponding type data, wherein the converted corresponding type data comprises peripheral control content.

It will be appreciated that the SPMI data needs to be converted into type data supported by each peripheral using the SPMI extended chip, for example, GPIO control data supported by each peripheral, or I2C data, SPI data, a reset signal (data), and the like.

For example, assuming that the display hardware 325 supports I2C data, the SPMI extended chip driver module 3143 controls the SPMI extended chip 322 to convert the received SPMI data into I2C data.

S404, the SPMI extended chip driving module in the mobile phone 100 system drives the SPMI extended chip to transmit the corresponding type data to the corresponding peripheral.

It will be appreciated that the I2C data includes peripheral control content.

For example, assuming that the display hardware 325 supports the I2C protocol, the SPMI extended chip driver module 3143 drives the SPMI extended chip 322 chip to send I2C data to the display hardware 325, and the display hardware 325 displays according to the peripheral control content.

It should be understood that the execution sequence of steps S401 to S404 is merely illustrative, and in other embodiments, other execution sequences may be adopted, and partial steps may be split or combined, which is not limited herein.

It will be appreciated that fig. 4 above illustrates a schematic process of controlling each peripheral by each peripheral software module in the mobile phone 100.

The following describes a specific process that after the peripheral generates an interrupt, the software module corresponding to each peripheral acquires the corresponding interrupt signal and responds according to the interrupt condition.

Fig. 5A provides a method for enabling the SPMI interface on the main control chip of the mobile phone 100 to receive an interrupt signal when each peripheral generates an interrupt, and enabling the corresponding peripheral software module to receive the interrupt signal, and the corresponding peripheral software module to respond according to the specific interrupt condition, according to some embodiments of the present application. The specific process is as follows:

S501, an AOP subsystem in the mobile phone 100 system receives an interrupt signal generated by a peripheral.

It will be appreciated that each peripheral device may experience an interruption during operation for various reasons. At this time, the peripheral will send the interrupt signal to the SPMI extended chip, the SPMI extended chip sends the interrupt request to the main control chip, and the AOP subsystem on the main control chip receives the interrupt signal. The interrupt signal comprises an interrupt Identification (ID) of the peripheral generating the interrupt, an interrupt request, an interrupt number and the like.

For example, FIG. 5B shows the corresponding data flow after an interrupt occurs with the charging audio hardware 327. When the mobile phone 100 is in the dormant state, the charging audio hardware 327 is interrupted, at this time, the charging audio hardware 327 sends an interrupt signal to the SPMI extension chip through the interrupt signal line, the SPMI extension chip sends the interrupt signal to the master control chip through the SPMI protocol, and the AOP subsystem on the master control chip receives the interrupt signal. The interrupt signal includes an interrupt Identification (ID), an interrupt request, and an interrupt number of the charging audio hardware 327 that generates the interrupt.

S502, the AOP subsystem in the mobile phone 100 system acquires the peripheral software module corresponding to the specific peripheral with the interrupt from the interrupt configuration table according to the received interrupt signal, and notifies the corresponding peripheral software module.

It can be understood that the AOP subsystem has an interrupt configuration table, and the corresponding peripheral software module can be determined according to the peripheral generating the interrupt indicated in the interrupt signal by using the interrupt configuration table, so as to notify the corresponding peripheral software module.

For example, the interrupt Identity (ID) in the interrupt signal is 1101, in the interrupt configuration table, the peripheral software module corresponding to the interrupt Identity (ID) 1101 is the charging audio module 313, and then the AOP subsystem obtains, according to the interrupt Identity (ID) 1101 in the received interrupt signal, that the peripheral software module corresponding to the specific peripheral device that has an interrupt is the charging audio module 313.

In some embodiments, if the corresponding peripheral software module is in a sleep state, the AOP subsystem wakes up the corresponding peripheral software and then sends an interrupt generation notification to the peripheral software module.

In other embodiments, the AOP subsystem may send an interrupt generation notification directly to a corresponding peripheral software module if the peripheral software module is in operation.

For example, assume that the charging audio module 313 is in a normally-on state, and the AOP subsystem notifies the charging audio module 313 that the corresponding peripheral device is interrupted. Assuming that the mobile phone 100 is in a dormant state, the charging audio module 313 is dormant, and at this time, the AOP subsystem wakes up the charging audio module 313, and then notifies the peripheral corresponding to the charging audio module 313 of an interrupt.

S503, after the peripheral software module in the mobile phone 100 system receives the notice, the SPMI driving interface in the SPMI architecture is called to control the SPMI interface and the SPMI extended chip to carry out SPMI data transmission.

It can be understood that, after the peripheral software module in the mobile phone 100 system receives the interrupt notification signal, the peripheral software module finds that the notification source is the notification source corresponding to the interrupt configuration table registered in the AOP subsystem, and at this time, the peripheral software module will respond to the interrupt.

For example, the charging audio module 313 may invoke an SPMI driver interface in the SPMI architecture 3141 to generate a read SPMI interface data instruction to control the SPMI interface to read interrupt specific type instructions from the SPMI extended chip using the SPMI protocol.

S504, the SPMI extended chip driving module in the mobile phone 100 system controls the SPMI extended chip to carry out interactive transmission with the corresponding peripheral equipment, and feeds back the specific data acquired from the peripheral equipment to the SPMI interface.

In some embodiments, the SPMI extended chip driving module controls the SPMI extended chip to convert the received SPMI data into type data supported by the corresponding peripheral, so as to communicate with the corresponding peripheral, and then feeds back specific data acquired from the peripheral to the SPMI interface.

For example, the SPMI extended chip driver module 3143 controls the SPMI extended chip 322 to convert SPMI data into I2C data including instructions to obtain a particular interrupt type. And, the SPMI extension chip 322 sends a specific interrupt type read signal to the charging audio hardware 327. Assuming that the charging audio hardware 327 generates an interrupt of an abnormal OCP (overload abnormality), the SPMI extended chip driving module 3143 controls the SPMI extended chip 322 to read a specific interrupt type, which is an OCP interrupt type, from a register of the peripheral using the I2C protocol, and to feed back specific data acquired from the peripheral to the SPMI interface.

S505, the peripheral software module in the mobile phone 100 system performs subsequent processing according to the data in the SPMI interface.

For example, the charging audio module 313 generates a control signal that controls the charging audio hardware 327 to stop operating based on data obtained from the SPMI interface.

It should be understood that the execution sequence of steps S501 to step 505 is merely illustrative, and in other embodiments, other execution sequences may be adopted, and partial steps may be split or combined, which is not limited herein.

It can be appreciated that, in some embodiments, the SLIMBUS interface in the main control chip is controlled by the mobile phone 100 software system to communicate with the SLIMBUS extension chip by using the SLIMBUS protocol, so as to realize a specific process of performing normal control on each peripheral, and the specific process of performing normal control on each peripheral is substantially the same as the specific process of performing normal control on each peripheral by communicating with the SPMI extension chip by using the SPMI protocol by using the SPMI interface in the main control chip controlled by the mobile phone 100 software system, which is not described herein. It will be appreciated that for audio class peripherals, transmissions using the SLIMBUS protocol will be more stable. For example, referring to fig. 3, the charging audio module 313 may also implement control of the charging audio hardware 327 by transmitting with the SLIMBUS extension chip through the SLIMBUS interface using the SLIMBUS protocol, and the process is substantially the same as the process of communicating with the SPMI extension chip using the SPMI protocol illustrated in fig. 4, which is not repeated herein.

In addition, after the SLIMBUS interface on the main control chip on the mobile phone 100 communicates with each peripheral by using the SLIMBUS extension chip, the interrupt processing procedure corresponding to the interrupt generated by each peripheral is substantially the same as the interrupt processing procedure related to the SLIMBUS interface, which is not described herein.

It can be appreciated that when the peripheral connected to the main control chip supports the SPMI protocol or the SLIMBUS protocol, at this time, the data type conversion is not required by using the SPMI extended chip or the SLIMBUS extended chip.

In some embodiments, for the peripheral devices supporting the SPMI protocol, a plurality of peripheral devices may be connected to 2 connection lines of the SPMI interface on the main control chip, where the main control chip may still provide a small number of connection lines (i.e. provide a small number of pads) to perform data transmission with the plurality of peripheral devices.

For example, as shown in the control circuit of fig. 6, it is assumed that the peripheral 10, the peripheral 20 and the peripheral 30 support the SPMI protocol, and each peripheral may be directly connected to the same SPMI interface on the host chip 01, so that the host chip 01 realizes transmission communication to a plurality of peripheral through one SPMI interface.

At this time, when the peripheral software module is used for control, the corresponding peripheral software module sends a driving signal to the SPMI framework, and the SPMI framework drives the SPMI interface to perform communication interaction with the corresponding peripheral. After an interrupt is generated by a certain peripheral, the AOP subsystem receives the interrupt signal, and obtains a peripheral software module corresponding to the specific peripheral generating the interrupt from the interrupt configuration table according to an interrupt Identification (ID) of the peripheral generating the interrupt in the interrupt signal, so as to access the corresponding peripheral software module. The peripheral software module accesses the SPMI interface in response to the interrupt. At this time, the SPMI architecture in the AOP subsystem drives the SPMI interface to perform communication interaction with the peripheral equipment corresponding to the interrupt generation, so that the interrupt type of the specific peripheral equipment is obtained again, and the subsequent normal control processing is facilitated.

In other embodiments, for the peripheral devices supporting the SLIMBUS protocol, multiple peripheral devices may be connected to 2 connection lines of the SLIMBUS interface on the main control chip, where the main control chip may still provide a small number of connection lines (i.e. provide a small number of pads) to perform data transmission with the multiple peripheral devices. It can be understood that the manner of connecting the plurality of peripherals with the 2 signal connection lines of the SLIMBUS on the main control chip is substantially the same as the manner of connecting the SPMI interface with the plurality of peripherals.

As shown in fig. 6, for the peripheral device 40 of the audio class and the peripheral device 50 of the audio class, which can support the SLIMBUS protocol, the signal connection lines corresponding to the same SLIMBUS interface on the main control chip 01 can be directly connected, so that the main control chip 01 can communicate with a plurality of peripheral devices through the same SLIMBUS interface.

At this time, when the peripheral software module is used for control, the corresponding peripheral software module sends a driving signal to the SLIMBUS architecture, and the SLIMBUS architecture drives the SLIMBUS interface to perform communication interaction with the corresponding peripheral. When a certain peripheral generates an interrupt, the AOP subsystem receives the interrupt, and obtains the specific peripheral generating the interrupt according to the interrupt Identification (ID) of the peripheral generating the interrupt in the interrupt configuration table, thereby accessing the corresponding peripheral software module. The peripheral software module accesses the SPMI architecture in response to the interrupt. At this time, the SLIMBUS architecture in the AOP subsystem drives the SLIMBUS interface to perform communication interaction with the peripheral corresponding to the interrupt generation, so that the interrupt type of the specific peripheral is obtained again, and the subsequent normal control processing is facilitated.

It is to be understood that the number of peripherals that communicate with one SPMI interface and SLIMBUS interface of the main control chip 01 is not particularly limited herein, and may be 1, 2, 3, or.

The following specifically describes a specific peripheral device that may be connected to the main control chip, taking the structure of the mobile phone 100 as an example. The above-mentioned main control chip 01 is taken as an example of the processor 110.

Fig. 7 is a schematic diagram of a hardware structure of the mobile phone 100 according to an embodiment of the present application.

As shown in fig. 7, the mobile phone 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (Universal Serial Bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a smart power amplifier 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, a subscriber identity module (Subscriber Identification Module, SIM) card interface 195, and the like. The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the mobile phone 100. In other embodiments of the present application, the handset 100 may include more or less components than illustrated, or certain components may be combined, certain components may be split, or different arrangements of components, without limitation.

The processor 110 may be the master control chip mentioned above, and may include one or more processing units, such as: the processor 110 may include an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing Unit, GPU), an image signal processor (Image Signal Processor, ISP), a controller, a video codec, and the like. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an I2C interface, an I2S interface, an SPI interface, an SPMI interface, a SLIMBUS interface, a pulse code modulation (Pulse Code Modulation, PCM) interface, a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface, a mobile industry processor interface (Mobile Industry Processor Interface, MIPI), a General-Purpose Input/Output (GPIO) interface, a subscriber identity module (Subscriber Identity Module, SIM) interface, and/or a universal serial bus (Universal Serial Bus, USB) interface, etc.

In some embodiments, the SPMI interface in the processor 110 and the SLIMBUS interface may communicate with various peripherals as connected in fig. 7. For some peripheral devices which do not support the SPMI protocol and the SLIMBUS protocol, the SPMI data and the SLIMBUS data can be respectively converted into type data supported by the peripheral devices through the SPMI extended chip and the SLIMBUS extended chip. For example, the sensor module 180 shown in the figure does not support the SPMI protocol, but only supports the I2C protocol, at this time, the SPMI data can be converted into the I2C data by the SPMI extended chip, so that one SPMI interface on the processor 110 can perform transmission communication with multiple peripherals, and the number of pads and occupation of area are reduced, so that the same number of pads can provide more functions.

For example, referring to fig. 2, the peripheral 11-31 may be various sensors, audio modules, keys, power management modules, etc. connected to the processor 110 in fig. 7, and are not described herein.

In some embodiments, the processor 110 may include one or more interfaces. The interface may include a universal serial bus (universal serial bus, USB) interface, or the like. The USB interface 130 may be used to connect to a charger to charge the mobile phone 100, or may be used to transfer data between the mobile phone 100 and a peripheral device.

The charge management module 140 is configured to receive a charge input from a charger. The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 to power the processor 110, the internal memory 121, the display 194, the camera 193, the wireless communication module 160, and the like.

The wireless communication function of the mobile phone 100 may be implemented by the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G, etc. applied to the handset 100. The modem processor may include a modulator and a demodulator.

The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc. applied to the mobile phone 100.

The mobile phone 100 implements display functions through a GPU, a display 194, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display 194 and the application processor.

The display screen 194 is used to display images, videos, and the like. The display 194 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Mini-LED, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the cell phone 100 may include 1 or N display screens 194, N being a positive integer greater than 1.

The mobile phone 100 may implement photographing functions through an ISP, a camera 193, a video codec, a GPU, a display 194, an application processor, and the like.

The ISP is used to process data fed back by the camera 193. For example, when photographing or taking a video, the shutter is opened, light is transmitted to the camera photosensitive element through the lens, the optical signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing, so that the electrical signal is converted into an image visible to the naked eye. ISP can also optimize the noise, brightness and skin color of the image. The ISP can also optimize parameters such as exposure, color temperature and the like of a shooting scene. In some embodiments, the ISP may be provided in the camera 193.

The camera 193 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a Complementary Metal Oxide Semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, which is then transferred to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV, or the like format. In some embodiments, the cell phone 100 may include 1 or N cameras 193, N being a positive integer greater than 1.

Video codecs are used to compress or decompress digital video.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to extend the memory capabilities of the handset 100.

The internal memory 121 may be used to store computer executable program code that includes instructions. The internal memory 121 may include a storage program area and a storage data area. The data storage area may store data created during use of the mobile phone 100 (such as video data obtained by photographing, etc.), and the like. In addition, the internal memory 121 may include a high-speed random access memory, a nonvolatile memory, and the like. The processor 110 performs various functional applications and data processing of the mobile phone 100 by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The handset 100 may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an intelligent power amplifier 170D, an application processor, and the like. Such as music playing, recording, etc.

The pressure sensor 180A is used to sense a pressure signal, and may convert the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A may be disposed on the display screen 194.

The pressure sensor 180A is of various types, such as a resistive pressure sensor, an inductive pressure sensor, a capacitive pressure sensor, and the like. The capacitive pressure sensor may be a capacitive pressure sensor comprising at least two parallel plates with conductive material. The capacitance between the electrodes changes when a force is applied to the pressure sensor 180A. The handset 100 determines the strength of the pressure from the change in capacitance. When a touch operation is applied to the display 194, the mobile phone 100 detects the intensity of the touch operation based on the pressure sensor 180A. The mobile phone 100 may also calculate the position of the touch based on the detection signal of the pressure sensor 180A.

The gyro sensor 180B may be used to determine the motion gesture of the cell phone 100.

The air pressure sensor 180C is used to measure air pressure. In some embodiments, the handset 100 calculates altitude from the barometric pressure value measured by the barometric pressure sensor 180C, aiding in positioning and navigation.

The magnetic sensor 180D includes a hall sensor. The mobile phone 100 can detect the opening and closing of the flip cover using the magnetic sensor 180D.

The acceleration sensor 180E can detect the magnitude of acceleration of the mobile phone 100 in various directions (typically three axes). The magnitude and direction of gravity can be detected when the handset 100 is stationary. The method can also be used for identifying the gesture of the electronic equipment and is applied to applications such as switching of a transverse screen and a vertical screen, pedometers and the like.

A distance sensor 180F for measuring a distance. The cell phone 100 may measure the distance by infrared or laser.

The proximity light sensor 180G may include, for example, a Light Emitting Diode (LED) and a light detector.

The ambient light sensor 180L is used to sense ambient light level.

The fingerprint sensor 180H is used to collect a fingerprint.

The temperature sensor 180J is for detecting temperature. In some embodiments, the handset 100 performs a temperature processing strategy using the temperature detected by the temperature sensor 180J. For example, when the temperature reported by temperature sensor 180J exceeds a threshold, handset 100 performs a reduction in the performance of a processor located near temperature sensor 180J in order to reduce power consumption to implement thermal protection.

The touch sensor 180K, also referred to as a "touch panel". The touch sensor 180K may be disposed on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, which is also called a "touch screen". The touch sensor 180K is for detecting a touch operation acting thereon or thereabout. The touch sensor may communicate the detected touch operation to the application processor to determine the touch event type. Visual output related to touch operations may be provided through the display 194.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the present application may be implemented as a computer program or program code that is executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a Digital Signal Processor (DSP), microcontroller, application Specific Integrated Circuit (ASIC), or microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. Program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described in the present application are not limited in scope to any particular programming language. In either case, the language may be a compiled or interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on one or more transitory or non-transitory machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy diskettes, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random Access Memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signal digital signals, etc.) in an electrical, optical, acoustical or other form of propagated signal using the internet. Thus, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

In the drawings, some structural or methodological features may be shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering may not be required. Rather, in some embodiments, these features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, may not be included or may be combined with other features.

It should be noted that, in the embodiments of the present application, each unit/module is a logic unit/module, and in physical aspect, one logic unit/module may be one physical unit/module, or may be a part of one physical unit/module, or may be implemented by a combination of multiple physical units/modules, where the physical implementation manner of the logic unit/module itself is not the most important, and the combination of functions implemented by the logic unit/module is the key to solve the technical problem posed by the present application. Furthermore, to highlight the innovative part of the present application, the above-described device embodiments of the present application do not introduce units/modules that are less closely related to solving the technical problems presented by the present application, which does not indicate that the above-described device embodiments do not have other units/modules.

It should be noted that in the examples and descriptions of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

While the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims (11)

1. A control circuit, comprising a first chip and M first devices located outside the first chip;

the first chip comprises a first chip interface, the first chip interface can transmit data to the M first devices based on a first transmission protocol, and the first chip interface can transmit multiple types of data to a first device D1 in the M first devices.

2. The circuit of claim 1, further comprising a second chip interface and a third chip interface; wherein,

the second chip interface is connected with the first chip interface of the first chip, and supports the first transmission protocol;

the third chip interface is connected with the first device D1, wherein the interface type of the third chip interface is different from that of the first chip interface.

3. The circuit of claim 2, wherein the first transmission protocol comprises at least one of a system power management interface protocol and a low power consumption inter-chip serial media bus protocol.

4. A circuit according to claim 2 or 3, wherein the second chip is for:

And converting the first data received from the second chip interface into second data supported by the third chip interface for transmission, and sending the second data to a first device D1 in the M first devices through the third chip interface.

5. The circuit of claim 4, wherein the second chip further comprises a fourth chip interface connected to a first device D2 of the M first devices, wherein the fourth chip interface is of a different interface type than both the first chip interface and the third chip interface; and is also provided with

The second chip is used for:

and converting the third data received from the second chip interface into fourth data supported by the fourth chip interface for transmission, and sending the fourth data to the first device D2 through the fourth chip interface.

6. The circuit of claim 5, wherein the third chip interface and fourth chip interface comprise at least one of:

an integrated circuit protocol interface, a serial peripheral interface, an integrated circuit built-in audio bus protocol interface, an interrupt interface, a reset interface and a general input/output control interface.

7. The circuit of claim 5, wherein the first transmission protocol is a low power inter-chip serial media bus protocol and the first device is an audio device.

8. The circuit of claim 1, wherein the control circuit further comprises N second devices located outside the first chip, and

the first chip further comprises a fifth chip interface, wherein the fifth chip interface can transmit data to the N second devices based on a fourth transmission protocol, and the fifth chip interface can transmit various types of data to a second device H1 in the N second devices; and is also provided with

The first transmission protocol is a system power management interface protocol, the fourth transmission protocol is a low-power consumption inter-chip serial media bus protocol, and the N second devices comprise audio devices.

9. The circuit of claim 1, wherein each of the M first devices has a first device interface supporting the first transport protocol;

the first chip interface is connected with first device interfaces of the M first devices.

10. A control method, characterized by being applied to a control circuit, the control circuit including a first chip and M first devices located outside the first chip, and the first chip including a first chip interface;

The method comprises the following steps:

the first chip interface is capable of transmitting data to the M first devices based on a first transmission protocol, and the first chip interface is capable of transmitting a plurality of types of data to a first device D1 of the M first devices.

11. An electronic device comprising the control circuit of any one of claims 1-9.