CN117688746A - MOS temperature model extraction method - Google Patents
MOS temperature model extraction method Download PDFInfo
- Publication number
- CN117688746A CN117688746A CN202311690825.6A CN202311690825A CN117688746A CN 117688746 A CN117688746 A CN 117688746A CN 202311690825 A CN202311690825 A CN 202311690825A CN 117688746 A CN117688746 A CN 117688746A
- Authority
- CN
- China
- Prior art keywords
- model
- temperature
- mos
- par
- formula
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000605 extraction Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000004590 computer program Methods 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 6
- 238000004088 simulation Methods 0.000 claims description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/08—Thermal analysis or thermal optimisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A MOS temperature model extraction method comprising: converting MOS temperature parameters from specific numerical values into external formulas; based on temperature current-voltage test data, extracting model fitting parameters in the plug-in formula; judging whether the model result meets a preset error condition, if so, finishing MOS temperature model extraction, otherwise, performing the following steps; calculating a temperature parameter value corresponding to each point model according to the plug-in formula and the extracted fitting parameter value, and obtaining a new point model according to the calculated temperature parameter value, wherein the new point model is used for generating a corresponding block model of each MOS device subinterval; and adjusting the temperature parameter values of the corresponding point models according to the error judgment result until the block models reach the precision requirement. According to the method, the parameter extraction efficiency of the MOS temperature model is improved by adopting a temperature parameter plug-in formula method, then the MOS temperature model is converted into a point model mode for fine adjustment, and the model continuity can be ensured while the model precision requirement is met.
Description
Technical Field
The invention relates to the technical field of SPICE modeling of a semiconductor integrated circuit, in particular to a MOS temperature model extraction method.
Background
MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) are among the common active devices of integrated circuits. The MOS device modeling method generally includes two modes, global and blocking. The global approach models the size range in question uniformly, while the bipinning approach models the size range in question separately into several sub-intervals, each bipinning model (block model) being synthesized from four point models (point models) for the corresponding size range, each point model corresponding to a specific W/L (MOS channel width/length), as shown in fig. 1. The binning model is more accurate but more labor intensive. In order to meet the precision requirements of the model under different temperature conditions, MOS temperature model extraction is required to be performed based on temperature test data.
For extraction of a binning mode temperature model, two methods are currently common: one is to use a plug-in formula for temperature parameters and adjust parameters in the plug-in formula; the other is to perform point mode parameter adjustment on the temperature parameters, namely directly adjusting the temperature parameters of each point model. The first method has a disadvantage in that the model accuracy may be insufficient, and each of the dimensional error requirements may not be satisfied. The second method has the disadvantage of adjusting the temperature parameters of each point model individually, is labor intensive, and is prone to discontinuity problems. No matter which method is used, the model extraction efficiency, the model precision and the continuity cannot be ensured at the same time, so how to quickly establish the MOS temperature model and ensure the model precision and the model continuity at the same time is a problem which needs to be faced and solved by the person skilled in the art.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide the MOS temperature model extraction method, which aims at the binning mode to rapidly complete the temperature modeling work and ensure the temperature model precision so as to improve the modeling efficiency of an MOS device.
In order to achieve the above object, the MOS temperature model extraction method provided by the present invention includes:
converting MOS temperature parameters from specific numerical values into external formulas;
based on temperature current-voltage test data, extracting model fitting parameters in the plug-in formula;
judging whether the model result meets a preset error condition, if so, finishing MOS temperature model extraction, otherwise, performing the following steps;
calculating a temperature parameter value corresponding to each point model according to the plug-in formula and the extracted fitting parameter value, and obtaining a new point model according to the calculated temperature parameter value, wherein the new point model is used for generating a corresponding block model of each MOS device subinterval;
and adjusting the temperature parameter values of the corresponding point models according to the error judgment result until the block models reach the precision requirement.
Further, the MOS temperature parameters include a threshold voltage temperature coefficient, a mobility temperature coefficient, a saturation rate temperature coefficient, a threshold voltage lining bias effect temperature coefficient, and a mobility lining bias effect temperature coefficient.
Further, the external formula of the MOS temperature parameter is as follows:
parm＝'parm_wl'，
and (b) par_wl= '(r_par+l_par/pwr (L, ll_par) +w_par/pwr (W, ww_par) +p_par/(p wr (L, llp _par) ×pwr (W, wwp _par)))', wherein par represents a MOS temperature parameter, L represents a MOS channel length, W represents a MOS channel width, and r_par, l_par, ll_par, w_par, ww_par, p_par, llp_par, ww_par are model fitting parameters.
Further, the temperature current-voltage test data includes a drain current-gate voltage curve, a drain current-drain voltage curve, and the temperature includes-40 ℃, -15 ℃, 85 ℃, and 125 ℃.
Further, the step of determining whether the model result meets the preset error condition further includes: and carrying out model simulation based on the block model, and judging whether the model result meets the conditions that the threshold voltage error is less than 15mV and the current error is less than 5%.
In order to achieve the above object, the present invention further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor is configured to execute the computer program stored in the memory, so as to implement the MOS temperature model extraction method as described above.
To achieve the above object, the present invention also provides a computer-readable storage medium having at least one instruction stored therein, the instruction being loaded and executed by a processor to implement the MOS temperature model extraction method as described above.
Compared with the prior art, the MOS temperature model extraction method provided by the invention has the following beneficial effects:
the temperature parameter plug-in formula method is adopted, the parameter extraction efficiency of the model is improved, the model mode of the joint is finely adjusted, the model continuity can be ensured while the model precision requirement is met, the MOS temperature model extraction efficiency is improved, and the temperature modeling work is rapidly completed.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:
FIG. 1 is a block-wise modeling schematic according to the present invention;
FIG. 2 is a flow chart of a method for extracting a MOS temperature model according to an embodiment of the invention;
fig. 3 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While the invention is susceptible of embodiment in the drawings, it is to be understood that the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the invention. It should be understood that the drawings and embodiments of the invention are for illustration purposes only and are not intended to limit the scope of the present invention.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 2 is a flowchart of a MOS temperature model extraction method according to an embodiment of the present invention, and a method embodiment of the present invention is described in detail below with reference to fig. 2.
In step 101, the MOS temperature parameter is converted from a specific value to an external formula.
In the embodiment of the invention, the MOS temperature parameter includes kt1 (threshold voltage temperature coefficient), ute (mobility temperature coefficient), at (saturation rate temperature coefficient), kt2 (threshold voltage lining bias effect temperature coefficient), uc1 (mobility lining bias effect temperature coefficient).
Taking parameter kt1 as an example, the external formula form is as follows:
(1)kt1＝'kt1_wl'，
(2)kt1_wl＝'(r_kt1+l_kt1/pwr(L,ll_kt1)+w_kt1/pwr(W,ww_kt1)+p_kt1/(pwr(L,llp_kt1)*pwr(W,wwp_kt1)))'。
wherein L represents MOS channel length, W represents MOS channel width, and r_kt1/l_kt1/ll_kt1/w_kt1/ww_kt1/p_kt1/llp _kt1/wwp _kt1 is model fitting parameter.
The model extraction needs to consider different size conditions, and r_kt1 mainly aims at Wmax/Lmax, l_kt1/ll_kt1, wmax/Lmin and Wmax/Lmiddle, w_kt1/ww_kt1 mainly aims at Wmin/Lmax and Wmiddle/Lmax, and p_kt1/llp _kt1/wwp _kt1 mainly aims at Wmin/Lmin, wmin/Lmiddle and Wmiddle/Lmin. This combination of parameters is common practice in the industry, wmax, wmiddle and Wmin represent the maximum, median and minimum values, respectively, of the MOS channel width, lmax, lmiddle and Lmin represent the maximum, median and minimum values, respectively, of the MOS channel length.
The external hanging formulas of the rest temperature parameters are the same as the formulas (1) and (2).
ute the plug-in formula is as follows:
(3)ute＝'ute_wl'，
(4)ute_wl＝'(r_ute+l_ute/pwr(L,ll_ute)+w_ute/pwr(W,ww_ute)+p_ute/(pwr(L,llp_ut e)*pwr(W,wwp_ute)))'。
at's plug-in formula is:
(5)at＝'at_wl'，
(6)at_wl＝'(r_at+l_at/pwr(L,ll_at)+w_at/pwr(W,ww_at)+p_at/(pwr(L,llp_at)*pwr(W,wwp_at)))'。
the plug-in formula of kt2 is:
(7) kt2 ＝ ' kt2_wl'，
(8)kt2_wl＝'(r_kt2+l_kt2/pwr(L,ll_kt2)+w_kt2/pwr(W,ww_kt2)+p_kt2/(pwr(L,llp_kt2)*pwr(W,wwp_kt2)))'。
the plug-in formula for uc1 is:
(9) uc1 ＝ ' uc1_wl'，
(10)uc1_wl＝'(r_uc1+l_uc1/pwr(L,ll_uc1)+w_uc1/pwr(W,ww_uc1)+p_uc1/(pwr(L,l lp_uc1)*pwr(W,wwp_uc1)))'。
at step 102, model fitting parameters are extracted based on high and low temperature IV (current-voltage) test data.
In the embodiment of the invention, the model fitting parameter extraction is performed based on high-low temperature IV (current-voltage) test data. The test data includes Id-Vg (drain current-gate voltage), id-Vd (drain current-drain voltage), etc., and the high and low temperatures generally include-40 ℃, -15 ℃, 85 ℃, 125 ℃.
The block model obtained in the step 102 is also obtained, whether the model result meets the requirement is judged through model simulation, if yes, the modeling can be ended, and otherwise, the block model is converted into a point model for further adjustment.
In step 103, it is determined whether the model result satisfies a preset condition.
In the embodiment of the invention, if the model result satisfies Vt error less than 15mV and Id error less than 5%, modeling work is completed. Otherwise, executing the following steps, namely, if the model result does not meet the precision requirement, and adjusting through the following steps. Where Vt error represents the threshold voltage error and Id error represents the current error.
In step 104, according to the plug-in formula and the extracted fitting parameter values, a temperature parameter value corresponding to each point model is calculated. Specifically, the linking model (block model) in step 102 is converted into a point model, and the calculated temperature parameter values are substituted into each point model, and based on the new point model, a corresponding linking model is generated.
In step 105, for the portions that do not meet the error requirement, the corresponding point model temperature parameters are adjusted to achieve the required accuracy requirement, thereby obtaining the final temperature model.
The steps 101, 102, 103 are based on a block model, and the step 104 involves a point model. The difference is that the previous temperature parameter is in the form of an externally-hung formula, the latter is in the form of a point model, and one dimension corresponds to one set of temperature parameter values. All dimensional accuracy requirements may not be met due to the plug-in formulation. Firstly, adopting an externally hung formula form to ensure most of point precision, converting the point precision into a point model form, and adjusting few point precision. The key of the invention is the conversion of two modes.
According to the MOS temperature model extraction method, MOS temperature parameters are changed into an externally hung formula, parameter extraction is performed based on temperature measured data, and a block model is established. And if the model result meets the precision requirement, finishing the temperature modeling work. If the model result does not meet the precision requirement, calculating the temperature parameter value of each point model according to the plug-in formula, and substituting each point model respectively to generate a corresponding binding model. And for the part which does not meet the error requirement, adjusting the temperature parameter of the corresponding point model to meet the precision requirement, thereby obtaining a final temperature model. The parameter extraction efficiency of the model is improved by adopting a temperature parameter plug-in formula method, and then the model is converted into a point mode for fine adjustment, so that the model continuity can be ensured while the model precision requirement is met.
In an embodiment of the present invention, there is further provided an electronic device, fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 3, the electronic device of the present invention includes a processor 301, and a memory 302, where,
the memory 302 stores a computer program which, when read by the processor 301 for execution, performs the steps in the MOS temperature model extraction method embodiment described above.
In an embodiment of the present invention, there is also provided a computer-readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps in the MOS temperature model extraction method embodiment described above when run.
In the present embodiment, the above-described computer-readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the concepts of "first," "second," etc. may be used in the present invention merely to distinguish between different devices, components or sections and are not intended to limit the order or interdependence of functions performed by these devices, components or sections. The modifications of "one" or "a plurality" as may be mentioned in the present invention are illustrative and not restrictive, and it should be understood by those skilled in the art that "one or more" should be interpreted as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The MOS temperature model extraction method is characterized by comprising the following steps of:
converting MOS temperature parameters from specific numerical values into external formulas;
based on temperature current-voltage test data, extracting model fitting parameters in the plug-in formula;
judging whether the model result meets a preset error condition, if so, finishing MOS temperature model extraction, otherwise, performing the following steps;
calculating a temperature parameter value corresponding to each point model according to the plug-in formula and the extracted fitting parameter value, and obtaining a new point model according to the calculated temperature parameter value, wherein the new point model is used for generating a corresponding block model of each MOS device subinterval;
and adjusting the temperature parameter values of the corresponding point models according to the error judgment result until the block models reach the precision requirement.
2. The MOS temperature model extraction method of claim 1, wherein the MOS temperature parameters comprise a threshold voltage temperature coefficient, a mobility temperature coefficient, a saturation rate temperature coefficient, a threshold voltage lining bias effect temperature coefficient, and a mobility lining bias effect temperature coefficient.
3. The method for extracting a MOS temperature model according to claim 1, wherein the form of the plug-in formula of the MOS temperature parameter is as follows:
parm＝'parm_wl'，
and (b) par_wl= '(r_par+l_par/pwr (L, ll_par) +w_par/pwr (W, ww_par) +p_par/(pwr (L, llp _par) ×pwr (W, wwp _par)))', wherein par represents a MOS temperature parameter, L represents a MOS channel length, W represents a MOS channel width, and r_par, l_par, ll_par, w_par, ww_par, p_par, llp_par, ww_par are model fitting parameters.
4. The MOS temperature model extraction method of claim 1, wherein the temperature current-voltage test data comprises a drain current-gate voltage curve, a drain current-drain voltage curve, the temperature comprising-40 ℃, -15 ℃, 85 ℃, and 125 ℃.
5. The method for extracting a MOS temperature model according to claim 1, wherein the step of judging whether the model result satisfies a preset error condition further comprises: and carrying out model simulation based on the block model, and judging whether the model result meets the conditions that the threshold voltage error is less than 15mV and the current error is less than 5%.
6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor is configured to execute the computer program stored in the memory to implement the MOS temperature model extraction method according to any one of claims 1 to 5.
7. A computer readable storage medium having stored therein at least one instruction that is loaded and executed by a processor to implement the MOS temperature model extraction method of any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311690825.6A CN117688746A (en) | 2023-12-07 | 2023-12-07 | MOS temperature model extraction method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311690825.6A CN117688746A (en) | 2023-12-07 | 2023-12-07 | MOS temperature model extraction method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117688746A true CN117688746A (en) | 2024-03-12 |
Family
ID=90136534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311690825.6A Pending CN117688746A (en) | 2023-12-07 | 2023-12-07 | MOS temperature model extraction method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117688746A (en) |
-
2023
- 2023-12-07 CN CN202311690825.6A patent/CN117688746A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Karpuzcu et al. | VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages | |
| CN102142057B (en) | BSIM4 stress model applied to MOSFET electrical simulation | |
| US8336010B1 (en) | Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits | |
| US8954908B1 (en) | Fast monte carlo statistical analysis using threshold voltage modeling | |
| US8136079B2 (en) | Effective gate length circuit modeling based on concurrent length and mobility analysis | |
| JP2004200461A5 (en) | ||
| US8032349B2 (en) | Efficient methodology for the accurate generation of customized compact model parameters from electrical test data | |
| US8370774B2 (en) | Constructing mapping between model parameters and electrical parameters | |
| CN102081686A (en) | Modeling method of MOS (Metal Oxide Semiconductor) transistor process corner SPICE (Simulation Program for Integrated Circuits Emphasis) model | |
| US20120123745A1 (en) | Adaptive Content-aware Aging Simulations | |
| CN117688746A (en) | MOS temperature model extraction method | |
| TW201439804A (en) | Aging-based leakage energy reduction method and system | |
| TW202328965A (en) | Margin calibration method and margin calibration system for static timing analysis | |
| US8271254B2 (en) | Simulation model of BT instability of transistor | |
| KR100316314B1 (en) | Amorphous Region Determination Method and Apparatus | |
| CN108763830B (en) | Flicker noise model of semiconductor device and extraction method thereof | |
| US20070233447A1 (en) | Circuit simulation method and circuit simulation apparatus | |
| CN116629009A (en) | ASM-GaN drain current modeling method considering temperature effect | |
| US8380479B2 (en) | Model parameter extracting apparatus and model parameter extracting program for semiconductor device model | |
| TWI756678B (en) | Method for aging simulation model establishment | |
| CN107480366A (en) | A kind of method and system that leakage current temperature characterisitic is improved for model | |
| Lu et al. | Teshop: A temperature sensing based hotspot-driven placement technique for fpgas | |
| Cheng et al. | Compact modeling of fin-width roughness induced FinFET device variability using the perturbation method | |
| Lu et al. | Going cooler with timing-constrained TeSHoP: a temperature sensing-based hotspot-driven placement technique for FPGAs | |
| US8539426B2 (en) | Method and system for extracting compact models for circuit simulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |