CN117674756A - Equalization circuit and equalization system - Google Patents
Equalization circuit and equalization system Download PDFInfo
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- CN117674756A CN117674756A CN202311767053.1A CN202311767053A CN117674756A CN 117674756 A CN117674756 A CN 117674756A CN 202311767053 A CN202311767053 A CN 202311767053A CN 117674756 A CN117674756 A CN 117674756A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/42—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/24—Frequency- independent attenuators
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Abstract
The application is applicable to the technical field of electronics, and provides an equalizing circuit and equalizing system, and this equalizing circuit includes: an input port for receiving a signal to be equalized; the signal attenuation module is connected with the input port and used for attenuating the signal to be equalized; the signal filtering module is connected with the input port and the signal attenuation module and is used for respectively carrying out filtering treatment on the signal to be equalized and the attenuated signal to be equalized; and the output port is connected with the signal attenuation module and the signal filtering module and is used for outputting signals obtained after being processed by the signal attenuation module and the signal filtering module. Compared with the waveguide equalization circuit and the resonant cavity equalization circuit in the prior art, the equalization circuit provided by the application is simple in structure, the amplitude distortion of signals to be equalized can be reduced only by the signal attenuation module and the signal filtering module, the waveguide equalization circuit can be widely applied to various application scenes, and the practicability of the equalization circuit is improved.
Description
Technical Field
The application belongs to the technical field of electronics, and particularly relates to an equalization circuit and an equalization system.
Background
At present, in the transmission and processing process of broadband signals, the gain fluctuation of devices (such as broadband amplifiers) in the system working at radio frequency and microwave ends causes the amplitude-frequency characteristic distortion of the signals, and influences the signal transmission quality. In practical application, the equalization circuit can improve the stability of gain of signals in a working frequency band in the transmission process, reduce or even avoid distortion of signal amplitude, and enable the amplitude-frequency characteristic of the signals to meet the signal transmission requirement.
Existing equalization circuits are typically waveguide equalization circuits and cavity equalization circuits. However, the waveguide equalization circuit and the resonant cavity have complex equalization electrical structures, so that the application scene is less, and the practicability of the equalization circuit is reduced.
Disclosure of Invention
In view of this, the embodiment of the application provides an equalization circuit and an equalization system, so as to solve the technical problems that the prior art has a complex structure, resulting in fewer application scenes and reducing the practicability of the equalization circuit.
An embodiment of the present application provides an equalization circuit, including:
an input port for receiving a signal to be equalized;
the signal attenuation module is connected with the input port and used for attenuating the signal to be equalized;
the signal filtering module is connected with the input port and the signal attenuation module and is used for respectively carrying out filtering treatment on the signal to be equalized and the attenuated signal to be equalized;
and the output port is connected with the signal attenuation module and the signal filtering module and is used for outputting signals obtained after being processed by the signal attenuation module and the signal filtering module.
Optionally, the signal filtering module includes;
the first filtering unit is connected with the input port and is used for filtering the signal to be equalized so as to filter out the signal in the first frequency range;
the second filtering unit is connected with the signal attenuation module and is used for filtering the attenuated signal to be equalized so as to filter out signals in a second frequency range; the lower limit of the first frequency range is greater than the upper limit of the second frequency range.
Optionally, the input end of the signal attenuation module is connected with the input port, the first output end of the signal attenuation module is connected with the output port, and the second output end of the signal attenuation module is connected with the first input end of the signal filtering module; the signal attenuation module comprises a first resistor, a second resistor and a third resistor;
the first end of the first resistor is an input end of the signal attenuation module, the second end of the first resistor and the first end of the second resistor are connected to the first end of the third resistor, the second end of the third resistor is a first output end of the signal attenuation module, and the second end of the second resistor is a second output end of the signal attenuation module.
Optionally, the attenuation of the signal to be equalized by the equalizing circuit is determined according to the resistance of the first resistor, the resistance of the second resistor and the resistance of the third resistor.
Optionally, an input end of the first filtering unit is connected with the input port, an output end of the first filtering unit is connected with the output port, and the first filtering unit comprises a first capacitor and a first inductor;
the first end of the first capacitor is the input end of the first filtering unit, the second end of the first capacitor is connected with the first end of the first inductor, and the second end of the first inductor is the output end of the first filtering unit.
Optionally, the first frequency range is determined according to a first capacitance value of the first capacitor and a first inductance value of the first inductor.
Optionally, the input end of the second filtering unit is connected with the first output end of the signal attenuation module, and the first filtering unit comprises a second capacitor and a second inductor;
the first end of the second capacitor and the first end of the second inductor are commonly connected and serve as the input end of the second filtering unit, the second end of the second capacitor is grounded, and the second end of the second inductor is grounded.
Optionally, the equalization circuit further includes: the first grounding port, the second grounding port, the third grounding port and the fourth grounding port;
the first grounding port and the second grounding port are positioned on two sides of the input port, and the first distance and the second distance are equal; the first distance refers to a distance between the first ground port and the input port; the second distance refers to a distance between the second ground port and the input port;
the third grounding port and the fourth grounding port are positioned on two sides of the output port, and the third distance and the fourth distance are equal; the third distance refers to a distance between the third ground port and the output port; the fourth distance refers to a distance between the fourth ground port and the output port.
Optionally, the equalization circuit is a circuit built on the substrate layer based on thin film passive device technology.
Optionally, the base layer is a single-layer dielectric plate, and the base layer uses gallium arsenide material as a substrate.
In a second aspect, embodiments of the present application provide an equalization system, including a signal generating circuit for generating a signal to be equalized and an equalization circuit as described in the first aspect or any of the alternatives of the first aspect; the signal generating circuit is electrically connected with the equalizing circuit.
The equalization circuit and the equalization system provided by the embodiment of the application have the following beneficial effects:
the equalization circuit provided by the embodiment of the application comprises an input port, an output port, a signal attenuation module and a signal filtering module; the signal attenuation module is used for attenuating the signal to be equalized; the signal filtering module is used for respectively carrying out filtering treatment on the signal to be equalized and the attenuated signal to be equalized; the output port is used for outputting signals obtained after processing by the signal attenuation module and the signal filtering module. Compared with the waveguide equalization circuit and the resonant cavity equalization circuit in the prior art, the equalization circuit provided by the application is simple in structure, the amplitude distortion of signals to be equalized can be reduced only by the signal attenuation module and the signal filtering module, the waveguide equalization circuit can be widely applied to various application scenes, and the practicability of the equalization circuit is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an equalization circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an equalization circuit according to another embodiment of the present application;
fig. 3 is a schematic structural diagram of an equalization circuit according to another embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of an equalizing circuit according to an embodiment of the present disclosure;
fig. 5 is a practical circuit configuration diagram of an equalizing circuit according to an embodiment of the present application;
FIG. 6 is a simulation plot of S-parameters of an equalization circuit according to an embodiment of the present application;
FIG. 7 is a return loss simulation plot of an equalization circuit provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of an equalization system according to an embodiment of the present application;
Detailed Description
In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first voltage value and the second voltage value are merely for distinguishing between different voltage values, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In this application, the terms "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an equalization circuit according to an embodiment of the present application. The equalization circuit is used for carrying out amplitude equalization processing on signals to be equalized.
As shown in fig. 1, the equalization circuit 10 is connected to a signal generation circuit 20. The signal generating circuit 20 is used for generating a signal to be equalized.
The equalization circuit 10 may include: an input port 11, a signal attenuation module 12, a signal filtering module 13 and an output port 14.
The input port 11, the signal attenuation module 12, the signal filtering module 13, and the output port 14 are all wired via transmission lines. The transmission line may be determined according to actual needs, and is not limited herein.
In practical applications, the transmission line includes, but is not limited to, parallel double-wire, parallel multi-wire, coaxial line, strip line, microstrip line, etc.
An input port 11 for receiving a signal to be equalized.
And the signal attenuation module 12 is connected with the input port 11 and is used for attenuating the signal to be equalized.
And the signal filtering module 13 is connected with the input port 11 and the signal attenuation module 12 and is used for respectively carrying out filtering processing on the signal to be equalized and the attenuated signal to be equalized.
And an output port 14, connected to the signal attenuation module 12 and the signal filtering module 13, for outputting the signal processed by the signal attenuation module 12 and the signal filtering module 13.
In some possible embodiments, the equalization circuit 10 may be connected to the signal generating circuit 20 through an input port 11, the input port 11 being configured to receive the signal to be equalized generated by the signal generating circuit 20.
In the present embodiment, the signal generating circuit 20 includes an amplifier or the like.
Illustratively, the equalization circuit 10 is applied to a radio frequency band, microwave band system, and the amplifier is a wideband amplifier. Based on this, the signal to be equalized generated by the signal generating circuit 20 is a wideband signal amplified by a wideband amplifier.
Since the signal to be equalized is a signal amplified by the amplifier in the signal generating circuit 20, and the signal to be equalized has a problem of distortion of amplitude-frequency characteristics due to gain fluctuation of each device itself in the signal generating circuit 20. Therefore, the signal to be equalized needs to be transmitted to the equalization circuit 10 for amplitude equalization processing, so as to improve the stability of the gain of the signal to be equalized in the subsequent transmission process.
In this embodiment, after receiving the signal to be equalized, the signal attenuation module 12 may perform signal attenuation processing on the signal to be equalized, so as to reduce the amplitude of the signal to be equalized.
In practical applications, the signal attenuation module 12 may be a T-type attenuation circuit, a pi-type attenuation circuit, or other attenuation circuits for attenuating signals.
In this embodiment of the present application, in order to further improve the stability of the gain of the signal to be equalized in the subsequent transmission process, the signal filtering module 13 in the equalizing circuit 10 may perform filtering processing on the signal to be equalized transmitted through the input port 11 and the signal to be equalized attenuated through the signal attenuation module 12, respectively.
In practical applications, the signal filtering module 13 may be a series resonant circuit, a parallel resonant circuit, or other filtering circuits for filtering signals.
In this embodiment of the present application, after the signal attenuation module 12 performs attenuation processing on the signal to be equalized, and the signal filtering module 13 performs filtering processing on the signal to be equalized and the signal to be equalized after being attenuated by the signal attenuation module 12, the output port 14 may output a signal obtained after being processed by the signal attenuation module 12 and the signal filtering module 13, that is, output a target signal whose amplitude-frequency characteristic meets the signal transmission requirement.
In one embodiment of the present application, both the input port 11 and the output port 14 are rectangular in shape in order to meet process production requirements and facilitate subsequent connection with other devices.
It should be noted that the shapes of the input port 11 and the output port 14 may be other shapes, such as a circle, a polygon, and the like.
In some possible embodiments, in order to improve the integration of the equalization circuit 10 and reduce the overall area of the equalization circuit 10 while facilitating the subsequent connection with other devices, the length and width of the input port 11 and the output port 14, which are arranged in rectangular shapes, are each 100 micrometers.
In another embodiment of the present application, in order to further increase the integration level of the equalization circuit 10 and reduce the size of the equalization circuit 10, the equalization circuit 10 may be a circuit built on a substrate layer based on a thin film passive device technology.
In practical applications, integrated passive device (Integrated Passive Devices, IPD) technology is a technology that integrates multiple electronic functions, with the advantage of miniaturization and improved system performance.
In one embodiment of the present application, the substrate layer for carrying the equalization circuit 10 may be a single layer dielectric plate in order to reduce cost and further reduce the overall bulk of the equalization circuit 10.
In yet another embodiment of the present application, the base layer for carrying the equalization circuit 10 may be a dielectric plate with gallium arsenide material as the substrate in order to improve the reliability and stability of the equalization circuit 10.
The equalization circuit provided by the embodiment of the application comprises an input port, an output port, a signal attenuation module and a signal filtering module; the signal attenuation module is used for attenuating the signal to be equalized; the signal filtering module is used for respectively carrying out filtering treatment on the signal to be equalized and the attenuated signal to be equalized; the output port is used for outputting signals obtained after processing by the signal attenuation module and the signal filtering module. Compared with the waveguide equalization circuit and the resonant cavity equalization circuit in the prior art, the equalization circuit provided by the application is simple in structure, the amplitude distortion of signals to be equalized can be reduced only by the signal attenuation module and the signal filtering module, the waveguide equalization circuit can be widely applied to various application scenes, and the practicability of the equalization circuit is improved.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an equalizing circuit according to another embodiment of the present application. As shown in fig. 2, in relation to the embodiment corresponding to fig. 1, in order to facilitate the electrical connection of the equalization circuit 10 with other devices, the equalization circuit 10 may further include a first ground port 15, a second ground port 16, a third ground port 17, and a fourth ground port 18.
Specifically, the first ground port 15 and the second ground port 16 are located on both sides of the input port 11.
The third ground port 17 and the fourth ground port 18 are located on both sides of the output port 14.
In this embodiment, in order to facilitate on-chip testing of the equalization circuit 10, a first distance between the first ground port 15 and the input port 11 is equal to a second distance between the second ground port 16 and the input port 11; the third distance between the third ground port 17 and the output port 14 is equal to the fourth distance between the fourth ground port 18 and the output port 14.
The first distance, the second distance, the third distance, and the fourth distance may be set according to actual needs, which is not limited herein. Illustratively, the first, second, third, and fourth distances may each be 150 microns.
In one embodiment of the present application, in order to improve the integration of the equalization circuit 10 and reduce the overall area of the equalization circuit 10 while facilitating the subsequent connection with other devices, the first ground port 15, the second ground port 16, the third ground port 17, and the fourth ground port 18 may all be provided in a rectangular shape.
It should be noted that the shapes of the first ground port 15, the second ground port 16, the third ground port 17, and the fourth ground port 18 may be other shapes, such as a circle, a polygon, and the like.
In another embodiment of the present application, in order to further meet the process requirements of the equalization circuit 10 and facilitate the subsequent connection of the equalization circuit 10 to other devices, the length and width of the first ground port 15, the second ground port 16, the third ground port 17, and the fourth ground port 18, which are rectangular, are 84 micrometers.
It can be seen from the above that, the equalization circuit provided in this embodiment further includes a first ground port, a second ground port, a third ground port and a fourth ground port, which is not only convenient for on-chip testing of the equalization circuit, but also convenient for the equalization circuit to be electrically connected with other devices.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an equalizing circuit according to another embodiment of the present application. As shown in fig. 3, the signal filtering module 13 in this embodiment includes a first filtering unit 31 and a second filtering unit 32, relative to the corresponding embodiment of fig. 1.
Specifically, the first filtering unit 31 is connected to the input port 11, and is configured to perform filtering processing on the signal to be equalized, so as to filter out the signal in the first frequency range.
The second filtering unit 32 is connected to the signal attenuation module 12, and is configured to perform filtering processing on the attenuated signal to be equalized, so as to filter out a signal in a second frequency range; the lower limit of the first frequency range is greater than the upper limit of the second frequency range.
In this embodiment, the first filtering unit 31 is configured to filter out high-frequency signals in the signal to be equalized, i.e. to filter out signals in the first frequency range. Wherein the high frequency signal refers to a signal in a first frequency range. The lower limit of the first frequency range may be 6GHZ.
The second filtering unit 32 is configured to filter out low-frequency signals in the attenuated signal to be equalized, i.e. to filter out signals in the second frequency range. Wherein the low frequency signal refers to a signal in a second frequency range. The upper limit of the second frequency range may be 300kHZ.
In practical applications, the first filtering unit 31 may be a series resonant circuit, and the second filtering unit 32 may be a parallel resonant circuit.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of an equalizing circuit according to an embodiment of the present application. For convenience of explanation, only the portions related to the present embodiment are shown. As shown in fig. 4, in this embodiment, an input end of the signal attenuation module 12 is connected to the input port 11, a first output end of the signal attenuation module 12 is connected to the output port 14, and a second output end of the signal attenuation module 12 is connected to a first input end of the signal filtering module 13.
The signal attenuation module 12 specifically includes a first resistor R1, a second resistor R2, and a third resistor R3.
Specifically, the first end of the first resistor R1 is an input end of the signal attenuation module 12, the second end of the first resistor R1 and the first end of the second resistor R2 are connected to the first end of the third resistor R3, the second end of the third resistor R3 is a first output end of the signal attenuation module 12, and the second end of the second resistor R2 is a second output end of the signal attenuation module 12.
It should be noted that, the attenuation of the signal to be equalized by the equalization circuit 10 may be determined according to the resistance of the first resistor R1, the resistance of the second resistor R2, and the resistance of the third resistor R3.
In practical applications, the first resistor R1, the second resistor R2, and the third resistor R3 may be thin film resistors.
With continued reference to fig. 4, in one embodiment of the present application, an input end of the first filtering unit 31 is connected to the input port 11, and an output end of the first filtering unit 31 is connected to the output port 14.
The first filtering unit 31 specifically includes a first capacitor C1 and a first inductor L1.
The first end of the first capacitor C1 is an input end of the first filtering unit 31, the second end of the first capacitor C1 is connected with the first end of the first inductor L1, and the second end of the first inductor L1 is an output end of the first filtering unit 31.
It should be noted that the first frequency range may be determined according to the first capacitance value of the first capacitor C1 and the first inductance value of the first inductor L1.
In practical applications, the first capacitor C1 may be a plate (Metal Insulator Metal) capacitor.
The first inductance L1 may be a spiral inductance.
With continued reference to fig. 4, in another embodiment of the present application, an input terminal of the second filtering unit 32 is connected to the first output terminal of the signal attenuation module 12.
The first filtering unit 32 includes a second capacitor C2 and a second inductor L2;
the first end of the second capacitor C2 and the first end of the second inductor L2 are commonly connected and serve as an input end of the second filtering unit 32, the second end of the second capacitor C2 is grounded, and the second end of the second inductor L2 is grounded.
It should be noted that the second frequency range may be determined according to the second capacitance value of the second capacitor C2 and the second inductance value of the second inductor L2.
In practical applications, the second capacitor C2 may be a plate (Metal Insulator Metal) capacitor.
The second inductance L2 may be a spiral inductance.
In one embodiment of the present application, the equalization circuit 10 may further include a fifth ground port (not shown) and a sixth ground port (not shown).
Thus, the second ground of the second capacitor C2 may be: the second end of the second capacitor C2 is connected to the fifth ground port.
The second ground of the second inductor L2 may be: the second end of the second inductor L2 is connected to the sixth ground port.
In one embodiment of the present application, in order to design an aesthetic appearance and improve the integration level of the equalization circuit 10 and reduce the overall area of the equalization circuit 10, the equalization circuit 10 may be symmetrically disposed, i.e., each device in the equalization circuit 10 may be symmetrically disposed.
Referring to fig. 5, fig. 5 is a schematic diagram of an equalization circuit according to an embodiment of the present application. As shown in fig. 5, the equalizing circuit 10 includes: the input port RF1, the output port RF2, the first ground port B1, the second ground port B2, the third ground port B3, the fourth ground port B4, the fifth ground port B5, the sixth ground port B6, the signal attenuation module 12 constituted by the first resistor R1, the second resistor R2 and the third resistor R3, the first filter unit 31 constituted by the first capacitor C1 and the first inductor L1, and the second filter unit 32 constituted by the second capacitor C2 and the second inductor L2. The fifth ground port B5 is connected to the second port of the second capacitor C2, and the sixth ground port B6 is connected to the second port of the second inductor L2.
In the present embodiment, the first filter unit 31 formed by the first capacitor C1 and the first inductor L1 and the second filter unit 32 formed by the second capacitor C2 and the second inductor L2 may be symmetrically arranged according to the first symmetry line determined by the signal attenuation module 12 formed by the first resistor R1, the second resistor R2 and the third resistor R3; the first resistor R1 and the third resistor R3 in the signal attenuation module 12 are symmetrically arranged with a second symmetry line determined according to the second resistor R2; the input port RF1 and the output port RF2 are symmetrically arranged with a third symmetry line determined according to the signal attenuation module 12; the first ground port B1 and the second ground port B2 are symmetrically arranged with a fourth symmetry line determined according to the input port RF 1; the third ground port B3 and the fourth ground port B4 are symmetrically arranged with respect to a fifth symmetry line determined from the output port RF 2.
The first symmetry line is specifically a straight line parallel to the straight line corresponding to the first direction and passing through the center of the signal attenuation module 12. The first direction specifically means that the first resistor R1 points in the direction of the third resistor R3.
The second symmetry line is specifically a straight line parallel to the straight line corresponding to the second direction and passing through the center of the second resistor R2. The straight line corresponding to the second direction is perpendicular to the straight line corresponding to the first direction.
The third symmetry line is specifically a straight line parallel to the straight line corresponding to the second direction, and passes through the signal attenuation module 12 to obtain a center straight line.
The fourth symmetry line is specifically a straight line parallel to the straight line corresponding to the first direction and passing through the center of the input port RF 1.
The fifth symmetry line is specifically a straight line parallel to the straight line corresponding to the first direction and passing through the center of the output port RF 2.
The specific operation principle of the equalizing circuit provided in the embodiment of the present application is described in detail below with reference to fig. 4 and 5:
as shown in fig. 4 and 5, the equalizing circuit 10 operates as follows:
after receiving the signal to be equalized, the input port 11 of the equalization circuit 10 performs signal attenuation on the signal to be equalized by a T-shaped attenuation circuit composed of a first resistor R1, a second resistor R2 and a third resistor R3.
On the other hand, the filter circuit formed by the first capacitor C1 and the first inductor L1 filters the signal to be equalized, so as to filter the signal in the first frequency range in the signal to be equalized.
Meanwhile, the filter circuit formed by the second capacitor C2 and the second inductor L2 filters the signals to be equalized after being attenuated by the T-shaped attenuation circuit so as to filter out signals in a second frequency range in the attenuated signals to be equalized.
Based on this, the output port 14 can output the final signal obtained by the filtering processing by the respective filter circuits and the attenuation by the T-shaped attenuation circuit, that is, the signal after the amplitude equalization has been completed.
Referring to fig. 6, fig. 6 is an S-parameter simulation graph of an equalizing circuit according to an embodiment of the present application.
In this embodiment, the S parameter specifically refers to a forward transmission parameter (i.e., gain) S21.
As shown in fig. 6, a curve Q1 is a forward transmission parameter (S21) obtained by performing a simulation test on the equalization circuit, that is, a gain simulation curve.
Referring to fig. 7, fig. 7 is a return loss simulation graph of an equalizing circuit according to an embodiment of the present application. As shown in fig. 7, a curve Q2 is an input reflection coefficient (S11) obtained by performing a simulation test on the equalization circuit, that is, an input return loss curve, and a curve Q3 is an output reflection coefficient (S22) obtained by performing a simulation test on the equalization circuit, that is, an output return loss curve.
An embodiment of the present application further provides an equalization system, referring to fig. 8, and fig. 8 is a schematic structural diagram of the equalization system provided in the embodiment of the present application. As shown in fig. 8, the equalization system 1 includes an equalization circuit 10 and a signal generation circuit 20, and the signal generation circuit 20 is electrically connected to the equalization circuit 10. The equalization circuit 10 may be the equalization circuit 10 in any embodiment corresponding to fig. 1 to 5.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference may be made to related descriptions of other embodiments.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. An equalization circuit, comprising:
an input port for receiving a signal to be equalized;
the signal attenuation module is connected with the input port and used for attenuating the signal to be equalized;
the signal filtering module is connected with the input port and the signal attenuation module and is used for respectively carrying out filtering treatment on the signal to be equalized and the attenuated signal to be equalized;
and the output port is connected with the signal attenuation module and the signal filtering module and is used for outputting signals obtained after being processed by the signal attenuation module and the signal filtering module.
2. The equalization circuit of claim 1, wherein the signal filtering module comprises;
the first filtering unit is connected with the input port and is used for filtering the signal to be equalized so as to filter out the signal in the first frequency range;
the second filtering unit is connected with the signal attenuation module and is used for filtering the attenuated signal to be equalized so as to filter out signals in a second frequency range; the lower limit of the first frequency range is greater than the upper limit of the second frequency range.
3. The equalization circuit of claim 1, wherein an input of the signal attenuation module is connected to the input port, a first output of the signal attenuation module is connected to the output port, and a second output of the signal attenuation module is connected to the first input of the signal filtering module; the signal attenuation module comprises a first resistor, a second resistor and a third resistor;
the first end of the first resistor is an input end of the signal attenuation module, the second end of the first resistor and the first end of the second resistor are connected to the first end of the third resistor, the second end of the third resistor is a first output end of the signal attenuation module, and the second end of the second resistor is a second output end of the signal attenuation module.
4. The equalizing circuit of claim 3, wherein the amount of attenuation of the signal to be equalized by the equalizing circuit is determined based on the resistance of the first resistor, the resistance of the second resistor, and the resistance of the third resistor.
5. The equalization circuit of claim 2, wherein an input of the first filter unit is connected to the input port, an output of the first filter unit is connected to the output port, and the first filter unit comprises a first capacitor and a first inductor;
the first end of the first capacitor is the input end of the first filtering unit, the second end of the first capacitor is connected with the first end of the first inductor, and the second end of the first inductor is the output end of the first filtering unit.
6. The equalization circuit of claim 5, wherein the first frequency range is determined based on a first capacitance value of the first capacitor and a first inductance value of the first inductor.
7. The equalization circuit of claim 2, wherein an input of the second filter unit is connected to a first output of the signal attenuation module, the first filter unit comprising a second capacitor and a second inductor;
the first end of the second capacitor and the first end of the second inductor are commonly connected and serve as the input end of the second filtering unit, the second end of the second capacitor is grounded, and the second end of the second inductor is grounded.
8. The equalization circuit of claim 1, wherein the equalization circuit further comprises: the first grounding port, the second grounding port, the third grounding port and the fourth grounding port;
the first grounding port and the second grounding port are positioned on two sides of the input port, and the first distance and the second distance are equal; the first distance refers to a distance between the first ground port and the input port; the second distance refers to a distance between the second ground port and the input port;
the third grounding port and the fourth grounding port are positioned on two sides of the output port, and the third distance and the fourth distance are equal; the third distance refers to a distance between the third ground port and the output port; the fourth distance refers to a distance between the fourth ground port and the output port.
9. Equalization circuit according to any of claims 1-8, characterized in that the equalization circuit is a circuit built on a substrate layer based on thin film passive device technology.
10. An equalization system comprising a signal generating circuit for generating a signal to be equalized and an equalization circuit as claimed in any one of claims 1-9; the signal generating circuit is electrically connected with the equalizing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311767053.1A CN117674756A (en) | 2023-12-21 | 2023-12-21 | Equalization circuit and equalization system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311767053.1A CN117674756A (en) | 2023-12-21 | 2023-12-21 | Equalization circuit and equalization system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117674756A true CN117674756A (en) | 2024-03-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN202311767053.1A Pending CN117674756A (en) | 2023-12-21 | 2023-12-21 | Equalization circuit and equalization system |
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| Country | Link |
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| CN (1) | CN117674756A (en) |
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2023
- 2023-12-21 CN CN202311767053.1A patent/CN117674756A/en active Pending
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