CN117637829B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents
Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDFInfo
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- CN117637829B CN117637829B CN202311556312.6A CN202311556312A CN117637829B CN 117637829 B CN117637829 B CN 117637829B CN 202311556312 A CN202311556312 A CN 202311556312A CN 117637829 B CN117637829 B CN 117637829B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 21
- 238000009826 distribution Methods 0.000 abstract description 15
- 230000002829 reductive effect Effects 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 67
- 238000004519 manufacturing process Methods 0.000 description 17
- 239000011229 interlayer Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a semiconductor device, which comprises: a semiconductor substrate; a drift layer; a hoop layer; the main groove part is arranged on the annular layer and extends in the first direction, the main groove part comprises a plurality of gate groove groups and a plurality of dummy gate groove parts, the gate groove groups are arranged at intervals in the second direction, at least one dummy gate groove part is arranged between two adjacent gate groove groups, and the gate groove groups comprise at least two gate groove parts arranged at intervals in the second direction; the connecting groove part is arranged on the annular layer and extends in the second direction, the connecting groove part is positioned at the edge of the active region of the semiconductor device, and at least one end of at least two gate groove parts in each gate groove group are communicated by the connecting groove part. Therefore, the electric field distribution of the semiconductor device can be optimized, the electrostatic protection capability and the insulation breakdown voltage withstand capability of the semiconductor device can be improved, the opening speed of the semiconductor device can be improved, and the opening loss can be reduced.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device.
Background
With the development of technology, semiconductor devices are increasingly used. The semiconductor device is provided with a groove during design and production and manufacture, and a grid can be formed at the groove, so that the normal operation of the semiconductor device is ensured.
In the related art, the trench is mostly in a stripe shape, and the electrostatic protection of the semiconductor device is easily disabled at the edge of the trench, resulting in lower stability and reliability of the semiconductor device.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, an object of the present invention is to provide a semiconductor device with better electrostatic protection capability, higher stability and reliability.
The semiconductor device according to an embodiment of the present invention includes: a semiconductor body having a first main surface and a second main surface opposite to the first main surface; a drift layer provided on the semiconductor body and located between the first main surface and the second main surface; a ring layer provided on a side of the drift layer facing the first main surface, wherein a side surface of the ring layer facing away from the drift layer forms a portion of the first main surface; the main groove part is arranged on the annular layer and extends in the first direction, the main groove part comprises a plurality of gate groove groups and a plurality of dummy gate groove parts, the gate groove groups are arranged at intervals in the second direction, at least one dummy gate groove part is arranged between two adjacent gate groove groups, and the gate groove groups comprise at least two gate groove parts arranged at intervals in the second direction; the connecting groove part is arranged on the annular layer and extends in a second direction, the connecting groove part is positioned at the edge of the active region of the semiconductor device, and the connecting groove part communicates at least one end of at least two gate groove parts in each gate groove group, wherein the first direction is perpendicular to the second direction.
Therefore, the connecting groove parts are arranged on the annular layer and extend in the second direction, the connecting groove parts are positioned at the edge of the active region of the semiconductor device, and at least one end of at least two gate groove parts in each gate groove group are communicated by the connecting groove parts, so that the electric field distribution of the semiconductor device can be optimized, the electrostatic protection capability and the insulation breakdown voltage withstand capability of the semiconductor device can be improved, the opening speed of the semiconductor device can be improved, and the opening loss can be reduced.
In some examples of the present invention, the connection trench portions are provided at both ends of at least two of the gate trench portions in each of the gate trench groups.
In some examples of the invention, the dummy gate trench portion is disposed between at least two of the gate trench portions in each of the gate trench groups.
In some examples of the invention, each of the gate trench groups includes two of the gate trench portions, and the connecting trench portion communicates at least one end of the two of the gate trench portions in each of the gate trench groups.
In some examples of the invention, the connecting trench portion communicates at least one end of a plurality of the gate trench groups.
In some examples of the present invention, the length of the first direction of the gate trench portion is greater than the length of the first direction of the dummy gate trench portion, two ends of the first direction of the gate trench portion protrude from two ends of the first direction of the dummy gate trench portion, and the connection trench portion is elongated and spaced apart from the dummy gate trench portion.
In some examples of the invention, the connecting trench portion communicates a plurality of gate trench groups and at least one end of a plurality of the dummy gate trench portions.
In some examples of the invention, the length of the dummy gate trench portion in the first direction is equal to the length of the gate trench portion in the first direction, and both ends of the gate trench portion in the first direction are flush with both ends of the dummy gate trench portion in the first direction.
In some examples of the invention, the connection trench portion communicates at least one end of a plurality of the dummy gate trench portions.
In some examples of the present invention, the length of the dummy gate trench portion in the first direction is greater than the length of the gate trench portion in the first direction, and both ends of the dummy gate trench portion in the first direction protrude from both ends of the gate trench portion in the first direction.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a top view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic view of region A of FIG. 1;
FIG. 3 is a schematic view of region B of FIG. 1;
Fig. 4 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention along A-A;
fig. 5 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention along the B-B direction;
fig. 6 is a partial schematic view of a semiconductor device according to another embodiment of the present invention;
fig. 7 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;
fig. 8 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;
Fig. 9 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;
fig. 10 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Reference numerals:
100. a semiconductor device;
10. a semiconductor substrate; 101. a first major face; 102. a second major face; 103. an active region; 104. a termination region;
11. A drift layer; 12. a hoop layer; 13. oxidizing the insulating layer; 14. a polycrystalline layer; 15. an interlayer dielectric layer; 16. an emitter metal layer; 17. a field stop layer; 18. a collector layer; 19. a contact hole;
20. A main groove portion; 21. a gate trench portion; 22. a dummy gate trench portion; 23. a gate trench set; 24. a dummy gate trench set;
30. a connection groove portion; 31. a sub-connection trench; 40. and a gate pad.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
A semiconductor device 100 according to an embodiment of the present invention is described below with reference to fig. 1 to 10. In the following description, N and P denote the conductivity types of semiconductors, and in the present invention, the first conductivity type is referred to as P-type, and the second conductivity type is referred to as N-type.
As shown in connection with fig. 1 to 6, a semiconductor device 100 according to the present invention may mainly include: the semiconductor substrate 10 includes a first main surface 101 and a second main surface 102 opposite to the first main surface 101, the ring layer 12 is provided on a side of the drift layer 11 facing the first main surface 101, a surface of the ring layer 12 on a side away from the drift layer 11 forms a portion of the first main surface 101, and the main trench 20 is provided on the ring layer 12 and extends in a first direction perpendicular to the second direction.
Specifically, the semiconductor body 10 has a first main surface 101 and a second main surface 102, the ring layer 12 and the drift layer 11 are both located between the first main surface 101 and the second main surface 102, the ring layer 12 is provided on a side of the drift layer 11 facing the first main surface 101, a side surface of the ring layer 12 remote from the drift layer 11 constitutes a portion of the first main surface 101, an oxide insulating layer 13, a polycrystalline layer 14, and an interlayer dielectric layer 15 are further stacked on top of the ring layer 12, and a field stop layer 17 and a collector layer 18 are further provided under the drift layer 11.
Further, the ring layer 12 is provided with a main trench portion 20, and the main trench portion 20 is provided to extend in the first direction, so that a gate electrode can be formed at the main trench portion 20, and an emitter metal layer 16 is provided over the interlayer dielectric layer 15 and a collector metal layer (not shown) is provided under the collector layer 18, so that a basic structure of the semiconductor device 100 can be formed, ensuring normal operation of the semiconductor device 100.
Wherein the main trench portion 20 may mainly include a plurality of gate trench groups 23 and a plurality of dummy gate trench portions 22, the plurality of gate trench groups 23 are spaced apart in the second direction, at least one dummy gate trench portion 22 is disposed between two adjacent gate trench groups 23, the gate trench groups 23 include at least two gate trench portions 21 spaced apart in the second direction,
Specifically, the gate trench portion 21 and the dummy gate trench portion 22 are both provided with the oxide insulating layer 13 and polysilicon is deposited, but the first conductivity type dopant is injected into the gate trench portion 21 and the second conductivity type well region is provided, the gate may be formed at the gate trench portion 21, and a conductive channel having a current passing capability is provided, ensuring normal operation of the semiconductor device 100, while the first conductivity type dopant is not injected at the dummy gate trench portion 22, and the second conductivity type well region is not provided, and the conductive channel and the current passing capability are not provided, and the dummy gate trench portion 22 may be connected to the emitter, reducing miller capacitance, and reducing current density.
By forming at least two gate trench portions 21 into one gate trench group 23, forming at least one dummy gate trench portion 22 into one dummy gate trench group 24, and disposing the gate trench group 23 and the dummy gate trench group 24 in plural, the plural gate trench groups 23 and the plural dummy gate trench groups 24 are alternately disposed in sequence in the second direction, the disposition of the plural gate trench portions 21 and the plural dummy gate trench portions 22 in the second direction can be made more reasonable, thereby further improving the operation performance of the semiconductor device 100.
As shown in fig. 1 to 4 and fig. 6, the semiconductor device 100 of the present invention may further include: and a connection trench portion 30, the connection trench portion 30 being disposed on the ring layer 12 and extending in a second direction, the connection trench portion 30 being located at an edge of the active region 103 of the semiconductor device 100, the connection trench portion 30 communicating at least one end of at least two gate trench portions 21 in each gate trench group 23, wherein the first direction is perpendicular to the second direction.
Specifically, at least two gate trench portions 21 in each gate trench group 23 are disposed at intervals in the second direction, that is: the end portions of at least two gate trench portions 21 in each gate trench group 23 are also arranged at intervals in the second direction, and considering that the area where the end portions of the gate trench portions 21 are located is relatively concentrated in electric field distribution, the electric field distribution is not uniform enough, and static electricity protection failure is liable to occur, and the dielectric breakdown withstand voltage is also relatively low, by arranging the connecting trench portions 30 on the ring layer 12, the connecting trench portions 30 are arranged to extend in the second direction, and the connecting trench portions 30 are located at the edges of the active region 103 of the semiconductor device 100, so that the connecting trench portions 30 communicate at least one end of at least two gate trench portions 21 in each gate trench group 23, and thus the connecting trench portions 30 can enclose at least one end of at least two gate trench portions 21 in the first direction in each gate trench group 23, so that the connecting trench portions 30 communicate with at least two gate trench portions 21 in each gate trench group 23.
On the one hand, the connecting trench portion 30 surrounds the outer sides of the end portions of the at least two gate trench portions 21 in each gate trench group 23, so that the electric field distribution of the end portions of the at least two gate trench portions 21 in each gate trench group 23 can be optimized, the electric field distribution of the end portions of the at least two gate trench portions 21 in each gate trench group 23 can be more uniform, thereby effectively improving the electrostatic protection capability of the semiconductor device 100, avoiding the electrostatic failure of the semiconductor device 100 at the end portions of the main trench portion 20, improving the dielectric breakdown voltage capability of the semiconductor device 100, and further improving the reliability of the semiconductor device 100.
On the other hand, the connection trench portion 30 can be used as a gate via, so that the gate via can be increased, the opening speed of the semiconductor device 100 can be increased, and the opening loss can be reduced.
Thus, by providing the connection trench portion 30, the connection trench portion 30 is provided in the ring layer 12 and extends in the second direction, the connection trench portion 30 is located at the edge of the active region 103 of the semiconductor device 100, and the connection trench portion 30 communicates at least one end of at least two gate trench portions 21 in each gate trench group 23, so that not only the electric field distribution of the semiconductor device 100 can be optimized, but also the electrostatic protection capability and the dielectric breakdown withstand voltage capability of the semiconductor device 100 can be improved, the turn-on speed of the semiconductor device 100 can be increased, and the turn-on loss can be reduced.
As shown in fig. 6, both ends of at least two gate trench portions 21 in each gate trench group 23 are provided with connection trench portions 30. Specifically, the gate trench portions 21 have two ends in the first direction, and by providing the connection trench portions 30 at two ends of at least two gate trench portions 21 in each gate trench group 23, such that the connection trench portion 30 at one end can connect one ends of at least two gate trench portions 21 to communicate with each other, and the connection trench portion 30 at the other end can connect the other ends of at least two gate trench portions 21 to communicate with each other, all ends of each gate trench group 23 can be communicated with the connection trench portion 30, and non-communicated ends of each gate trench group 23 are avoided, electric field distribution of the semiconductor device 100 can be further optimized, electrostatic protection capability and dielectric breakdown capability of the semiconductor device 100 can be improved, and turn-on speed of the semiconductor device 100 can be further improved.
Since the semiconductor device 100 is provided with the gate pad 40, the gate pad 40 is used for connection to the gate, and the gate trench portion 21 and the dummy gate trench portion 22 are disconnected at the gate pad 40 as gate lead-out terminals, the connection trench portion 30 can be provided also at the end portion of the gate trench group 23 on the side close to the gate pad 40, and the connection trench portion 30 can be made to communicate with the end portion of the gate trench group 23 on the side close to the gate pad 40, thereby improving the electrostatic protection capability of the semiconductor device 100 more reliably and the turn-on speed of the semiconductor device 100.
In some embodiments of the present invention, a dummy gate trench portion 22 is provided between at least two gate trench portions 21 in each gate trench group 23. Specifically, a dummy gate trench portion 22 may be provided between at least two gate trench portions 21 in each gate trench group 23, and the length of the dummy gate trench portion 22 in the first direction is not greater than the length of the gate trench portion 21, so that the provision of the dummy gate trench portion 22 can be prevented from affecting the connection of the connection trench portion 30 to at least one end of at least two gate trench portions 21 in each gate trench group 23.
In one embodiment of the present invention, as shown in connection with fig. 6, each gate trench group 23 may mainly include two gate trench portions 21, and a connection trench portion 30 communicates at least one end of the two gate trench portions 21 in each gate trench group 23. Specifically, each gate trench group 23 may mainly include two gate trench portions 21, and the connecting trench portion 30 communicates at least one end of the two gate trench portions 21 in each gate trench group 23, so that the arrangement of the number of gate trench portions 21 in each gate trench group 23 may be made more reasonable, and the arrangement of the connecting trench portion 30 may also be facilitated.
As shown in connection with fig. 1-3, the connecting trench portion 30 communicates at least one end of the plurality of gate trench groups 23.
Specifically, considering that when the connection trench portions 30 connect at least two gate trench portions 21 in each gate trench group 23, although the electric field distribution of the semiconductor device 100 can be optimized to some extent to improve the electrostatic protection capability and the dielectric breakdown capability of the semiconductor device 100, the plurality of gate trench groups 23 are still in an unconnected state, and there is still an end region of each gate trench group 23 in the second direction where the electric field still concentrates, the electrostatic protection capability and the dielectric breakdown capability of the semiconductor device 100 still remain to be improved.
By connecting the connection trench portion 30 to at least one end of the plurality of gate trench groups 23, it is possible to facilitate connection of the connection trench portion 30 to at least one end of all gate trench portions 21 of the semiconductor device 100, so that the connection trench portion 30 can surround at least one end of all gate trench portions 21 of the semiconductor device 100, and the connection trench portion 30 can communicate with at least one end of all gate trench portions 21 of the semiconductor device 100.
On the one hand, the connection trench portion 30 surrounds the outer sides of the end portions of all gate trench portions 21, so that not only the electric field distribution of the end portions of all gate trench portions 21 can be optimized, and the electric field distribution of the end portions of all gate trench portions 21 can be more uniform, the electric field concentration at the end portions of all gate trench portions 21 can be avoided, but also the gate oxide thickness of the end portions of all gate trench portions 21 can be increased, thereby effectively improving the electrostatic protection capability of the semiconductor device 100, avoiding the electrostatic failure of the semiconductor device 100 at the end portions of the gate trench portions 21, and improving the reliability of the semiconductor device 100.
On the other hand, the connection trench portion 30 can be used as a gate via, so that the gate via can be increased, the opening speed of the semiconductor device 100 can be increased, the opening loss can be reduced, and the operation performance of the semiconductor device 100 can be improved.
On the other hand, in order to ensure the normal extraction of the current, it is necessary to provide a contact hole 19 in the semiconductor device 100, wherein the contact hole 19 can connect the gate electrode with other materials, thereby realizing the function of the circuit, and by providing a connection trench 30, the connection trench 30 is communicated with the ends of the plurality of gate trench 21, so that the contact hole 19 can be directly provided in the connection trench 30 on the premise of ensuring the normal operation of the semiconductor device 100, thereby facilitating the manufacture of the contact hole 19 and reducing the manufacturing difficulty of the contact hole 19 and the semiconductor device 100.
Thus, not only the electric field distribution of the semiconductor device 100 can be optimized, the electrostatic protection capability of the semiconductor device 100 can be improved, but also the turn-on speed of the semiconductor device 100 can be increased, the turn-on loss can be reduced, and the manufacturing difficulty of the semiconductor device 100 can be reduced.
In some embodiments of the present invention, as shown in fig. 1-3, the length of the first direction of the gate trench portion 21 is greater than the length of the first direction of the dummy gate trench portion 22, two ends of the first direction of the gate trench portion 21 protrude from two ends of the first direction of the dummy gate trench portion 22, and the connection trench portion 30 is in a strip shape and is spaced apart from the dummy gate trench portion 22.
Specifically, in consideration of the fact that the dummy gate trench portion 22 does not have the conductive capability, the electrostatic failure does not occur at the end portion of the dummy gate trench portion 22, and when the length of the first direction of the gate trench portion 21 is greater than the length of the first direction of the dummy gate trench portion 22, and both ends of the first direction of the gate trench portion 21 protrude from both ends of the first direction of the dummy gate trench portion 22, it is only necessary to communicate the connection trench portion 30 with each gate trench group 23 without communicating the plurality of dummy gate trench groups 24, and the connection trench portion 30 is elongated and spaced apart from the dummy gate trench portion 22, the electrostatic protection capability of the semiconductor device 100 can be improved, and the turn-on speed of the semiconductor device 100 can be increased, so that the manufacturing cost of the semiconductor device 100 can be reduced.
In other embodiments of the present invention, the connecting trench portion 30 communicates at least one end of the plurality of gate trench groups 23 and the plurality of dummy gate trench portions 22. Specifically, the connecting trench portion 30 may be also made to communicate at least one ends of the plurality of gate trench groups 23 and the plurality of dummy gate trench portions 22, that is: the connection trench portion 30 may communicate at least one end of all the main trench portions 20, so that the connection trench portion 30 may be opened conveniently on the premise of optimizing the electric field distribution of the semiconductor device 100, and the manufacturing difficulty of the semiconductor device 100 may be reduced.
Further, the length of the dummy gate trench portion 22 in the first direction is equal to the length of the gate trench portion 21 in the first direction, and both ends of the gate trench portion 21 in the first direction are flush with both ends of the dummy gate trench portion 22 in the first direction. Specifically, when the length of the dummy gate trench portion 22 in the first direction of the semiconductor device 100 is equal to the length of the gate trench portion 21 in the first direction, both ends of the gate trench portion 21 in the first direction are flush with both ends of the dummy gate trench portion 22 in the first direction, the connection trench portion 30 may be directly connected between the end of the gate trench portion 21 and the end of the dummy gate trench portion 22, so that the connection trench portion 30 penetrates the active region 103 of the semiconductor device 100 in the first direction, and the structure of the semiconductor device 100 is simpler and more reliable.
In still other embodiments of the present invention, the connecting trench portions 30 communicate at least one end of the plurality of dummy gate trench portions 22. Specifically, on the premise that the connection trench portion 30 is provided to connect at least one end of the plurality of gate trench portions 21 in each gate trench group 23, the connection trench portion 30 may be additionally provided, so that the connection trench portion 30 communicates at least one end of the plurality of dummy gate trench portions 22 between two adjacent gate trench groups 23, so that on one hand, the connection trench portion 30 may optimize electric field distribution of at least one end of the plurality of dummy gate trench portions 22, avoid electric field concentration, and improve reliability of the semiconductor device 100, and on the other hand, may facilitate respective designs of the connection trench portion 30 and the dummy gate trench portions 22, and expand application scenarios of the semiconductor device 100.
Further, the length of the dummy gate trench portion 22 in the first direction is longer than the length of the gate trench portion 21 in the first direction, and both ends of the dummy gate trench portion 22 in the first direction protrude from both ends of the gate trench portion 21 in the first direction. Specifically, when the length of the dummy gate trench portion 22 in the first direction of the semiconductor device 100 is greater than the length of the gate trench portion 21 in the first direction, both ends of the dummy gate trench portion 22 in the first direction protrude from both ends of the gate trench portion 21 in the first direction, the connection trench portion 30 may be separately provided in each gate trench group 23, and the connection trench portion 30 may be separately provided between the plurality of dummy gate trench portions 22 between the adjacent two gate trench groups 23, so that the two can be prevented from affecting each other, and the electrostatic protection capability and the insulation breakdown withstand voltage capability of the semiconductor device 100 can be ensured.
As shown in fig. 4 and 5, the main groove portion 20 and the connecting groove portion 30 are each provided to extend in a direction from the first main surface 101 toward the second main surface 102, the depth of the main groove portion 20 is L1 in the direction from the first main surface 101 to the second main surface 102, the depth of the connecting groove portion 30 is L2, and the L1 and L2 satisfy the relation: l1 is less than or equal to L2.
Specifically, by setting the depth of the connection trench portion 30 to be not smaller than the depth of the main trench portion 20 in the direction from the first main surface 101 to the second main surface 102, the connection trench portion 30 can completely connect the main trench portion 20 in the direction from the first main surface 101 to the second main surface 102, the shortage of the depth of the connection trench portion 30 is avoided, the lower side of the main trench portion 20 is not communicated with the connection trench portion 30, the electric field distribution under the main trench portion 20 is uneven, the electrostatic protection of the semiconductor device 100 is still easy to fail, and thus, the optimization of the electric field at each position of the end of the main trench portion 20 can be ensured, and the electrostatic protection capability of the semiconductor device 100 is further improved.
As shown in fig. 4 and 5, the width of the main groove portion 20 in the second direction is W1, the width of the connecting groove portion 30 in the first direction is W2, and W1 and W2 satisfy the relation: w1 is less than or equal to W2.
Specifically, the width of the connection trench portion 30 in the first direction may affect the via size of the connection trench portion 30, and by setting the width of the connection trench portion 30 in the first direction to be not smaller than the width of the main trench portion 20 in the second direction, the via capability of the connection trench portion 30 may be further increased on the premise of increasing the gate via through the connection trench portion 30, so that the turn-on speed of the semiconductor device 100 may be further improved, and the loss of the semiconductor device 100 may be reduced.
Preferably, the depth of the connection trench portion 30 may be set to be the same as the depth of the main trench portion 20 in the direction from the first main surface 101 to the second main surface 102, and the width of the connection trench portion 30 in the first direction may be set to be the same as the width of the main trench portion 20 in the second direction, so that on the premise of improving the electrostatic protection capability of the semiconductor device 100 and the switching speed of the semiconductor device 100, the synchronous etching of the main trench portion 20 and the connection trench portion 30 may be facilitated, and the structures may be the same or almost the same, so that the processing complexity may be reduced and the production efficiency may be improved.
As shown in fig. 4 and 5, the main trench portion 20 and the connection trench portion 30 are each provided at a distance from the drift layer 11. Specifically, the main trench portion 20 and the connection trench portion 30 are etched and formed on the ring layer 12, and by disposing both the main trench portion 20 and the connection trench portion 30 at a distance from the drift layer 11, namely: the main trench portion 20 and the connection trench portion 30 are not formed to penetrate the ring layer 12, and the main trench portion 20 and the connection trench portion 30 are provided to be spaced apart from the drift layer 11, so that the presence of the field ring layer 12 between the main trench portion 20 and the connection trench portion 30 and the drift layer 11 can be ensured, and the electrical performance of the semiconductor device 100 can be ensured.
As shown in fig. 1 and 2, the semiconductor body 10 may include an active region 103 and a termination region 104, the termination region 104 being disposed around the outside of the active region 103, the main trench portion 20 being disposed in the active region 103, and the connection trench portion 30 being located between the active region 103 and the termination region 104.
Specifically, the active region 103 may not only bear most of the forward current during forward conduction, but also bear high blocking voltage when a reverse voltage is applied, and the termination region 104 may relieve electric field crowding at the edge of the active region 103 when the semiconductor device 100 is applied with the reverse voltage, thereby achieving the purpose of increasing the reverse breakdown voltage of the semiconductor device 100.
Further, the main trench portion 20 is disposed in the active region 103, and the end portion of the main trench portion 20 is located between the active region 103 and the terminal region 104, and by disposing the connection trench portion 30 between the active region 103 and the terminal region 104, the connection trench portion 30 can block the diffusion of the electric field of the active region 103, can more effectively and reliably avoid the failure of the electrostatic protection at the region between the active region 103 and the terminal region 104, and can improve the electrostatic protection capability of the semiconductor device 100.
The following describes an example of the fabrication method of the semiconductor device 100 with reference to fig. 7 to 10:
as shown in fig. 7, a substrate, which is an N-type drift layer 11, is provided, and P-type dopants are implanted on the substrate to form the N-type drift layer 11 and a P-type ring layer 12.
As shown in fig. 8, the connection trench portion 30 is etched in the ring layer 12, and the oxide insulating layer 13 is grown over the ring layer 12.
As shown in fig. 9, polysilicon deposition and polysilicon etching are performed over the oxide insulating layer 13 to form a polysilicon layer 14.
As shown in fig. 10, an interlayer dielectric is grown over the polycrystalline layer 14, an interlayer dielectric layer 15 is formed, metal sputtering is performed over the interlayer dielectric layer 15, an emitter metal layer 16 is formed, and a field stop layer 17, a collector layer 18, and a collector metal layer are prepared under the drift layer 11, to finally form the semiconductor device 100.
It should be noted that, in this manufacturing method, only the manufacturing of the connection trench portion 30 is taken as an example, and the main trench portion 20 may be etched simultaneously while the connection trench portion 30 is etched on the ring layer 12, which is not described herein. And, the manufacturing method is merely illustrative of a part of the manufacturing process, and other constitution and operation of the semiconductor device 100 according to the embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A semiconductor device, comprising:
a semiconductor body having a first main surface and a second main surface opposite to the first main surface;
a drift layer provided on the semiconductor body and located between the first main surface and the second main surface;
a ring layer provided on a side of the drift layer facing the first main surface, wherein a side surface of the ring layer facing away from the drift layer forms a portion of the first main surface;
The main groove part is arranged on the annular layer and extends in the first direction, the main groove part comprises a plurality of gate groove groups and a plurality of dummy gate groove parts, the gate groove groups are arranged at intervals in the second direction, at least one dummy gate groove part is arranged between two adjacent gate groove groups, and the gate groove groups comprise at least two gate groove parts arranged at intervals in the second direction;
The semiconductor substrate comprises an active area and a terminal area, the terminal area is arranged on the outer side of the active area in a surrounding mode, the main groove portion is arranged in the active area, the end portion of the main groove portion is located between the active area and the terminal area, the connecting groove portion is arranged between the active area and the terminal area, and the connecting groove portion is used for communicating at least two at least one ends of the gate groove portions in each gate groove group, wherein the first direction is perpendicular to the second direction.
2. The semiconductor device according to claim 1, wherein both ends of at least two of the gate trench portions in each of the gate trench groups are provided with the connection trench portions.
3. The semiconductor device according to claim 1, wherein the dummy gate trench portion is provided between at least two of the gate trench portions in each of the gate trench groups.
4. The semiconductor device according to claim 1, wherein each of the gate trench groups includes two of the gate trench portions, the connection trench portion connecting at least one ends of the two gate trench portions in each of the gate trench groups.
5. The semiconductor device according to claim 1, wherein the connection trench portion communicates at least one end of the plurality of gate trench groups.
6. The semiconductor device according to claim 5, wherein a length of the gate trench portion in the first direction is longer than a length of the dummy gate trench portion in the first direction, both ends of the gate trench portion in the first direction protrude from both ends of the dummy gate trench portion in the first direction, and the connection trench portion is elongated and spaced apart from the dummy gate trench portion.
7. The semiconductor device according to claim 1, wherein the connection trench portion communicates a plurality of the gate trench groups and at least one end of a plurality of dummy gate trench portions.
8. The semiconductor device according to claim 7, wherein a length of the dummy gate trench portion in the first direction is equal to a length of the gate trench portion in the first direction, and both ends of the gate trench portion in the first direction are flush with both ends of the dummy gate trench portion in the first direction.
9. The semiconductor device according to claim 1, wherein the connection trench portion communicates at least one end of the plurality of dummy gate trench portions.
10. The semiconductor device according to claim 9, wherein a length of the dummy gate trench portion in the first direction is longer than a length of the gate trench portion in the first direction, and both ends of the dummy gate trench portion in the first direction protrude from both ends of the gate trench portion in the first direction.
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| CN107924951A (en) * | 2016-03-10 | 2018-04-17 | 富士电机株式会社 | Semiconductor device |
| CN108257953A (en) * | 2016-12-29 | 2018-07-06 | 英飞凌科技股份有限公司 | The semiconductor devices of diode region not can be switched with IGBT areas and |
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| DE112017000727T5 (en) * | 2016-09-14 | 2018-10-31 | Fuji Electric Co., Ltd. | RC-IGBT and manufacturing process for it |
| CN109713037B (en) * | 2018-12-29 | 2021-11-23 | 安建科技(深圳)有限公司 | Insulated gate bipolar transistor device and preparation method thereof |
| JP7533146B2 (en) * | 2020-11-16 | 2024-08-14 | 三菱電機株式会社 | Semiconductor Device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107924951A (en) * | 2016-03-10 | 2018-04-17 | 富士电机株式会社 | Semiconductor device |
| CN108257953A (en) * | 2016-12-29 | 2018-07-06 | 英飞凌科技股份有限公司 | The semiconductor devices of diode region not can be switched with IGBT areas and |
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