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CN117637457A - Methods of fabricating ohmic contacts for electronic devices with thermal budget optimization - Google Patents

Methods of fabricating ohmic contacts for electronic devices with thermal budget optimization Download PDF

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Publication number
CN117637457A
CN117637457A CN202311081391.XA CN202311081391A CN117637457A CN 117637457 A CN117637457 A CN 117637457A CN 202311081391 A CN202311081391 A CN 202311081391A CN 117637457 A CN117637457 A CN 117637457A
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forming
layer
semiconductor body
ohmic contact
region
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M·G·萨吉奥
C·M·卡玛勒里
G·贝洛基
S·拉斯库纳
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STMicroelectronics SRL
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STMicroelectronics SRL
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Priority claimed from US18/363,349 external-priority patent/US20240079237A1/en
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Publication of CN117637457A publication Critical patent/CN117637457A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

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Abstract

Embodiments of the present disclosure relate to methods of fabricating ohmic contacts for electronic devices with thermal budget optimization. A method of fabricating an electronic device includes forming an ohmic contact at an implanted region of a semiconductor body. The ohmic contact is formed to perform a high temperature heat treatment to allow a reaction between the metal material and the material of the semiconductor body to form a silicide of the metal material. The step of forming ohmic contacts is performed prior to the step of forming one or more electrical structures comprising a material that may be damaged due to the high temperature of the heat treatment for forming the silicide.

Description

Method of fabricating ohmic contacts for electronic devices with thermal budget optimization
Technical Field
The present disclosure relates to a method of manufacturing an electronic device, and more particularly to the manufacture of ohmic contacts for an electronic device.
Background
Semiconductor materials with a wide band gap, in particular with a high band gap value, low on-resistance (R ON ) Semiconductor materials with high thermal conductivity values, high operating frequencies, and high charge carrier saturation velocities are ideal for producing electronic components such as diodes or transistors, especially for electrical applications. A material having the characteristics and suitable for use in manufacturing electronic components is silicon carbide (SiC). In particular, silicon carbide of different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC) is preferred over silicon with respect to the properties listed above.
Hexagonal SiC polytype (4H-SiC) is the most polytype studied so far, and 4H-SiC wafers have been currently realized in commercial mass production, but at a higher cost than typical silicon wafers.
An electronic device provided with a silicon carbide substrate also has advantages such as low on-output resistance, low leakage current, and high operating frequency, as compared with a similar device provided with a silicon substrate. In particular, siC schottky diodes exhibit higher switching performance, making SiC electronic devices particularly suitable for high frequency applications.
Many scientific papers also report good switching performance of silicon carbide (SiC) MOSFET devices. From an industrial point of view, siC MOSFET devices have good structural robustness in addition to switching performance, which is a desirable feature in power systems.
A related structural element in SiC (particularly 4H-SiC) MOSFET devices is the gate dielectric (or oxide). The properties of the gate dielectric (dielectric constant, fixed charge, etc.) and the quality of the dielectric/SiC interface (interface state density D it Near-interface oxideTrap, NIOT) versus MOSFET dependent parameters (such as field effect channel mobility μ FE On-state resistance and threshold voltage V th ) Has significant impact. Therefore, gate dielectric optimization is a precondition for fully exploiting SiC MOSFET performance.
Since SiC is easily produced by thermal oxidation, silicon oxide (SiO 2 ) Are commonly used as gate dielectrics in commercial SiC MOSFETs. However, siC has a lower oxidation rate than silicon and a interface state density ratio of SiO 2 The interface state density of the/Si stack is about 2-3 orders of magnitude higher. To reduce the use of SiO 2 Interface state density D of 4H-SiC MOSFET as gate dielectric it And improves channel mobility mu FE Usually in the presence of nitrogen (N) 2 O, NO) is performed in an ambient of post-oxidation anneal (POA) or post-deposition anneal (PDA) step. However, thermal oxidation of SiC and POA and PDA processes typically require high temperatures ±>1100 ℃) and long annealing times (up to 8 hours in some cases). Furthermore, all these processes result in the presence of SiO 2 The "disordered" region is formed at the/SiC interface, this is achieved by using NO or N 2 And the result of interfacial reoxidation that inevitably occurs during high temperature annealing of O. The disordered interface is characterized by the presence of SiO x And C non-stoichiometric defects, which are a function of channel mobility and threshold voltage (V th ) Has a negative effect on the stability of (c).
According to a solution known to the applicant, to reduce the thermal budget required for the oxidation of SiC, siO deposited by CVD 2 The layer can be used as SiO 2 Gate insulator in MOSFET.
According to the solutions known to the applicant, al has been proposed 2 O 3 Film as gate insulator to regulate V in SiC MOSFETs th Values. High-k insulators (referred to as "high-k" materials) may be used, inter alia, to improve V in the on-state in SiC MOSFETs th Values. However, the integration of high-k dielectrics is subject to the thermal budget that it requires to form contacts in SiC devices>Limit the sensitivity to crystallization phenomena at 800 c). Furthermore, the bandgap of an insulator decreases as its dielectric constant increases; thus, a simple high is selectedk will typically result in SiC with small band offset, resulting in high leakage currents.
In SiC power MOSFETs, ohmic contacts are formed by siliciding a metal to form a silicide. High temperature steps are involved in this process, which may be detrimental in some implementations. For example, dielectrics that are used as hydrogen rich gate dielectrics (deposited by PECVD) cannot be used as an intermediate insulator for the gate terminals because of the inherent instability of the temperature used by the layer during the process of forming the silicide. In addition, implementations employing high-k dielectrics also face the problem of too high a process temperature. This limitation is due to degradation of the dielectric properties of the materials (in other words, once they are deposited on the wafer, subsequent process steps cannot use temperatures higher than the properties of the high-k materials used or their withstand capability).
It is therefore desirable to define a process for fabricating ohmic contacts that allows for the above-mentioned problems, particularly with respect to the need to optimize the thermal budget as a function of the gate dielectric used.
Disclosure of Invention
In accordance with the present disclosure, a method of fabricating an electronic device is provided that includes forming a first implant region in a semiconductor body of silicon carbide, the first implant region facing a first side of the semiconductor body and extending into the semiconductor body. The method further includes forming a reactive layer of a metallic material at the first implantation region in contact with the semiconductor body; forming an ohmic contact at the first implantation region by performing a heat treatment to allow a reaction between the metal material at the first implantation region and the material of the semiconductor body to form a silicide of the metal material; one or more additional electrical structures of the electronic device are formed, the electrical structures comprising one or more materials that may be damaged by the heat treatment, wherein the step of forming ohmic contacts is performed prior to the step of forming the one or more additional electrical structures of the electronic device.
Drawings
For a better understanding of the present disclosure, preferred embodiments of the present disclosure will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:
fig. 1 illustrates, in a lateral cross-sectional view, a MOSFET device in accordance with an aspect of the present disclosure; and
fig. 2A-2F illustrate a lateral cross-sectional view of a portion of an electronic device, according to a manufacturing method of the present disclosure; and
fig. 3A-3B illustrate steps of a method of manufacture according to an alternative embodiment of the present disclosure.
Detailed Description
As set forth below, the present disclosure provides a step of forming an ohmic contact prior to forming a gate terminal, optimizing the distribution of thermal budget within the process flow and allowing the use of materials that may be incompatible with high process temperatures (particularly materials for gate dielectrics), particularly materials that are incompatible with temperatures used to form ohmic contacts for source and/or body wells.
The present disclosure also provides for the formation of ohmic contacts based on metal silicides (e.g., ti) formed at high temperatures, which are covered with a high melting point metal layer (e.g., W). These are layers that do not melt at the processing temperature. They are coatings that remain solid during the formation of the contact, maintaining the structural morphology.
Fig. 1 illustrates a transistor 20 (particularly a vertical channel MOSFET, even more particularly a power MOSFET) in accordance with one aspect of the present disclosure in a cross-sectional view of a cartesian (triaxial) frame of reference of X, Y, Z axes. The transistor 20 includes: a gate terminal G (forming a control terminal) which in use is coupleable to a bias voltage V GS Is a generator of (2); a first conductive terminal S comprising a source region 26 (N-type implanted region) and a source metallization layer 59 (e.g., nickel, which forms an ohmic electrical contact with the source region 26); and a second conductive terminal D or drain region D (including drain metallization 27, such as nickel, which forms an ohmic electrical contact). In use, a conductive channel of majority carriers (electrons here) is established between the source region 26 and the drain region 27 by appropriate biasing.
In more detail, transistor 20 includes a semiconductor body 48, in particular of SiC, having a direction along the Z-axis relative to one anotherThe opposing first face 48a and second face 48b. In particular, in the present embodiment, the term "semiconductor body" means a structural element or a solid body that may comprise one or more epitaxial layers grown on a base substrate. Specifically, fig. 1 illustrates a semiconductor body 48 including a base substrate 36, the base substrate 36 having an epitaxially grown structural layer 38 extending thereon that serves as a drift layer. The substrate 36 has a first conductivity (here N-type) and is doped, for example, to between 1.10 18 cm -3 And 5.10 19 cm -3 Between them. The structural layer 38 has a first conductivity (here N-type) and has a lower doping than the substrate 36, for example between 1.10 14 cm -3 And 5.10 16 cm -3 Between them.
According to one aspect of the present disclosure, the polytype of the semiconductor body 48 is a cubic polytype of silicon carbide or 3C-SiC. Alternatively, and in accordance with another aspect of the present disclosure, the polytype of semiconductor body 48 is 4H-SiC. However, the present disclosure also finds application to additional and different silicon carbide polytypes.
The gate terminal G extends on the first face 48a of the semiconductor body 48; body region 45 has a second conductivity (here, a P-type implanted region) opposite the first conductivity, extending into semiconductor body 48 (more specifically, into structural layer 38) at first face 48a (facing first face 48 a); the source region 26 has a first conductivity and extends into the body region 45 at the first surface 48a (facing the first surface 48 a); and the drain metallization 27 extends at the second face 48b of the semiconductor body 48. Transistor 20 is of a vertical conductivity type (i.e., the conductive channel extends along the main direction (which is along the Z-axis)).
The gate terminal G includes a gate metallization 53 and a gate dielectric 52. Gate metallization 53 extends over gate dielectric 52.
The gate dielectric 52 may be any material suitable for the purpose, such as, for example, an oxide (e.g., siO 2 ) Or a compound, multilayer or alloy comprising aluminum (e.g. Al 2 O 3 AlN, alON). The gate dielectric 52 may also be formed of multiple sublayers forming a stack or multiple layersIncluding the foregoing materials, comprising: al (Al) 2 O 3 、AlN、AlON、AlN/SiN、Al 2 O 3 /HfO 2 、SiO 2 /Al 2 O 3 /SiO 2 、SiO 2 /HfO 2 /Al 2 O 3 。
Other materials that may be used to form gate dielectric 52 include NiO, ceO 2 、HfO 2 、SiN、SiO 2 /HfO 2 /SiO 2 。
The insulating layer 52 has a thickness measured along the Z-axis of between 10nm and 100 nm.
An insulating or dielectric layer 56 extends over the gate terminal G, and in particular silicon dioxide (SiO 2 ) Or an insulating or dielectric layer of silicon nitride (SiN) having a thickness measured along the Z-axis of between 0.5 μm and 1.5 μm. Further, a source terminal 58, particularly a source terminal of a metallic material (e.g., aluminum), having a thickness of between 0.5 μm and 2 μm measured along the Z-axis extends near the insulating layer 56.
The source terminal 58 extends until it contacts the source region 26 through an ohmic contact region 59 of metal silicide, such as silicide of Ni, ti, co, pt.
A metal layer 27 of, for example, ti/Ni/Au, forming the gate terminal D extends on the second face 48b of the semiconductor body 48. An interface layer (not shown) allowing ohmic contact, such as an interface layer of nickel silicide, may be present between the semiconductor body 48 and the metal layer 27.
Referring to gate dielectric 52, in one embodiment, it is formed from a stack designed in such a way as to have high density of electron traps, thereby inducing (increasing) negative charge density within the gate dielectric during use. In particular, the stack is an insulating multilayer having at least an energy level close to (e.g., between 0eV and 2 eV) the energy of the conduction band of the semiconductor material (e.g., siC) of the body 48.
In particular, the stack comprises: a first insulating layer, in particular silicon oxide (SiO 2 ) Has a thickness along Z of between 0.5nm and 5 nm; a second insulating layer, in particular hafnium oxide (HfO 2 ) Has a thickness along Z of between 0.5nm and 5 nm; a third insulating layer, in particular an alloy comprising aluminium (e.g. Al 2 O 3 AlN, alON) has a thickness along Z of between 10nm and 100 nm. In one embodiment, the third insulating layer is made of Al 2 O 3 And HfO 2 Is formed of a plurality of (e.g., two) sublayers.
The above may be modified, and in particular, the first insulating layer may be an insulating layer of SiN, alN instead; the second insulating layer may alternatively be HfSiO x 、ZrO 2 、ZrSiO x Is a dielectric layer; the third insulating layer may alternatively be AlSiO x 、HfSiO x Is provided.
Referring now to fig. 2A-2F, the steps of fabricating the MOSFET device 20 are illustrated.
Fig. 2A-2F illustrate a portion of a device (e.g., a MOSFET of the type illustrated in fig. 1) limited to only the source and body regions where it is desired to form respective ohmic contacts 59, 61. The teachings of fig. 2A-2F are generally applicable to the formation of any ohmic contact in MOSFET device 20 and, more generally, to the formation of any ohmic contact in different types of devices, such as VMOS ("vertical channel MOS"), DMOS ("diffused MOS"), CMOS ("complementary MOS"), FET, trench FET.
In the context of fig. 2A to 2F, the same reference numerals as in fig. 1 will be used to illustrate common elements for simplicity of description and to improve clarity, and thus no loss of generality is achieved.
Fig. 2A includes steps of forming a semiconductor body 48, which are known per se and therefore not described in detail, including providing a substrate 36 and forming an epitaxial layer 38 (by epitaxy) on the substrate 36.
Then, fig. 2B performs implantation of dopant species to form implantation regions 45 (body well) and 26 (source region). In this embodiment, p+ implant regions 55 are also formed within the respective body regions 45 and are in direct electrical contact with the respective body regions 45. Source region 26 extends laterally to P + implant region 55. The P + implant region 55 has the same dopant type (P-type here) as the body region 45 and a greater dopant concentration than the body region 45. The p+ implant region 55 has a function of allowing ohmic contact with the body region 45.
An annealing step (e.g., at an elevated temperature of about 1400 c-2000 c) is then performed to activate the dopants of body 45 and source 26 implanted regions.
Then, the method continues with fig. 2C, where source ohmic contacts 59 and body ohmic contacts 61 are formed.
This step includes forming a deposition mask 51, such as a deposition mask 51 of silicon oxide, which is patterned such that the surface regions 48a' of the semiconductor body 48 where ohmic contacts 59, 61 are to be formed are exposed. In the non-limiting example shown in the figures, ohmic contacts are formed at the source region 26 (left side of the figure) and the p+ implant region 55 (right side of the figure).
A metal layer 57 (typically Ni, ti or a combination of Ni/Ti) is then deposited over the mask 51 and at the surface areas 48a' exposed through the mask 51. This step is followed by a suitable high temperature anneal (rapid thermal treatment, at a time interval of 1 minute to 120 minutes, between 800 ℃ and 1150 ℃, more particularly between 900 ℃ and 1150 ℃). This allows ohmic contacts 59, 61 (e.g., ni in the case where layer 57 is Ni) to be formed by a chemical reaction between the deposited metal and silicon present in semiconductor body 48 (in this embodiment SiC) 2 Si). In fact, the deposited metal reacts where it contacts the surface material of the semiconductor body 48, forming an ohmic contact (for example Ni in the case where the metal of layer 57 is Ni 2 Si)。
Subsequently, fig. 2D, the metal of layer 57 extending over mask 51 is removed, and mask 51 is also removed.
Then, fig. 2E, one or more steps for forming gate dielectric 52 are performed.
Forming gate dielectric 52 may include deposition and photolithographic definition, such as SiO 2 Or SiN, or form a multilayer of the type described above.
In particular, in a possible embodiment, in halfThe conductor body 48 is formed thereon to include SiO 2 /HfO 2 /Al 2 O 3 Is a multi-layer or stack of layers.
Variations of the above are possible, in particular the first insulating layer may alternatively be Al 2 O 3 An insulating layer of SiN or AlN; the second insulating layer may alternatively be HfSiO x 、ZrO 2 Or ZrSiO x Is a dielectric layer; the first sub-layer of the third insulating layer may alternatively be AlSiO x The insulating layer and/or the second sub-layer of (C) may alternatively be HfSiO x An insulating layer.
The first insulating layer has a reduced thickness to allow tunneling of electrons from the semiconductor body 48 and has a band gap that is greater than the band gap of the second insulating layer. Thus, the first insulating layer has such a thickness: so that electrons confined in the potential well and limited in number by the state allowed by the potential well can tunnel through the first insulating layer to produce a positive V of the MOSFET 20 th 。
The layer acting as a charge trap is a second insulating layer having a reduced band gap, which forms a quantum well between the first insulating layer and the third insulating layer. In one embodiment, hafnium oxide represents a potential well of electrons bounded on one side by a first insulating layer and on the other side by a third insulating layer.
The third insulating layer is configured to have a band gap greater than that of the second insulating layer. Since the third insulating layer includes the two (or more) sublayers previously described, a high bandgap (e.g., al 2 O 3 Can be between 7eV and 9 eV) and high dielectric constant (e.g., hfO 2 The dielectric constant of about 20).
In one embodiment:
the first insulating layer has a first band gap value and a first thickness;
the second insulating layer has a second band gap value lower than the first band gap value and a second thickness greater than the first thickness; and
the third insulating layer has a third bandgap value between the first bandgap value and the second bandgap value and a third thickness greater than the second thickness.
In one embodiment:
the first insulating layer has a thickness between 0.5nm and 1nm (inclusive) and a band gap between 7eV and 9eV (inclusive); the first insulating layer is SiO 2 Or one of the materials indicated above for this layer;
the second insulating layer has a thickness between 1.5nm and 2.5nm (inclusive) and a band gap between 4eV and 6eV (inclusive); the second insulating layer is HfO 2 Or one of the materials indicated above for this layer; and
the third insulating layer has a thickness between 10nm and 100nm (inclusive) and a band gap between 7eV and 8.5eV (inclusive); the third insulating layer is a multilayer comprising a first sub-layer and a second sub-layer, or is a continuous plurality of layers alternating with each other.
According to the stack of the present disclosure, the advantage of the high band gap of the third insulating layer and the advantage of the high dielectric constant of the second insulating layer are allowed to be combined with respect to a single layer or a set of sub-layers of high k materials other than those described herein.
When the material forming the stack is amorphous (and non-crystalline), the stack is stable and has the properties described above. Another additional positive effect is that the proposed structure has a higher capacitance relative to the gate dielectric of single silicon monoxide, allowing a higher RC constant, thus limiting ringing caused by the fast switching of the MOSFET device 20.
With reference to the above stacked manufacturing process, the first silicon oxide insulating layer is formed by thermal oxidation or oxidation of a solution (H 2 O 2 ) Bath or Atomic Layer Deposition (ALD) techniques; then, a second insulating layer HfO is formed on the first insulating layer by ALD technique 2 The method comprises the steps of carrying out a first treatment on the surface of the Then, a third insulating layer Al is formed on the second insulating layer by ALD technique 2 O 3 。
In one embodiment, the second insulating layer HfO may be deposited by thermal treatment or plasma using the parameters according to the following table 2 ：
In one embodiment, the third insulating layer Al may be deposited by a thermal treatment or plasma using parameters according to the following table 2 O 3 ：
As an alternative to deposition by ALD, one or all of the above-described insulating layers may be deposited by CVD techniques or reactive ion sputtering.
The post-deposition annealing step is then performed in an oxygen-containing atmosphere or in an inert atmosphere (which has argon and/or nitrogen), in particular at a temperature equal to or lower than 1000 ℃.
Finally, in fig. 2F, the remaining steps are performed to complete the formation of the MOSFET device, including forming the conductive layer 53 (metallization or polysilicon) of the gate terminal in a manner known per se.
To electrically contact the source ohmic contact 59 and the body ohmic contact 61, a through opening is formed through the layers 52 and 53 at the source ohmic contact 59 and the body ohmic contact 61.
The formation of the MOSFET device is then completed by forming insulating layer 56 and depositing metallization layer 58, metallization layer 58 electrically contacting source ohmic contact 59 and body ohmic contact 61 through the through openings formed through layers 52 and 53.
Referring to fig. 3A, according to an alternative embodiment of fig. 2E and 2F, after the steps that have been described with reference to fig. 2A to 2D are completed, a first protective layer 80 and a second protective layer 81 are formed at and above the source ohmic contacts 59 and the body ohmic contacts 61. Layer 80 is silicon oxide (SiO) 2 ) Also referred to as "pad oxide", while layer 81 extending over layer 80 is silicon nitride (SiN, si) deposited by LPCVD techniques 2 N 3 ). The protective layers 80, 81 extend limitedly on the side 48a to the surface portions where the ohmic contacts 59, 61 are present to completely cover them and no gate terminal G will be formed thereinThe region extends. The function of the first protective layer 80 and the second protective layer 81 is to "seal" the silicide (cover it) from contamination outside the device during successive manufacturing steps.
The method then continues with forming gate dielectric 52 in a manner similar to that described with reference to fig. 2E. In this case, the gate dielectric 52 also extends over the first protective layer 80 and the second protective layer 81.
Finally, the remaining steps are performed to complete the formation of the MOSFET device, including the formation of the conductive layer 53 (metallization or polysilicon) and the insulating layer 56 of the gate terminal.
Referring to fig. 3B, in order to electrically contact the source ohmic contact 59 and the body ohmic contact 61, through openings through the layers 52, 53, 80, and 81 are formed at the source ohmic contact 59 and the body ohmic contact 61, thereby exposing them. The formation of the MOSFET device is then completed by forming insulating layer 56 and depositing metallization layer 58, metallization layer 58 electrically contacting source ohmic contact 59 and body ohmic contact 61 through the through openings formed through layers 52, 53, 80, 81.
The advantages that they provide are apparent from a survey of the features of the present disclosure made in accordance with the present disclosure.
In particular, the present disclosure allows for the use of materials (high-K materials, H-rich materials, etc.) that are subject to a thermal budget for the formation of silicide because the formation of silicide ohmic contacts occurs in an initial fabrication step of the device prior to the formation of gate terminals or other structures.
The proposed solution is in the case of gate dielectrics using high-K materials that may be unstable at high temperatures and in the case of conventional gate dielectrics (e.g. SiO 2 ) Is feasible in all cases.
Finally, it is clear that modifications and variations may be made to what is described and illustrated herein without departing from the scope of the present disclosure as defined in the appended claims.
For example, the present disclosure may be limited to forming a single source ohmic contact 59 (without ohmic contact 61).
Further, the present disclosure may be limited to forming a single drain ohmic contact (in the absence of the source ohmic contact 59 and the body ohmic contact 61).
Alternatively, the present disclosure may include forming any combination of two or more of the following: a source ohmic contact 59 is formed, a drain ohmic contact is formed, and a body ohmic contact 61 is formed.
Furthermore, the present disclosure may be applied to devices based on SiC polytypes other than 4H-SiC, such as 3C-SiC or 6H-SiC devices.
Further, the present disclosure may be applied to devices having substrates (semiconductor bodies) of materials other than SiC, such as GaN and AlGaN/GaN (e.g., used in HEMT fabrication).
The present disclosure also applies to horizontal channel devices.
A method of manufacturing an electronic device (20) may be summarized as including the steps of: forming a first implantation region (26; 55) in the semiconductor body (48) of silicon carbide, the first implantation region (26; 55) facing a first side (48 a;48 b) of the semiconductor body (48) extending into the semiconductor body (48); forming a reactive layer (57) of metallic material at the first implantation region (26; 55) in contact with the semiconductor body (48); forming an ohmic contact (59; 61) at the first implantation region (26; 55) by performing a heat treatment to allow a reaction between the metallic material at the first implantation region (26; 55) and the material of the semiconductor body (48) to form a silicide of the metallic material; and forming one or more further electrical structures (G, 53, 56) of the electronic device (20), said further electrical structures comprising one or more materials that may be damaged due to said heat treatment, characterized in that the step of forming ohmic contacts is performed before the step of forming the one or more further electrical structures (G, 53, 56) of the electronic device (20).
The step of forming the one or more further electrical structures (G, 53, 56) may comprise forming an electrical control terminal (G) of the electronic device (20).
The electrical control terminal (G) of the electronic device (20) may be a gate terminal and may comprise a gate dielectric (52) and a gate conductive layer (53) on the gate dielectric (52), the gate dielectric (52) comprising said material which may be damaged due to the heat treatment.
The gate dielectric material (52) may be a high-k or hydrogen-rich material.
The heat treatment for forming ohmic contacts may be performed at a temperature between 800 ℃ and 1150 ℃.
The method may further comprise the step of forming a second implant region (45) prior to the step of forming the first implant region (26, 45), the first implant region (26, 45) being entirely contained within the second implant region (45).
The second implant region (45) may be a body region of the electronic device (20) and may have a first conductivity (P) and a first dopant concentration, and the first implant region (26; 55) may be one of: a source region (26) having a second conductivity (N) opposite to the first conductivity (P); a body contact region (55) having a first conductivity (P) and a second dopant concentration greater than the first dopant concentration.
The control terminal (G) may extend laterally to the first injection region (26; 55).
The method may further comprise the step of forming a conductive terminal (S; D) in electrical contact with the ohmic contact (59; 61).
Forming one or more additional electrical structures (52, 56) of the electronic device (20) may include depositing one or more dielectric or insulating materials, particularly by ALD techniques.
The method may further comprise the step of forming a multilayer for completely covering the ohmic contact (59; 61) at the ohmic contact (59; 61) and above the ohmic contact (59; 61), the multilayer comprising a first protective layer (80) of silicon oxide and a second protective layer (81) of silicon nitride, said step of forming one or more further electrical structures (52, 53, 56) of the electronic device (20) being performed after forming the first and second protective layers (80, 81).
The method may further comprise the step of forming a mask (51) on the first side (48 b) of the semiconductor body (48), the mask (51) having a through opening at least one surface portion (48 a ') of the first implantation region (26; 55), a reaction layer (57) being formed over the mask (51) and in contact with the surface portion (48 a'); the method may further include the step of removing the mask (51) and the metal material of the unreacted reaction layer (57) prior to the step of forming the ohmic contact.
The electronic device may be a MOSFET.
The semiconductor body (48) may be polytype 4H of silicon carbide or 4H-SiC.
The various embodiments described above may be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims (20)

1. A method of manufacturing an electronic device, comprising:
forming a first implant region in a semiconductor body of silicon carbide, the first implant region facing a first side of the semiconductor body extending into the semiconductor body;
forming a reactive layer of a metallic material at the first implantation region in contact with the semiconductor body;
forming an ohmic contact at the first implant region by performing a heat treatment to allow a reaction between the metal material at the first implant region and the material of the semiconductor body to form a silicide of the metal material; and
forming one or more electrical structures of the electronic device, the electrical structures comprising one or more materials that may be damaged by the heat treatment,
wherein forming the ohmic contact is performed prior to forming the one or more electrical structures of the electronic device.
2. The method of claim 1, wherein the step of forming the one or more electrical structures comprises forming electrical control terminals of the electronic device.
3. The method of claim 2, wherein the electrical control terminal of the electronic device is a gate terminal and comprises a gate dielectric and a gate conductive layer on the gate dielectric, the gate dielectric comprising the material that would be damaged by the heat treatment.
4. The method of claim 3, wherein the gate dielectric material is a high-k or hydrogen-rich material.
5. The method of claim 1, wherein the heat treatment for forming the ohmic contact is performed at a temperature between 800 ℃ and 1150 ℃.
6. The method of claim 1, further comprising: a step of forming a second implant region prior to the step of forming the first implant region, the first implant region being entirely contained within the second implant region.
7. The method of claim 6, wherein the second implant region is a body region of the electronic device and has a first conductivity and a first dopant concentration, the first implant region being one of:
a source region having a second conductivity opposite the first conductivity; and
a body contact region having the first conductivity and a second dopant concentration greater than the first dopant concentration.
8. The method of claim 7, wherein the control terminal extends laterally to the first injection region.
9. The method of claim 1, further comprising: and forming a conductive terminal in electrical contact with the ohmic contact.
10. The method according to claim 1, wherein forming the one or more further electrical structures of the electronic device comprises depositing one or more dielectric or insulating materials, in particular by ALD technique.
11. The method of claim 1, further comprising: a step of forming a multilayer for completely covering the ohmic contact at and above the ohmic contact, the multilayer including a first protective layer of silicon oxide and a second protective layer of silicon nitride,
the step of forming one or more further electrical structures of the electronic device is performed after forming the first protective layer and the second protective layer.
12. The method of claim 1, further comprising: a step of forming a mask on the first side of the semiconductor body, the mask having a through opening at least one surface portion of the first implantation region,
the reaction layer is formed over the mask and in contact with the surface portion;
the method further includes the step of removing the metal material of the mask and unreacted reaction layer prior to the step of forming the ohmic contact.
13. The method of claim 1, wherein the electronic device is a MOSFET.
14. The method of claim 1, wherein the semiconductor body is 4H polytype of silicon carbide or 4H-SiC.
15. A method, comprising:
a first source region is formed in a first side of the semiconductor body,
forming a metal layer coupled to the first source region and the first side of the semiconductor body;
forming a first ohmic contact in the first source region;
forming a gate dielectric layer on the first side of the semiconductor body, the gate dielectric layer being coupled to the first ohmic contact;
forming a conductive layer on the gate dielectric layer;
forming a first opening through the gate dielectric layer and the conductive layer, the first opening exposing the first ohmic contact;
forming an insulating layer covering the gate dielectric layer and the conductive layer; and
a metallization layer is formed on the insulating layer, the metallization layer being coupled to the first ohmic contact.
16. The method of claim 15, wherein forming the gate dielectric layer comprises photolithography.
17. The method of claim 15, wherein forming a first ohmic contact comprises a high temperature thermal annealing process wherein a reaction occurs between the metal layer and the semiconductor body.
18. A method, comprising:
forming a first body well in a first side of a semiconductor body, the first body well having a first side coplanar with the first side of the semiconductor body;
forming a first source region in the first body well, the first source region having a first side coplanar with the first side of the semiconductor body;
forming a first implant region in the first source region, the first implant region having a first side coplanar with the first side of the semiconductor body;
forming a deposition mask layer on the first side of the semiconductor body, the deposition mask layer having a first opening exposing the first source region;
forming a metal layer on the deposition mask layer, the metal layer being coupled to the first source region through the first opening in the deposition mask layer; and
a first ohmic contact is formed in the first source region.
19. The method of claim 18, comprising: the metal layer and the deposition mask layer are removed after the first ohmic contact is formed.
20. The method of claim 18, wherein the first body well has a first doping type and a first doping concentration, and the first implant region has the first doping type and a second doping concentration that is greater than the first doping concentration.
CN202311081391.XA 2022-08-29 2023-08-25 Methods of fabricating ohmic contacts for electronic devices with thermal budget optimization Pending CN117637457A (en)

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IT102022000017733 2022-08-29
US18/363,349 US20240079237A1 (en) 2022-08-29 2023-08-01 Method of manufacturing ohmic contacts of an electronic device, with thermal budget optimization
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