CN117594658B - A trench field effect transistor and a method for manufacturing the same - Google Patents

Abstract

The invention discloses a groove type field effect transistor and a preparation method thereof, which belong to the technical field of semiconductors, and the groove type field effect transistor comprises: a substrate layer; an epitaxial layer; a first body region; a second body region; a first trench; a second trench; a first source region; and a second source region. According to the invention, the depth of the first body region and the depth of the second body region are preset, so that the depth of the second body region is smaller than that of the first body region, and the second body region with the shallower depth compared with that of the first body region is obtained, so that the length of the body region is reduced, and the threshold voltage for starting the diode is further reduced, and the body diode is started at a lower threshold voltage, thereby reducing the reverse freewheeling power consumption.

Description

A trench field effect transistor and a method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a trench field effect transistor and a preparation method thereof.

Background Art

Trench field effect transistors play an indispensable role in the field of semiconductor technology and are crucial to the development of power semiconductor devices. However, due to the high complexity of the field of semiconductor technology, the parasitic diode of the traditional trench MOS is a PN junction diode composed of its P-type body base region and N-type epitaxial layer, and its turn-on voltage is around 1V. When the reverse current flows, the current passes through the body diode, resulting in a higher turn-on voltage and greater power consumption.

Therefore, how to turn on the body diode with a lower turn-on voltage to reduce the reverse freewheeling power consumption becomes an urgent problem to be solved.

Summary of the invention

Based on this, an embodiment of the present application provides a trench field effect transistor and a method for preparing the same, in order to solve the problem that when the parasitic diode of the current traditional trench MOS is reversely freewheeling, the current passes through the body diode, resulting in a high turn-on voltage and high power consumption.

In a first aspect, an embodiment of the present application provides a trench field effect transistor and a method for manufacturing the same, including:

a substrate layer of a first conductivity type;

An epitaxial layer of a first conductivity type, the epitaxial layer being located on the substrate layer;

a first body region of a second conductivity type, the first body region being located on the epitaxial layer;

A second body region of a second conductivity type, the second body region being located on the epitaxial layer, the first body region and the second body region being adjacent to each other, and a depth of the second body region being less than a depth of the first body region;

a first trench, the first trench penetrating the first body region along a depth direction and extending to the inside of the epitaxial layer, a first gate structure being disposed in the first trench;

a second trench, the second trench penetrating the second body region along a depth direction and extending into the interior of the epitaxial layer, wherein a second gate structure is disposed in the second trench;

a first source region of a first conductivity type, the first source region being located on the first body region;

A second source region of the first conductivity type is located on the second body region.

Optionally, the ion doping concentration of the second body region is less than the ion doping concentration of the first body region.

Optionally, forming the first gate structure includes: forming a first dielectric layer of the first gate structure, and a first gate located on the first dielectric layer;

Forming the second gate structure includes: forming a second dielectric layer of the second gate structure, and a second gate located on the second dielectric layer, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer.

Optionally, forming the second dielectric layer of the second gate structure includes: forming a bottom dielectric layer located above the bottom of the second trench, an upper wall dielectric layer located on the side wall of the second trench, and a lower wall dielectric layer located on the side wall of the second trench, the upper wall dielectric layer is located above the lower wall dielectric layer, and the thickness of the upper wall dielectric layer is less than the thickness of the lower wall dielectric layer.

Optionally, a first contact hole of a preset shape is provided on the second gate structure, a second contact hole is provided between the first source region and the second source region, and the first contact hole and the second contact hole are filled with metal for connecting the second gate structure and the first source region and the second source region through the first contact hole, the metal, and the second contact hole.

Optionally, the first contact hole and the second contact hole have a depth range of 0.3um-0.5um, and a width range of 0.2um-0.4um.

Optionally, the depth range of the first body region is 1um-2um, and the depth range of the second body region is 0.5um-1um.

Optionally, an interlayer dielectric layer is located on the first source region and the second source region.

Optionally, a metal layer is located on the interlayer dielectric layer.

In a second aspect, the present invention provides a trench field effect transistor and a method for manufacturing the same, including:

providing a substrate layer of a first conductivity type;

forming an epitaxial layer of a first conductivity type on the substrate layer;

Forming a first trench extending into the epitaxial layer along a depth direction, and forming a first gate structure in the first trench; forming a second trench extending into the epitaxial layer along a depth direction, and forming a second gate structure in the second trench;

forming a first body region of a second conductivity type on the epitaxial layer, so that the first trench penetrates the first body region, forming a second body region of a second conductivity type on the epitaxial layer, so that the second trench penetrates the second body region, and the depth of the second body region is less than the depth of the first body region;

A first source region of a first conductivity type is formed on the first body region, and a second source region of the first conductivity type is formed on the second body region.

Optionally, forming a first gate structure in the first trench includes:

Growing a first dielectric layer of a first preset thickness on the inner wall of the first trench, etching the first dielectric layer, and retaining the first dielectric layer at the bottom of the first trench;

A first dielectric layer of a second preset thickness is grown on the sidewall of the first trench, a first gate is deposited on the first dielectric layer, and a portion of the first gate is etched to obtain a first gate structure in the first trench.

Optionally, forming a second gate structure in the second trench includes:

Coating a photoresist on the first gate structure in the first trench, etching the upper part of the gate and the upper part of the dielectric layer in the second trench, retaining the lower part of the gate, and using the lower part of the dielectric layer as the bottom dielectric layer and the lower wall dielectric layer of the second dielectric layer;

Etching the lower part of the gate to remove the photoresist and grow an upper wall dielectric layer, wherein the upper wall dielectric layer is located above the lower wall dielectric layer, and a second dielectric layer is formed by the bottom dielectric layer, the lower dielectric layer and the upper wall dielectric layer;

A second gate is deposited on the second dielectric layer, and a portion of the second gate is etched to obtain a second gate structure in the second trench.

The beneficial effect of the embodiments of the present application compared with the prior art is as follows: by presetting the depths of the first body region and the second body region, the depth of the second body region is made smaller than the depth of the first body region, thereby obtaining a second body region with a shallower body region depth than the first body region, thereby reducing the length of the body region, and further reducing the threshold voltage for turning on the diode, thereby turning on the body diode with a lower threshold voltage, thereby reducing the reverse freewheeling power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

FIG1 is a schematic diagram of a trench field effect transistor structure provided by an embodiment of the present invention;

FIG2 is a schematic diagram of the corresponding structures obtained in various preparation processes of a trench field effect transistor provided by an embodiment of the present invention;

3 is a schematic diagram of the corresponding structures obtained in various preparation processes of a trench field effect transistor provided by an embodiment of the present invention;

4 to 14 are flow charts of a method for preparing a trench field effect transistor according to an embodiment of the present invention;

15 is a flow chart of a method for preparing a trench field effect transistor according to an embodiment of the present invention;

16 is a flow chart of a method for preparing a trench field effect transistor according to an embodiment of the present invention;

17 to 27 are flow charts of a method for preparing a trench field effect transistor according to another embodiment of the present invention;

Description of labels:

101. substrate layer; 102. epitaxial layer; 103. first body region; 104. second body region; 105. first trench; 106. first gate structure; 107. second trench; 108. second gate structure; 109. first source region; 110. second source region; 111. first gate; 112. first dielectric layer; 112-1. first bottom dielectric layer; 113. second gate; 114. second dielectric layer; 114-1 bottom dielectric layer; 114-2 lower wall dielectric layer; 114-3 upper wall dielectric layer; 115. interlayer dielectric layer; 116. metal layer; 117. first contact hole; 118. second contact hole; 119. hard mask dielectric layer; 120. photoresist.

DETAILED DESCRIPTION

In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and/or combinations thereof.

It should also be understood that the term “and/or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

It should be understood that the size of the serial numbers of the steps in the following embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In order to illustrate the technical solution of the present application, a specific embodiment is provided below for illustration.

In one embodiment, as shown in FIG. 1 , a trench field effect transistor is provided, comprising:

A substrate layer 101 of a first conductivity type;

An epitaxial layer 102 of a first conductivity type, wherein the epitaxial layer 102 is located on the substrate layer 101;

A first body region 103 of a second conductivity type, wherein the first body region 103 is located on the epitaxial layer 102;

A second body region 104 of a second conductivity type, the second body region 104 is located on the epitaxial layer 102, the first body region 103 and the second body region 104 are adjacent, and the depth of the second body region 104 is less than the depth of the first body region 103;

A first trench 105, wherein the first trench 105 penetrates the first body region 103 along a depth direction and extends to the inside of the epitaxial layer 102, and a first gate structure 106 is disposed in the first trench 105;

A second trench 107, wherein the second trench 107 penetrates the second body region 104 along a depth direction and extends to the inside of the epitaxial layer 102, and a second gate structure 108 is disposed in the second trench 107;

A first source region 109 of a first conductivity type, wherein the first source region 109 is located on the first body region 103;

A second source region 110 of the first conductivity type is located on the second body region 104 .

In the above-mentioned trench field effect transistor, the substrate layer 101 is of the first conductivity type, which can be N-type or P-type. The ions doped in the substrate layer 101 are N-type heavily doped ions, which can be aluminum ions, boron ions, indium (In), gallium (Ga), etc.

In the above trench field effect transistor, the epitaxial layer 102 is of the first conductivity type, and the ions doped in the epitaxial layer 102 are N-type lightly doped ions, which may be nitrogen ions, phosphorus ions, and the like.

In the above-mentioned trench field effect transistor, the first body region 103 is P-type, and the first body region 103 usually has a conductivity type opposite to that of the epitaxial layer 102. For example, in the N-type body region, doping materials such as phosphorus (P) are usually added, and in the P-type body region, doping materials such as boron (B) are usually added.

In the above trench field effect transistor, the second body region 104 is of P type. The second body region 104 is usually formed by doping techniques such as ion implantation and diffusion. The second body region 104 usually has a conductivity type opposite to that of the epitaxial layer 102 .

In the above trench field effect transistor, the first trench 105 is etched according to a preset shape, passes through the first body region 103 of the semiconductor device, and extends to the inside of the epitaxial layer 102. For example, the trench is usually created by a manufacturing process such as photolithography or etching. Photolithography is used to define the shape of the trench, and etching is used to carve the trench into the semiconductor material along a preset direction. The depth and shape of the trench depend on the design of the device and the required function.

In the above-mentioned trench field effect transistor, the second trench 107 is etched according to a preset shape, passes through the second body region 104 of the semiconductor device, and extends to the inside of the epitaxial layer 102. For example, trenches are usually used to isolate different parts of the device and define the boundary or shape of the electronic component. In semiconductor devices, trenches are generally used to separate different electronic components to ensure that the electronic components do not interfere with each other.

In the above trench field effect transistor, the first source region 109 is of N type, and its conductivity type is the same as that of the substrate layer 101 and the epitaxial layer 102 , which are both of the first conductivity type.

In the above-mentioned trench field effect transistor, the second source region 110 is N-type. For example, the source region is usually N-type or P-type semiconductor material. The formation of the source region usually includes ion implantation or other doping processes again. In actual application, the setting of the doping type can be adjusted according to actual conditions.

A trench field effect transistor in an embodiment of the present application obtains a second body region 104 having a shallower body region depth than the first body region 103 by presetting the depth of the first body region 103 and the second body region 104. By presetting the length of the body region, the threshold voltage for turning on the diode is reduced, thereby turning on the body diode with a lower threshold voltage, thereby reducing the reverse freewheeling power consumption.

In one embodiment, the ion doping concentration of the second body region 104 is less than the ion doping concentration of the first body region 103 .

As shown in FIG1 , the first body region 103 is a P-type body region, and the ion doping concentration of the first body region 103 is 1×10 ¹⁷ cm ^-3 , and the second body region 104 is a P-type body region, and the doping concentration of the second body region 104 is 5×10 ¹⁶ cm ^-3 . The ion doping concentration of the first body region 103 is greater than that of the second body region 104, that is, the higher the doping concentration, the greater the threshold voltage, and the lower the doping concentration, the smaller the threshold voltage. The specific doping degree can be set according to the usage.

Among them, the ions doped in the body region can be boron ions, etc., and the ion doping concentration refers to the density of a specific type of ions in the semiconductor crystal. In the semiconductor manufacturing process, the conductive properties of the semiconductor material are adjusted by controlling and adjusting the ion doping concentration. Generally, areas with high ion doping concentrations have better conductivity, while areas with low ion doping concentrations may exhibit higher resistance or other properties.

A trench field effect transistor in an embodiment of the present application, on the basis of defining the depths of the first body region 103 and the second body region 104, further defines the ion doping concentrations of the first body region 103 and the second body region 104, so that the ion doping concentration of the second body region 104 is less than the ion doping concentration of the first body region 103, thereby reducing the conduction voltage of the diode of the trench MOS device and reducing the conduction loss of the diode.

In one embodiment, as shown in FIG. 2 , forming the first gate structure 106 includes: forming a first dielectric layer 112 of the first gate structure 106 , and a first gate 111 located on the first dielectric layer 112 ;

Forming the second gate structure 108 includes: forming a second dielectric layer 114 of the second gate structure 108 , and a second gate 113 located on the second dielectric layer 114 , wherein the thickness of the second dielectric layer 114 is smaller than the thickness of the first dielectric layer 112 .

Specifically, the first dielectric layer 112 and the second dielectric layer 114 are grown by a chemical vapor deposition process. The first dielectric layer 112 and the second dielectric layer 114 can be silicon dioxide, or can be polysilicon, metal, or other oxide materials. The thickness of the second dielectric layer 114 is less than the thickness of the first dielectric layer 112. For example, the thickness range of the first dielectric layer 112 is 0.2um-2um, the thickness range of the lower wall dielectric layer 114-2 in the second dielectric layer 114 is 0.2um-2um, and the thickness range of the upper wall dielectric layer 114-3 in the second dielectric layer 114 is 0.1um-1um.

A trench field effect transistor according to an embodiment of the present application, on the basis of limiting the depth of the first body region 103 and the second body region 104 and limiting the ion doping concentration of the first body region 103 and the second body region 104, further limits the thickness of the dielectric layer in the first gate structure 106 and the second gate structure 108, further reduces the threshold voltage for turning on the diode, turns on the body diode with a lower threshold voltage, and enhances the effect of reducing reverse freewheeling power consumption.

In one embodiment, as shown in Figure 2, the second dielectric layer 114 forming the second gate structure 108 includes: forming a bottom dielectric layer 114-1 located above the bottom of the second trench 107, an upper wall dielectric layer 114-3 located on the side wall of the second trench 107, and a lower wall dielectric layer 114-2 located on the side wall of the second trench 107, the upper wall dielectric layer 114-3 is located above the lower wall dielectric layer 114-2, and the thickness of the upper wall dielectric layer 114-3 is less than the thickness of the lower wall dielectric layer 114-2.

For example, a bottom dielectric layer 114-1, a lower wall dielectric layer 114-2, and an upper wall dielectric layer 114-3 can be formed by an etching process. For example, the thickness of the bottom dielectric layer 114-1 after etching is in the range of 0.06um-0.3um, the thickness of the lower wall dielectric layer 114-2 after etching is in the range of 0.02um-0.1um, and the thickness of the upper wall dielectric layer 114-3 after etching is in the range of 0.01um-0.05um.

In a trench field effect transistor according to an embodiment of the present application, the second gate structure 108 includes a second dielectric layer 114, and the second dielectric layer 114 is composed of a bottom dielectric layer 114-1, an upper wall dielectric layer 114-3, and a lower wall dielectric layer 114-2. The bottom dielectric layer 114-1 has the function of reducing capacitance and increasing withstand voltage, and the upper wall dielectric layer 114-3 and the lower wall dielectric layer 114-2 reduce the threshold voltage for turning on the diode.

In one embodiment, as shown in FIG. 1 , a first contact hole 117 of a preset shape is provided on the second gate structure 108, a second contact hole 118 is provided between the first source region 109 and the second source region 110, and the first contact hole 117 and the second contact hole 118 are filled with metal 116 for connecting the second gate structure 108 and the first source region 109 and the second source region 110 through the first contact hole 117, the metal 116, and the second contact hole 118.

Specifically, the first contact hole 117 is located on the second gate structure 108, and the second contact hole 118 is located between the first source region 109 and the second source region 110. The metal 116 is generally used as a conductive material. The metal 116 is filled into the first contact hole 117 and the second contact hole 118, and an electrical connection is established through the first contact hole 117, the second contact hole 118, and the metal 116, thereby connecting the second gate structure 108, the first source region 109, and the second source region 110.

A trench field effect transistor in an embodiment of the present application connects a second gate structure 108, a first source region 109, and a second source region 110 by setting a first contact hole 117, a second contact hole 118, and a metal 116, so that when the device in Figure 1 is in reverse freewheeling, the source is at a high potential and the drain is at a low potential, thereby turning on the body diode with a lower threshold voltage to pass current and ensure the normal operation and reliability of the device.

In one embodiment, the first contact hole 117 and the second contact hole 118 have a depth ranging from 0.3um to 0.5um and a width ranging from 0.2um to 0.4um.

As shown in Figure 1, the depth refers to the distance from the hole mouth to the hole bottom, which is used to determine the depth of the hole. The width refers to the span of the hole, which is used to determine the diameter or lateral size of the hole. The contact hole is usually located on the surface of the semiconductor device and is used to establish an electrical connection so as to connect to different parts of the device. The shapes of the first contact hole 117 and the second contact hole 118 can be pre-designed according to the specific situation. The shape of the contact hole can be a regular quadrilateral, or it can be an irregular polygon, a circle, etc.

A trench field effect transistor in an embodiment of the present application establishes electrical connections with a second gate structure 108, a first source region 109, and a second source region 110 through a first contact hole 117 and a second contact hole 118 so as to be connected to different parts of the device, thereby turning on the body diode with a lower threshold voltage, thereby reducing reverse freewheeling power consumption.

In one embodiment, the depth of the first body region 103 is in the range of 1 um-2 um, and the depth of the second body region 104 is in the range of 0.5 um-1 um.

Specifically, the depth range of the first body region 103 is 1um-2um, and the depth range of the second body region 104 is 0.5um-1um. For example, the depth range of the first body region 103 can also be 0.8um-1.8um, 1.2um-2.2um, etc., and the depth range of the second body region 104 can also be 0.2um-0.7um, 0.8um-1.3um.

In a trench field effect transistor of an embodiment of the present application, the deeper the depth of the body region, the higher the threshold voltage. By presetting the depth range of the first body region 103 and the second body region 104, the length of the body region is reduced, thereby reducing the threshold voltage for turning on the diode, thereby turning on the body diode with a lower threshold voltage, thereby reducing reverse freewheeling power consumption.

In one embodiment, the trench field effect transistor as shown in FIG. 1 further includes: an interlayer dielectric layer 115 located on the first source region 109 and the second source region 110 .

Specifically, the material of the interlayer dielectric layer 115 may be silicon dioxide, or silicon nitride or other materials.

A trench field effect transistor according to an embodiment of the present application provides an interlayer dielectric layer 115 between the first source region 109 and the second source region 110 so as to obtain a structure and performance that meet design requirements in subsequent steps.

In one embodiment, the trench field effect transistor as shown in FIG. 1 further includes: a metal layer 116 located on the interlayer dielectric layer 115 .

Specifically, the material of the metal layer 116 may be aluminum, silicon, copper alloy, etc. The metal layer 116 is usually used to lead out electron flow so as to input or output current to the semiconductor device.

In a trench field effect transistor of an embodiment of the present application, the metal layer 116 is usually used for connection, wiring, controlling electronic channels or providing external connections. The metal layer 116 is usually precisely manufactured and arranged to ensure the normal operation and reliability of the device.

In one embodiment, as shown in FIG3 , the method for preparing the trench field effect transistor comprises the following steps:

Step S21, providing a substrate layer 101 of a first conductivity type;

As shown in FIG4 , the substrate layer 101 of the first conductivity type is heavily doped N-type, and the substrate layer 101 may be a semiconductor material such as silicon (Si), silicon carbide (SiC), etc. The substrate layer 101 of the first conductivity type may be an N-type semiconductor material or a P-type semiconductor material. When the substrate layer 101 is an N-type semiconductor material, the epitaxial layer 102 of the first conductivity type formed on the substrate layer 101 is also an N-type semiconductor material.

Step S22, forming an epitaxial layer 102 of a first conductivity type on the substrate layer 101;

As shown in FIG. 4 , the epitaxial layer 102 of the first conductivity type is a lightly doped N-type epitaxial layer 102 , and the epitaxial layer 102 and the substrate layer 101 have the same conductivity type.

Step S23, forming a first trench 105 extending to the inside of the epitaxial layer 102 along the depth direction, and forming a first gate structure 106 in the first trench 105; forming a second trench 107 extending to the inside of the epitaxial layer 102 along the depth direction, and forming a second gate structure 108 in the second trench 107;

As shown in FIG5 , a hard mask dielectric layer 119 is deposited on the epitaxial layer 102. The hard mask dielectric layer 119 may be silicon dioxide, or may be a first silicon oxide, a first silicon nitride, etc. A photoresist 120 is coated on the hard mask dielectric layer 119, and photolithography is performed according to a preset groove pattern. The hard mask dielectric layer 119 is dry-etched to remove the photoresist 120 and the hard mask dielectric layer 119. As shown in FIG6 , a first groove 105 and a second groove 107 are formed.

As shown in FIG7 , a first dielectric layer 112 and a second dielectric layer 114 are grown on the first trench 105 and the second trench 107 by chemical vapor deposition process. The first dielectric layer 112 and the second dielectric layer 114 may be silicon dioxide, or polysilicon, metal, or other oxide materials. The first dielectric layer 112 and the second dielectric layer 114 are etched, as shown in FIG8 , and the first bottom dielectric layer 112-1 and the bottom dielectric layer 114-1 are retained. As shown in FIG9 , the first dielectric layer 112 is grown on the sidewall of the first trench 105, and the second dielectric layer 114 is grown on the sidewall of the second trench 107. The growth speed and thickness can be preset according to specific conditions. As shown in FIG10 , the first gate 111 and the second gate 113 are deposited. The first gate 111 and the second gate 113 may be polysilicon, metal, or other materials. The first gate 111 and the second gate 113 are etched, as shown in FIG11 , and finally the first gate structure 106 and the second gate structure 108 are obtained. The degree and number of etchings can be preset according to specific usage conditions.

Step S24, forming a first body region 103 of a second conductivity type on the epitaxial layer 102, so that the first trench 105 penetrates the first body region 103, forming a second body region 104 of a second conductivity type on the epitaxial layer 102, so that the second trench 107 penetrates the second body region 104, and the depth of the second body region 104 is less than the depth of the first body region 103;

As shown in FIG12, after obtaining the first gate structure 106 and the second gate structure 108, firstly, a photoresist 120 is coated on the second gate structure 108, and ions with a higher doping concentration are implanted into the first body region 103 to form the first body region 103. Then, the photoresist 120 is removed, and as shown in FIG13, ions with a lower doping concentration are implanted into the second body region 104 to form the second body region 104, wherein the depth of the second body region 104 is less than the depth of the first body region 103. For example, when the depth of the first body region 103 is 2 um, the depth of the second body region 104 may be 1 um, and when the depth of the first body region 103 is 1.8 um, the depth of the second body region 104 may be 0.8 um.

Step S25 , forming a first source region 109 of the first conductivity type on the first body region 103 , and forming a second source region 110 of the first conductivity type on the second body region 104 .

As shown in Fig. 14, the first source region 109 and the second source region 110 are formed by implanting ions of different doping concentrations into the first body region 103 and the second body region 104. The implanted ions may be arsenic ions or phosphorus ions.

Then, silicon dioxide is deposited on the first source region 109 and the second source region 110 to form an interlayer dielectric layer 115 , and a first contact hole 117 and a second contact hole 118 are etched in the interlayer dielectric layer 115 . Finally, metal 116 is deposited in the first contact hole 117 and the second contact hole 118 .

The preparation method of this embodiment obtains the second body region 104 with a shallower body region depth than the first body region 103 by presetting the depth of the first body region 103 and the second body region 104, and reduces the threshold voltage of the diode opening by reducing the length of the body region, so that the body diode is turned on with a lower threshold voltage, thereby reducing the reverse freewheeling power consumption. Wherein, in step S25, ions with a higher concentration are injected into the first body region 103, and ions with a lower concentration are injected into the second body region 104, which is equivalent to injecting ions of different concentrations into the first body region 103 twice, so that the ion doping concentration of the second body region 104 is less than the ion doping concentration of the first body region 103. By setting ions with different doping concentrations in different body regions, the conduction voltage of the diode of the trench MOS device is further reduced on the basis of limiting the depth of the first 103 and the second body region 104, and the diode conduction loss is reduced.

In one embodiment, as shown in FIG. 15 , in step S23 , forming a first gate structure 106 in the first trench 105 includes:

Step S231, growing a first dielectric layer 112 of a first preset thickness on the inner wall of the first trench 105, etching the first dielectric layer 112, and retaining the first dielectric layer 112 at the bottom of the first trench 105;

As shown in Figures 7 and 8, a first preset first dielectric layer 112 is grown on the inner wall of the first groove 105 by chemical vapor deposition process. For example, the thickness range of the first preset thickness of the dielectric layer is 0.2um-2um. The first dielectric layer 112 is etched to retain the first bottom dielectric layer 112-1. The thickness range of the first bottom dielectric layer 112-1 is 0.06um-0.3um.

Step S232 , growing a first dielectric layer 112 of a second preset thickness on the sidewall of the first trench 105 , depositing a first gate 111 on the first dielectric layer 112 , and etching a portion of the first gate 111 to obtain a first gate structure 106 in the first trench 105 .

As shown in Figures 9 to 11, a dielectric layer of a second preset thickness is grown on the side wall of the first groove 105. For example, the thickness range of the dielectric layer of the second preset thickness is 0.02um-0.1um. The first gate 111 is deposited on the first dielectric layer 112. The thickness range of the first gate 111 is 0.2um-2um. The first gate 111 is etched to obtain the first gate structure 106 in the first groove 105.

The preparation method of the embodiment of the present application reduces the threshold voltage for turning on the diode by limiting the thickness of the first gate structure 106 , turns on the body diode at a lower threshold voltage, and enhances the effect of reducing reverse freewheeling power consumption.

In one embodiment, as shown in FIG. 16 , in step S23 , forming the second gate structure 108 in the second trench 107 includes:

Step S233, coating the first gate structure 106 in the first trench 105 with a photoresist 120, etching the upper portion of the gate and the upper portion of the dielectric layer in the second trench 107, retaining the lower portion of the gate, and using the lower portion of the dielectric layer as the bottom dielectric layer 114-1 and the lower wall dielectric layer 114-2 of the second dielectric layer 114;

As shown in FIG17, after the photoresist 120 is coated on the first gate structure 106 in the first trench 105, the second gate 113 in the second trench 107 is etched, and the upper second gate 113 and the upper second dielectric layer 114 are etched respectively. As shown in FIG18, the lower second gate 113 and the lower second dielectric layer 114 are obtained, and the lower second dielectric layer 114 is composed of a bottom dielectric layer 114-1 and a lower wall dielectric layer 114-2.

Step S234, etching the lower part of the gate to remove the photoresist 120, growing an upper wall dielectric layer 114-3, wherein the upper wall dielectric layer 114-3 is located above the lower wall dielectric layer 114-2, and forming a second dielectric layer 114 by the bottom dielectric layer 114-1, the lower dielectric layer, and the upper wall dielectric layer 114-3;

As shown in Fig. 19, the lower part of the second gate 113 is etched to remove the photoresist 120. As shown in Fig. 20, an upper wall dielectric layer 114-3 is grown, wherein the second dielectric layer 114 is in a stepped shape, i.e., the thickness of the dielectric layer increases from top to bottom. For example, the thickness of the bottom dielectric layer 114-1 is in the range of 0.06um-0.3um, the thickness of the lower wall dielectric layer 114-2 is in the range of 0.01um-0.05um, and the thickness of the upper wall dielectric layer 114-3 is in the range of 0.005um-0.025um. For example, the thickness of the upper wall dielectric layer 114-3 is 0.025um, the thickness of the lower wall dielectric layer 114-2 is 0.01um, and the thickness of the bottom dielectric layer 114-1 is 0.06um.

Step S235 , depositing a second gate 113 on the second dielectric layer 114 , and etching a portion of the second gate 113 to obtain a second gate structure 108 in the second trench 107 .

As shown in Fig. 21, a second gate 113 is deposited on the second dielectric layer 114. As shown in Fig. 22, the second gate 113 is etched to obtain a second gate structure 108, wherein the degree and number of deposition and etching can be preset according to specific usage conditions.

After the second gate structure 108 is prepared and formed, in step S25, a first body region 103 of a second conductivity type is formed on the epitaxial layer 102, so that the first trench 105 penetrates the first body region 103, and a second body region 104 of a second conductivity type is formed on the epitaxial layer 102, so that the second trench 107 penetrates the second body region 104, and the depth of the second body region 104 is less than the depth of the first body region 103, including:

Specifically, after obtaining the first gate structure 106 and the second gate structure 108, as shown in FIG23, a photoresist 120 is first coated on the second gate structure 108, and ions with a higher concentration are implanted into the first body region 103 to form the first body region 103. Then, the photoresist 120 is removed, and ions with a lower concentration are implanted into the second body region 104 to form the second body region 104, as shown in FIG24.

In step S26, forming a first source region 109 of a first conductivity type on the first body region 103 and forming a second source region 110 of a first conductivity type on the second body region 104 includes:

As shown in FIG. 25 , ions with different doping concentrations are implanted into the first body region 103 and the second body region 104 to form a first source region 109 and a second source region 110 .

Then, as shown in Fig. 25, silicon dioxide is deposited on the first source region 109 and the second source region 110 to form an interlayer dielectric layer 115. As shown in Fig. 26, a first contact hole 117 and a second contact hole 118 are etched through the interlayer dielectric layer 115. Finally, as shown in Fig. 27, metal 116 is deposited in the first contact hole 117 and the second contact hole 118.

In the preparation method of this embodiment, the depth of the first contact hole 117 is increased, two contact holes of equal depth are set, and the second gate structure 108, the first source region 109, and the second source region 110 are connected through the first contact hole 117, the second contact hole 118, and the metal 116, so that when the device in FIG. 27 is in reverse freewheeling, the source is at a high potential and the drain is at a low potential, thereby turning on the body diode with a lower threshold voltage, and enhancing the effect of reducing the reverse freewheeling power consumption. The current is passed to ensure the normal operation and reliability of the device.

The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims (11)

1.A trench field effect transistor, comprising:

a substrate layer of a first conductivity type;

an epitaxial layer of a first conductivity type, the epitaxial layer being located on the substrate layer;

A first body region of a second conductivity type, the first body region being located on the epitaxial layer;

A second body region of a second conductivity type, the second body region being located on the epitaxial layer, the first body region being adjacent the second body region, the second body region having a depth less than a depth of the first body region;

The first groove penetrates through the first body region along the depth direction and extends into the epitaxial layer, and a first grid structure is arranged in the first groove;

the second groove penetrates through the second body region along the depth direction and extends into the epitaxial layer, and a second grid structure is arranged in the second groove;

A first source region of a first conductivity type, the first source region being located on the first body region;

a second source region of the first conductivity type, the second source region being located on the second body region;

The second body region has an ion doping concentration that is less than the ion doping concentration of the first body region.

2. The trench field effect transistor of claim 1, wherein forming said first gate structure comprises: forming a first dielectric layer of the first gate structure and a first gate electrode positioned on the first dielectric layer;

forming the second gate structure includes: and forming a second dielectric layer of the second gate structure, and a second gate positioned on the second dielectric layer, wherein the thickness of the second dielectric layer is smaller than that of the first dielectric layer.

3. The trench field effect transistor of claim 2, wherein forming the second dielectric layer of the second gate structure comprises: forming a bottom dielectric layer above the bottom of the second trench, an upper wall dielectric layer on the side wall of the second trench, and a lower wall dielectric layer on the side wall of the second trench, wherein the upper wall dielectric layer is above the lower wall dielectric layer, and the thickness of the upper wall dielectric layer is smaller than that of the lower wall dielectric layer.

4. The trench field effect transistor of claim 2, wherein a first contact hole of a predetermined shape is provided on the second gate structure, a second contact hole is provided between the first source region and the second source region, and metal is filled in the first contact hole and the second contact hole, so as to connect the second gate structure and the first source region and the second source region through the first contact hole, the metal, and the second contact hole.

5. The trench fet of claim 4 wherein the first and second contact holes have a depth ranging from 0.3um to 0.5um and a width ranging from 0.2um to 0.4um.

6. The trench field effect transistor of claim 1 wherein the depth of the first body region is in the range of 1um to 2um and the depth of the second body region is in the range of 0.5um to 1um.

7. The trench field effect transistor of claim 1, further comprising:

And the interlayer dielectric layer is positioned on the first source region and the second source region.

8. The trench field effect transistor of claim 7, further comprising:

and the metal layer is positioned on the interlayer dielectric layer.

9. The preparation method of the trench field effect transistor is characterized by comprising the following steps of:

Providing a substrate layer of a first conductivity type;

forming an epitaxial layer of a first conductivity type on the substrate layer;

Forming a first groove extending to the inside of the epitaxial layer along the depth direction, and forming a first grid structure in the first groove; forming a second groove extending to the inside of the epitaxial layer along the depth direction, and forming a second grid structure in the second groove;

Forming a first body region of a second conductivity type on the epitaxial layer, enabling the first trench to penetrate through the first body region, forming a second body region of the second conductivity type on the epitaxial layer, enabling the second trench to penetrate through the second body region, and enabling the depth of the second body region to be smaller than that of the first body region; controlling the ion doping concentration of the second body region to be smaller than that of the first body region;

A first source region of a first conductivity type is formed over the first body region and a second source region of the first conductivity type is formed over the second body region.

10. The method of manufacturing of claim 9, wherein forming a first gate structure in the first trench comprises:

Growing a first dielectric layer with a first preset thickness on the inner wall of the first groove, etching the first dielectric layer, and reserving the first dielectric layer at the bottom of the first groove;

And growing a first dielectric layer with a second preset thickness on the side wall of the first groove, depositing a first grid electrode on the first dielectric layer, and etching part of the first grid electrode to obtain a first grid electrode structure in the first groove.

11. The method of manufacturing of claim 10, wherein forming a second gate structure in the second trench comprises:

Coating photoresist on a first grid structure in the first groove, etching the upper part of the grid and the upper part of the dielectric layer in the second groove, reserving the lower part of the grid, and taking the lower part of the dielectric layer as a bottom dielectric layer and a lower wall dielectric layer of the second dielectric layer;

Etching the lower part of the grid electrode, removing the photoresist, and growing an upper wall dielectric layer, wherein the upper wall dielectric layer is positioned above the lower wall dielectric layer, and a second dielectric layer is formed by the bottom dielectric layer, the lower dielectric layer and the upper wall dielectric layer;

And depositing a second grid electrode on the second dielectric layer, and etching part of the second grid electrode to obtain a second grid electrode structure in the second groove.