CN117558618A - Micro processor for processing wafer with protective layer and wafer thereof - Google Patents
Micro processor for processing wafer with protective layer and wafer thereof Download PDFInfo
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- CN117558618A CN117558618A CN202311851745.4A CN202311851745A CN117558618A CN 117558618 A CN117558618 A CN 117558618A CN 202311851745 A CN202311851745 A CN 202311851745A CN 117558618 A CN117558618 A CN 117558618A
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- wafer
- protective layer
- hydrogen peroxide
- thickness
- silicon dioxide
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- 239000011241 protective layer Substances 0.000 title claims abstract description 209
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 116
- 238000000034 method Methods 0.000 claims abstract description 101
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 80
- 239000010410 layer Substances 0.000 claims abstract description 76
- 230000008569 process Effects 0.000 claims abstract description 71
- 239000011259 mixed solution Substances 0.000 claims abstract description 53
- 230000003647 oxidation Effects 0.000 claims abstract description 46
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 46
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 38
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 25
- 239000007788 liquid Substances 0.000 claims description 27
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 21
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 20
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 18
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 18
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 18
- 230000001590 oxidative effect Effects 0.000 claims description 15
- 229910021529 ammonia Inorganic materials 0.000 claims description 9
- 230000002829 reductive effect Effects 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000013136 deep learning model Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000003062 neural network model Methods 0.000 claims description 3
- 238000001556 precipitation Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 76
- 238000005468 ion implantation Methods 0.000 abstract description 66
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 230000008901 benefit Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 202
- 239000010408 film Substances 0.000 description 70
- 229910052751 metal Inorganic materials 0.000 description 29
- 239000002184 metal Substances 0.000 description 29
- 230000000694 effects Effects 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 229910052710 silicon Inorganic materials 0.000 description 22
- 239000010703 silicon Substances 0.000 description 22
- 238000004140 cleaning Methods 0.000 description 21
- 238000011109 contamination Methods 0.000 description 21
- 239000012535 impurity Substances 0.000 description 21
- 238000000137 annealing Methods 0.000 description 20
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 19
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 18
- 238000010884 ion-beam technique Methods 0.000 description 18
- 238000005530 etching Methods 0.000 description 17
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- 239000000356 contaminant Substances 0.000 description 9
- 230000002265 prevention Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 238000005224 laser annealing Methods 0.000 description 8
- 239000002245 particle Substances 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
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- 239000000203 mixture Substances 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 230000002411 adverse Effects 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 238000001035 drying Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 150000002736 metal compounds Chemical class 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 238000003672 processing method Methods 0.000 description 5
- 230000035484 reaction time Effects 0.000 description 5
- 239000008367 deionised water Substances 0.000 description 4
- 229910021641 deionized water Inorganic materials 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000036961 partial effect Effects 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241001050985 Disco Species 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000011550 stock solution Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
- H01J37/244—Detectors; Associated components or circuits therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3171—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation for ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention relates to a micro-processor for processing a wafer with a protective layer and the wafer thereof, wherein the protective layer of the wafer is arranged on the back of the wafer, the protective layer comprises at least two layers of silicon dioxide films, and the silicon dioxide films are formed by processing a second mixed solution comprising hydrogen peroxide through a wet process; during processing, the oxidation rates of at least two silica films are different. The protective layer has the advantages that due to different oxidation rates, the density of the silicon dioxide film of each hierarchical structure gradually becomes smaller from the first layer structure to the N layer structure, so that the diffusion speed of free ions entering each hierarchical structure is different. Therefore, the diffusion difficulty of free ions to the back surface of the wafer is increased, and the pollution of the free ions in the ion implantation process is effectively prevented.
Description
The invention relates to a processing method for preventing ion pollution of a wafer back surface process, which is divided into patent application with the application number of 202311038557.X and the application date of 2023, 8 and 17.
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a micro-processor for processing wafers with a protective layer and a wafer thereof.
Background
Ion implantation is required on the wafer backside of various IGBTs and other power devices. The conventional ion implantation method comprises the following steps: grinding and thinning the back of the wafer; wet silicon etching and cleaning are carried out on the back of the wafer; ion implantation is carried out on the back of the wafer; annealing the back surface of the wafer; cleaning the back of the wafer to remove the natural oxide layer; a metal film is deposited on the back of the wafer. Obviously, before the step of ion implantation, no protective layer is arranged on the back of the wafer, so that doping interference in the ion implantation process cannot be avoided, and subsequent electrical property and stability of the product are easily affected. To solve this problem, a protective layer is provided on the back side of the wafer.
The most important purpose of the protective layer is to avoid contamination in a broad sense. Contamination in a broad sense includes contamination by conventional surface particles or organics, as well as surface contamination by free ions (meaning ions that are not normally accelerated). These contaminants originate from processes (fig. 7) in which free molecules after long-term operation or ions accumulated at the ion beam receiver are bounced by impact and then attached back to the wafer surface.
Fig. 8 shows contamination after ion implantation in the absence and presence of a protective layer. In the absence of the protective layer, there are more impurity ions or atoms after ion implantation. Impurity ions or atoms are also present after annealing. In the presence of the protective layer, no impurities are present after ion implantation. I.e., if no protective layer is provided, doping interference exists on the back surface of the wafer.
Conventional protective layers are typically formed using oxidation or low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition-LPCVD). However, both of these methods require a relatively high temperature. Specifically, the protective layer in the prior art is a Thermal oxide or CVD method, and the temperature of the protective layer is generally above 500 ℃. During the wafer backside process, various metals or metal compounds have been provided on the wafer front side, and high temperatures above 500 ℃ can affect the structure or electrical properties already formed on the front side. Obviously, wafers provided with various metals or metal compounds on the front surface of the wafer are not suitable for directly forming the protective layer in a high-temperature mode.
In carrying out wafer backside processing, workers prefer to forgo the provision of the protective layer in view of the negative impact of the high temperature during the formation of the protective layer on the wafer's positive structure. Without the provision of a protective layer, the ion implantation process on the back side of the wafer cannot avoid doping interference.
For example, patent application publication number CN102047376a discloses a method for reducing particle contamination during ion implantation of one or more workpieces, the method comprising: providing an ion implantation system for implanting ions into one or more workpieces by an ion beam, wherein the ion implantation system comprises one or more components under a selective vacuum, wherein the one or more components have one or more contaminants associated with ion beam formation disposed thereon, and wherein the one or more contaminants are substantially in a first state; and introducing a gas into the ion implantation system, wherein the gas generally reacts with at least a portion of the one or more contaminants, wherein the at least a portion of the one or more contaminants are converted to a second state, and wherein the at least a portion of the one or more contaminants in the second state remain disposed on the one or more components, wherein the at least a portion of the one or more contaminants in the second state preferentially produce lower particulate contamination on the one or more workpieces.
For example, patent application publication number CN105097460a discloses a method of solving the path contamination of an ion implanter, the method comprising at least the steps of: providing ions with medium and light atomic weight as an ion source, adjusting an ion implanter to enable the ion source to form a divergent ion beam on a path after being accelerated, enabling the ion beam to strike a pollution layer on the inner wall of the path, and stripping the pollution layer; providing a plurality of control wafers arranged on an ion implantation machine, and implanting the ion beam and the stripped pollution layer into the control wafers to finish the removal of the pollution layer.
For example, patent application publication number CN101310360a discloses an ion implantation system comprising: for generating an ion beam; a beamline assembly for directing the ion beam toward a target device; a process chamber containing a target device for receiving the ion beam; and a gas introduction system coupled to the process chamber for providing a gas input to the process chamber, wherein the gas introduction system is operable to provide a gas into the process chamber in proximity to the target device in order to mitigate contamination of the target device and/or to change an existing property of a process environment to alter a physical or chemical state thereof.
For example, patent application publication No. CN106373846A discloses a method for improving metal contamination of a wafer high energy ion implanter, comprising the steps of: ions are generated by an ion source and changed into negative ions through exchanging electrons with a magnesium furnace; the negative ions exchange electrons with the gas after acceleration and are changed into positive ions again; after the positive ions are accelerated, beam current meeting the injection energy is screened out through an energy screening electromagnetic field; after the electromagnetic field is screened by the energy, an electric field deflecting a certain angle in the vertical direction of the beam is added to eliminate metal pollution, after the beam enters the electric field, uniform linear motion is carried out in the horizontal direction, acceleration motion is carried out in the vertical direction, and the set vertical deflection angle is used for further eliminating metal pollution.
For another example, patent application publication No. CN115064432a discloses a method of manufacturing a semiconductor device and a semiconductor device. The manufacturing method of the semiconductor device comprises the steps of providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a region to be processed; wet oxidation is carried out on the surface of the area to be treated, and a sacrificial oxide layer covering the area to be treated is formed; and removing the sacrificial oxide layer by adopting a wet etching process. However, in the scheme, the surface of the area to be treated is oxidized by the high-concentration ozonized deionized water to form a sacrificial oxide layer, the formed chemical oxide is about 8-12 m, the chemical oxide is thinner, and the thickness of the oxide is uneven. Therefore, the conventional sacrificial oxide layer is too thin to be used to protect the ion implantation process.
As described above, the ion implantation contamination prevention method in the related art includes a high temperature setting of a sacrificial oxide layer, removal of path contaminants, removal of metal contamination by gas isolation of contaminants, setting of an electric field and its deflection angle, and the like, but there is no contamination prevention scheme of setting the sacrificial oxide layer at a low temperature.
Accordingly, it is desirable to provide an ion implantation method in which a sacrificial oxide layer is provided at a low temperature to avoid the influence on the front surface of a wafer.
Furthermore, there are differences in one aspect due to understanding to those skilled in the art; on the other hand, since the applicant has studied a lot of documents and patents while making the present invention, the text is not limited to details and contents of all but it is by no means the present invention does not have these prior art features, but the present invention has all the prior art features, and the applicant remains in the background art to which the right of the related prior art is added.
Disclosure of Invention
In the prior art, conventional protective layers are formed using oxidation or LPCVD. However, both of these methods require a relatively high temperature, typically above 500 ℃. In the process of implementing the wafer back side, the wafer front side is already provided with various metals or metal compounds, so that it is not suitable to directly form the protective layer in a high temperature manner. In carrying out wafer backside processing, workers prefer to forgo the provision of the protective layer in view of the negative impact of the high temperature during the formation of the protective layer on the wafer's positive structure. Without the provision of a protective layer, the ion implantation process on the back side of the wafer cannot avoid doping interference.
In order to overcome the defects in the prior art, the invention provides an ion pollution prevention processing method for a wafer back surface process, which at least comprises the following steps: at least one protective layer is arranged on the back of the wafer based on a wet process; and under the condition that the growth thickness of the protective layer reaches the standard range, performing ion implantation on the back surface of the wafer.
The invention uses the wet process, can set up the protective layer without high temperature condition, therefore will not form the adverse effect to the structure of the front of the wafer in the course of forming the protective layer, help to avoid the popularization of the technical scheme that the impurity ion of the ion implantation process interferes with through the protective layer.
Preferably, the method for oxidizing the back surface of the wafer based on the second mixed solution to form the protective layer comprises the following steps: and oxidizing the back of the wafer by the second mixed solution containing ammonia water at room temperature to form the protective layer with the thickness reaching the standard range. The protective layer includes at least two silicon dioxide films formed based on different oxidation rates. The prior art cannot form a protective layer with a protective function for an ion implantation process at room temperature. The invention forms the protective layer by adopting the second mixed solution containing ammonia water, so that the silicon dioxide film forming the protective layer can form a film with uniform thickness.
Preferably, the method for oxidizing the back surface of the wafer based on the second mixed solution to form the protective layer further comprises: and oxidizing the back surface of the wafer by at least two second mixed liquids in turn to form the protective layer with the thickness reaching the standard range. The advantage of this arrangement is that the film formed from one of the mixtures is not thick enough to provide effective protection against free ions during ion implantation. Limited by the limitations of wet processing, the ultimate thickness of the monolayer film is 20 a. Therefore, the silicon dioxide films of different layers are oxidized alternately for multiple times by adopting different mixed solutions, so that the thickness and the density of the silicon dioxide films of different layers are different, and the rapid dispersion of free ions can be effectively avoided.
Preferably, the method for disposing at least one protective layer on the back of the wafer based on the wet process at least comprises the following steps: etching the back surface of the wafer based on the first mixed solution; oxidizing the back surface of the wafer based on the second mixed solution to form a protective layer; and cleaning the protective layer.
The invention etches the back of the wafer through a wet process, so that the back of the wafer reaches the required thickness. And oxidizing the back surface of the wafer by the second mixed solution to form a protective layer, so that the thickness change of the protective layer is controllable. Meanwhile, the second mixed liquid is adopted to form the protective layer, the protective layer can be realized without high temperature, and the influence of the high temperature on the front structure and the electrical property of the wafer is avoided.
Preferably, the method further comprises: annealing the back surface of the wafer;
preferably, the thickness of the protective layer is 10-20 angstroms, which is beneficial to ensuring the pollution-proof effect of the protective layer. If the protective layer is thin, it is difficult to form the isolation layer effectively to avoid contamination by impurity ions.
Preferably, the method for etching the back surface of the wafer based on the first mixed solution at least comprises the following steps: the etching thickness range of the wafer back surface based on the first mixed solution is as follows: 5-15 um. The etch thickness is determined by the product requirements. This thickness range is advantageous for the growth of the protective layer.
Preferably, the second mixed solution for oxidizing the back surface of the wafer to form the protective layer at least includes: a mixed solution of ammonia water, hydrogen peroxide and water; and/or a mixed solution of sulfuric acid, hydrogen peroxide and water. The second mixed liquor is configured such that the oxidation rate of the grown protective layer is controllable.
Preferably, the method further comprises: and carrying out metal coating on the back of the wafer, wherein the metal film formed by the metal coating mode at least comprises one of aluminum, titanium, nickel and silver. The metal coating is favorable for complete encapsulation of the wafer.
Preferably, the method for disposing at least one protective layer on the back of the wafer based on the wet process at least comprises the following steps: etching, rinsing and/or drying the back surface of the wafer based on the first mixed solution; oxidizing the back surface of the wafer based on the second mixed solution to form a protective layer; and cleaning and/or drying the protective layer. All the steps are completed by a wet process, a high-temperature step is not needed, and the pollution prevention effect of ion implantation can be well realized under the condition of ensuring the electrical characteristics of the front surface of the wafer.
Preferably, the method further comprises: the oxidation rate of the protective layer is regulated by regulating the concentration of hydrogen peroxide in the second mixed solution. By increasing the concentration of hydrogen peroxide, the oxidation rate can be increased and the growth time of the protective layer can be shortened.
The invention also provides a wafer with the protective layer, wherein the protective layer is arranged on the back of the wafer, the protective layer comprises at least two layers of silicon dioxide films, and the silicon dioxide films are formed by processing a second mixed solution comprising hydrogen peroxide through a wet process; during processing, the oxidation rates of at least two silica films are different.
According to a preferred embodiment, the oxidation rate of the silica film is regulated by adjusting the concentration of hydrogen peroxide.
According to a preferred embodiment, at least two silica films are formed by alternate oxidation of a second, different mixture.
According to a preferred embodiment, the first silicon dioxide film on the back of the wafer is formed by oxidizing a second mixed liquid comprising sulfuric acid and hydrogen peroxide; a second silica film formed by precipitation on the surface of the first silica film is formed of a second mixed solution including ammonia and hydrogen peroxide; the first silicon dioxide film and the second silicon dioxide film have different densities.
According to a preferred embodiment, the arrangement rule of the hierarchical structure of the protection layer includes: the silicon dioxide film on the back of the wafer is of a first layer structure; as the level increases, the oxidation rate of the silicon oxide film becomes gradually smaller.
According to a preferred embodiment, the oxidation rate of the silica film is adjusted in such a way that: the larger the proportion of hydrogen peroxide in the second mixed solution, the larger the thickness value of the silica film, and the faster the oxidation rate.
According to a preferred embodiment, the second mixed solution is a mixed solution of ammonia water, hydrogen peroxide and water, or a mixed solution of sulfuric acid, hydrogen peroxide and water.
According to a preferred embodiment, in the second mixture, the ratio of ammonia, hydrogen peroxide and water is 1:2: 50-1: 10:50.
the invention also provides a micro-processor for processing the wafer with the protective layer, wherein an early warning model is arranged in the micro-processor; under the condition that the room temperature is reduced or increased, the micro-processor acquires historical data of the thickness value of the protective layer corresponding to the room temperature data and the proportioning data of the second mixed solution; when the early warning model judges that the historical data of the thickness value of the protective layer is smaller than and not in the thickness standard range, the micro-processor sends out early warning signals of sound, light, electricity and combination thereof through an early warning component connected with the micro-processor; the protective layer comprises at least two layers of silicon dioxide films, and the silicon dioxide films are formed by processing a second mixed solution comprising hydrogen peroxide through a wet process; during processing, the oxidation rates of at least two silica films are different.
According to a preferred embodiment, the microprocessor establishes a data connection with at least one temperature sensor that collects room temperature in a wired or wireless manner to receive room temperature data; the micro processor establishes a data connection relation with equipment for detecting the thickness of the protective layer in a wired or wireless mode so as to receive the thickness data of the protective layer; the micro processor learns historical data of the room temperature, the proportion of the second mixed liquid and the thickness of the protective layer based on the deep learning model or the neural network model, and establishes an association relation between the thickness of the protective layer, the proportion of the second mixed liquid and the room temperature, so as to construct an early warning model.
Drawings
FIG. 1 is a flow chart of the steps of an ion contamination prevention processing method for wafer backside processing according to a preferred embodiment of the present invention;
FIG. 2 is a schematic view of the front surface of a wafer without a protective layer according to the present invention;
FIG. 3 is a schematic view of the front surface of a wafer with a protective layer according to the present invention;
FIG. 4 is a SIMS simulation of a phosphorus ion implantation laser anneal without a protective layer provided by the present invention;
FIG. 5 is a SIMS simulation of the invention after laser annealing of phosphorus ion implantation after the provision of a protective layer;
Fig. 6 is a flow chart of specific steps of an ion implantation method in the prior art;
FIG. 7 is a schematic diagram of free ions of an ion implantation process of the prior art;
FIG. 8 is a comparative schematic diagram of the contamination effect of ion implantation in the prior art, if a protective layer is provided;
fig. 9 is a schematic diagram showing a change in concentration of phosphorus ions contaminated after ion implantation in the prior art;
FIG. 10 is a flowchart illustrating another ion implantation method according to the present invention;
fig. 11 is a schematic view of a partial enlarged machine of the wet etching/cleaning apparatus provided by the present invention.
List of reference numerals
1: the back surface of the wafer; 2: the front surface of the wafer; 3: a protective layer; 5: an ion beam; 6: free ions; 7: and (3) a nozzle.
Detailed Description
The following detailed description refers to the accompanying drawings.
The invention provides an ion pollution prevention processing method for a wafer back surface process, and also provides a semiconductor device produced based on the ion implantation method.
In the prior art, conventional protective layers are formed using oxidation or LPCVD. The protective layer is pre-selected from SiO 2 A film. However, both of these methods require a relatively high temperature, typically above 500 ℃. In implementing wafer backside process The front side of the wafer has been provided with various metals or metal compounds. The high temperature can have an effect on the structural or electrical characteristics of the various metals or metal compounds on the front side of the wafer. It is not suitable to form the protective layer directly at high temperature.
As shown in fig. 6, specific method steps for performing ion implantation in the prior art include S11 to S16.
S11: grinding and thinning the back of the wafer;
s12: wet silicon etching and cleaning are carried out on the back of the wafer;
s13: ion implantation is carried out on the back of the wafer;
s14: annealing the back surface of the wafer;
s15: cleaning the back of the wafer to remove the natural oxide layer;
s16: and depositing a metal film on the back of the wafer.
That is, in the wafer processing technology in the prior art, before ion implantation, a protective layer is not arranged on the back surface of the wafer, so that various pollution is caused in the ion implantation process.
As shown in fig. 7, when the ion beam 5 enters the wafer back surface 1, the free ions 6 near the ion beam 5 are mixed and enter, and doping interference of ion implantation is formed.
As shown in the three partial figures of the first row in fig. 8, in the case where the shield layer is provided, during ion implantation, a part of the free ions is blocked at the surface thereof by the shield layer, and a part of the free ions enter the shield layer and are blocked by the shield layer so as not to enter the back surface of the wafer, so that when the free ions enter the shield layer, only ions in the ion beam 5 enter the back surface of the wafer. After annealing the wafer, only the required ions are present on the back of the wafer, and no impurity ions are present.
As shown in the three partial figures of the second row in fig. 8, in the case where the protective layer is not provided, the free ions are implanted into the back surface of the wafer along with the ions in the ion beam during the ion implantation. The free ions form contamination. After annealing the wafer, impurity ions remain in the wafer.
As shown in fig. 9, since the protective layer is not provided, the concentration distribution of P (phosphorus) ions on the wafer surface after ion implantation is shown in the figure. The concentration of P (phosphorus) ions is reduced to normal post ion implantation levels with increasing depth from very high concentrations near the wafer surface. This is precisely because the P (phosphorus) ions accumulated on the silicon surface are diffused inward during the laser annealing process without protection of the protective layer.
In the actual production process, the utilization rate of the traditional protective layer forming mode in the prior art is low. In the case where there is a concern that the high temperature adversely affects the structure of the front surface of the wafer, more workers tend to discard the protective layer setting step. Without the provision of a protective layer, the ion implantation process on the back side of the wafer cannot avoid doping interference.
In view of the drawbacks of the prior art, it is desirable to provide a method of manufacturing a protective layer and an ion implantation method that can be performed at room temperature or within a temperature range that does not affect the structures already formed on the front surface of a wafer.
The temperature range that does not affect the structure already formed on the front surface of the wafer is, for example: less than or equal to 400 ℃.
Based on the object of solving the drawbacks of the prior art, the present invention proposes a step of forming a sacrificial oxide film by a wet process. Since there are other wet process steps before the ion implantation step is performed on the back surface of the wafer, the step of forming the protective layer by using the wet process can be performed in the same equipment, without adding additional processing equipment or adding excessive cost and process flow. The ion implantation method of the invention can more meet the requirements of the current wafer processing technology.
In the present invention, a wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, and the original material is silicon. The high-purity polycrystalline silicon is dissolved and then doped with silicon crystal seed, and then slowly pulled out to form cylindrical monocrystalline silicon. The silicon ingot is ground, polished and sliced to form a silicon wafer, i.e., a wafer.
The front side of the wafer refers to the side with the pattern after the single-sided processing of the wafer is completed. The back side of the wafer refers to the side opposite the front side.
Example 1
In order to overcome the defects in the prior art, the invention provides an ion pollution prevention processing method for a wafer back surface process, which at least comprises the following steps: at least one protective layer is arranged on the back of the wafer based on a wet process; and under the condition that the growth thickness of the protective layer reaches the standard range, performing ion implantation on the back surface of the wafer.
The wet process is performed without the need for high temperature conditions. The temperature ranges in which wet processes can generally be successfully practiced are: 20-50 ℃. The temperature is obviously lower than 400 ℃, and the adverse effect on the structure of the front surface of the wafer is not formed at all.
The invention uses the wet process, can set up the protective layer without high temperature condition, therefore will not form the adverse effect to the structure of the front of the wafer in the course of forming the protective layer, help to avoid the popularization of the technical scheme that the impurity ion of the ion implantation process interferes with through the protective layer.
The process flow for processing the back side of the wafer is briefly described as follows.
Obtaining a chip wafer (Production wafer) of the IGBT completing the front side process from a front side factory; sticking a film on the front surface of the wafer; grinding and thinning the back of the wafer from 725 micrometers to about 60-200 micrometers; wet silicon etching (etching about 5-20 microns to a final target thickness) and cleaning the back of the wafer; tearing the film from the front surface of the wafer; performing ion implantation on the back surface of the wafer; carrying out laser annealing on the back surface of the wafer; cleaning the back of the wafer; depositing a metal film (3-4 layers of metal) on the back of the wafer; performing chip testing; cutting off the wafer Tai drum ring; and (5) cutting the chip. After these steps are completed, the wafer is sent to a packaging factory for further processing such as packaging testing.
In the above steps, back grinding, back etching/cleaning, back ion implantation, annealing, back deposition of metal film, and chip testing were all performed using corresponding different equipment.
In the present invention, as shown in fig. 1, the process of the front surface of the wafer is completed, and specific steps of the ion implantation method are as follows.
S21: and grinding and thinning the back of the wafer.
Specifically, the wafer is ground and thinned in a Taiko grinding mode through Disco's machine equipment. The final thickness of the wafer is in the range of 50-150 um. The specific thickness of the wafer is determined according to the product characteristic requirement.
S22: wet silicon etching, protective layer setting and cleaning are carried out on the back of the wafer.
Wafers are loaded into the apparatus.
A first step of: etching the back surface of the wafer based on the first mixed solution.
Preferably, the etching thickness range for etching the back surface of the wafer based on the first mixed liquid is: 5-15 um. The main components of the first mixed solution at least comprise HF, HNO and H 2 SO 4 、H 3 PO 4 One of them.
The etch thickness is determined by the product requirements. This thickness range is advantageous for the growth of the protective layer.
Preferably, after etching is completed, the back surface of the wafer is rinsed and/or dried to remove impurities from the back surface of the wafer, so that the subsequent growth of the protective layer is more uniform.
And a second step of: oxidizing the back surface of the wafer based on the second mixed solution to form a protective layer.
As shown in fig. 2, when the protective layer is not provided, silicon on the wafer back surface 1 is exposed, and free ions are likely to exist. As shown in fig. 3, in the case of providing a protective layer, a protective layer 3 is provided on the silicon surface of the wafer back surface 1.
After the protective layer is formed in a conventional manner in the prior art, the thickness of the protective layer ranges from 20 to 200 EmiWhen the protective layer is formed by adopting the wet process, the limit thickness of the protective layer is 20 Emi +.>Thus, the thicker the protective layer, the better.
Preferably, the standard range of the thickness of the protective layer is 10 to 20 EmiIs beneficial to ensuring the pollution-proof effect of the protective layer. If the protective layer is thin, it is difficult to form the isolation layer effectively to avoid contamination by impurity ions.
Preferably, the standard range of the thickness of the protective layer is 10 to 15 EmiNot only can be effectively pollution-proof, but also the growth time of the protective layer can be shortened, the process is easier to realize, and the manufacturing cost is lower. If the thickness of the protective layer is set to be more than 15 Emi->More process time is required to increase the thickness of the protective layer while the thickness of the protective layer increases less. Therefore, the thickness of the protective layer is set to 10 to 15 Emi ∈ based on the demand of production efficiency >The production cost is lower, and the anti-pollution effect of the protective layer can be achieved.
More preferably, the protective layer has a thickness of 15 EmiAfter the free ions enter the protective layer, even if the polluted free ions diffuse to the direction of the back surface of the wafer in the annealing stage, the free ions cannot completely pass through the protective layer with the thickness and cannot enter the back surface of the wafer.
As shown in fig. 11, after the wafer is placed in the machine of the apparatus, the second mixed liquid is sprayed toward the wafer back surface 1 through the nozzle 7 while the wafer is rotated. During the shower, the wafer backside 1 undergoes an oxidation effect forming a protective layer. During the spraying process, the second mixed solution can clean particles on the back surface of the wafer. After the cleaning is completed, the wafer is transferred to a drying assembly inside the apparatus for drying.
Preferably, the thickness of the protective layer of the batch of wafers is monitored and confirmed according to a preset period, so that the thickness of the protective layer of the wafers is prevented from not reaching the expected thickness. Preferably, the thickness of the protective layer is measured using an ellipsometer or a Transmission Electron Microscope (TEM).
Since the formation of the protective layer by the wet process can be performed in an environment of 20 to 50 ℃. Then, the temperature conditions for forming the protective layer remain: (1) at room temperature; (2) at a predetermined fixed temperature.
When performed at room temperature, the oxidation rate of the protective layer on the wafer surface is not constant. When the oxidation rate becomes slow, it is necessary to adjust the oxidation rate of the protective layer.
Preferably, under the condition that the oxidation rate of the protective layer is slower, the oxidation rate of the protective layer is faster by increasing the growth time of the protective layer or adjusting the proportion of the second mixed solution.
The protective layers of the wafer are all formed and inspected in batches. After the growth time of the protective layer reaches the preset time, if the detection finds that the thickness of the protective layer of the wafers in the batch does not reach the standard range, the growth time of the protective layer of the wafers in the next batch is properly prolonged, or the second mixed solution is adjusted/replaced, so that the hydrogen peroxide concentration is increased. Preferably, the second mixed solution is formed by mixing ammonia water, hydrogen peroxide and water according to a certain proportion. For example, the ratio of ammonia, hydrogen peroxide and water is 1:5:50. the second mixed liquor is set as a mixed liquor of ammonia water, hydrogen peroxide and water, which has the advantage that the oxidation rate of the grown protective layer is controllable. The oxidation rate can be increased by increasing the concentration of hydrogen peroxide.
The following two reactions A and B occur on the silicon surface with the ammonia and hydrogen peroxide mixture.
Reaction A: si+2H 2 O 2 →SiO 2 +2H 2 O；
B reaction: 2SiO 2 +4NH 4 OH→2(NH 4 ) 2 SiO 3 +2H 2 O。
The reaction A generates SiO 2 The B reaction is to make SiO 2 Becomes ammonium silicate to make it water soluble.
The reaction A and the reaction B are also the reaction basis of removing particles on the surface of the wafer by the mixed solution of ammonia water and hydrogen peroxide.
The mixed solution of ammonia water and hydrogen peroxide can also remove surface particles at the same time, thereby achieving the effect of enabling SiO to be 2 The film has cleaner effect, and the final SiO can be balanced by increasing the concentration of hydrogen peroxide 2 Thickness of the film.
Wherein the SiO formed can be caused by increasing the hydrogen peroxide concentration 2 And finally deposit on the surface of the wafer to form SiO 2 A film.
Preferably, in order to enable both the formation of SiO on the wafer surface 2 The film can also enable the second mixed solution to have certain cleaning capacity, and the invention enables the proportion of ammonia water, hydrogen peroxide and water to be configured at 1:2: 50-1: 10: 50. I.e. the ratio provides sufficient hydrogen peroxide to form SiO 2 The film also provides enough ammonia to remove particles.
Preferably, the second mixed solution may also be other chemical solutions having oxidizing properties, such as mixed solution of sulfuric acid, hydrogen peroxide and water. Wherein, sulfuric acid is mainly used as a catalyst to promote the oxidizing environment, and the main reaction is also the A reaction: si+2H 2 O 2 →SiO 2 +2H 2 O。
If only one protective layer is provided, e.g. only one SiO layer 2 Thin film, monolayer SiO based on process limitations 2 The thickness of the film can only reach 20 mSiO 2 The compactness of the film is the same. This causes free ions to diffuse in the film without a change in compactness.
If two layers of protective layers with different compactness are arranged. Based on the difference in compactness, the diffusion rate of free ions is significantly slowed down. In the subsequent annealing process of the wafer, the diffusion barrier of the free ions becomes large, and the free ions are less likely to diffuse into the back surface of the wafer.
Preferably, the at least two second mixed liquids oxidize the back of the wafer in turn to form the protective layer with the thickness reaching the standard range.
For example, the two second mixed liquids include ammonia water, a hydrogen peroxide mixed liquid, and sulfuric acid, a hydrogen peroxide mixed liquid.
Firstly, sulfuric acid and hydrogen peroxide mixed solution are used for forming a first layer of SiO on the back surface of a wafer 2 A film. SiO formed at this time 2 The surface of the film is uneven and SiO exists 2 A plurality of particles.
Then ammonia water and hydrogen peroxide mixed solution are used for preparing the first SiO layer 2 The surface of the film is continuously deposited to form a second layer of SiO 2 A film. In this way, the overall thickness of the protective layer is increased, and the surface particles react with ammonia water to form ammonium silicate and dissolve in water. Two-layer SiO 2 The density of the film is different, so that the diffusion obstruction degree of the film to free ions is different.
Preferably, the first layer of SiO 2 The density of the film is higher than that of the second layer SiO 2 The compactness of the film.
Preferably, siO in the protective layer 2 The film is not limited to two layers, but can be three layers or four layers. Preferably, sulfuric acid, hydrogen peroxide mixture and ammonia water, hydrogen peroxide mixture may be deposited in turn with each other and circulated a plurality of times to form a three-layer, four-layer structure.
Preferably, the SiO is in direct contact with the back of the wafer 2 The film is a first layer structure, and SiO deposited on the surface of the first layer structure 2 The film is a second layer structure, and so on.
The hierarchical structure of the protective layer is set as follows: with increasing level, siO 2 The oxidation rate of (a) becomes gradually smaller. Namely, according to the arrangement sequence of the layers, the oxidation rate of the first layer structure is less than the oxidation rate of the second layer structure is less than the oxidation rate of the third layer structure … … is less than the oxidation rate of the N layer structure.
Due to the difference of oxidation rates, siO of each hierarchical structure 2 The density of the film gradually becomes smaller from the first layer structure to the Nth layer structure, so that the diffusion speed of free ions entering each hierarchical structure is different. Therefore, the diffusion difficulty of free ions to the back surface of the wafer is increased, and the pollution of the free ions in the ion implantation process is effectively prevented.
Preferably, each layer structure of the protective layer of the invention can be formed by deposition of ammonia water and hydrogen peroxide mixed solution with different concentrations.
Due to the concentration of hydrogen peroxide and SiO in the second mixed solution 2 Is related to the oxidation rate of (a). The greater the proportion of hydrogen peroxide, the higher the concentration, the SiO formed 2 The greater the thickness value of the film, i.e., the protective layer, the faster the oxidation rate.
Thus, with deposited SiO 2 The concentration of hydrogen peroxide in the second mixed solution gradually becomes smaller due to the increase of the layer number of the thin film, and the SiO can be realized along with the increase of the layer level 2 The oxidation rate of (c) becomes gradually smaller.
Preferably, the layer level is increased, siO 2 The oxidation rate of (c) becomes gradually greater. By the arrangement, the density of each level can be different and the diffusion of free ions can be prevented. But the technical effect of this solution is slightly worse. Preferably, the oxidation rate of the protective layer is adjusted by adjusting the concentration of hydrogen peroxide in the second mixed solution.
Table 1 shows a part of sample data of the concentration and oxidation rate of hydrogen peroxide. As can be seen from Table 1, the higher the hydrogen peroxide ratio, i.e., the higher the concentration in the same volume of the mixture, the higher the SiO 2 The faster the oxidation rate of (c). In the stock solutions for the preparation used in table 1, specific concentrations of ammonia water and hydrogen peroxide are shown below.
Ammonia = 29% nh 4 OH; hydrogen peroxide = 31% h 2 O 2 。
Table 1 formation of protective layer sample data
As shown in Table 1, the hydrogen peroxide ratio of the sample of group 4 is larger than that of the sample of group 1, and SiO is produced by the sample of group 4 under the conditions of the same temperature and the same reaction time 2 The film thickness was 12. Mu.mSiO generated by group 1 samples 2 The film thickness was 10. Mu.m->
The temperature and reaction time were the same for group 5 samples compared to group 1 samples. The hydrogen peroxide ratio of the 5 th group sample is also larger than that of the 1 st group sample, and the 4 th group sample generates SiO 2 Film thickness value was 13 EmiObviously, under the same conditions of temperature and reaction time, the larger the proportion of hydrogen peroxide, the higher the concentration, the SiO produced 2 The greater the thickness value of the film, i.e., the protective layer, the faster the oxidation rate. Therefore, adjusting the thickness of the protective layer by adjusting the concentration of hydrogen peroxide has a remarkable effect.
As shown in group 2 data and group 3 data, the increase in temperature instead caused the formation of SiO 2 Thickness value of film to SiO generated by group 1 sample 2 The smaller the film thickness value. I.e. an increase in temperature instead reduces the oxidation rate of the protective layer.
For example, when ammonia: hydrogen peroxide: the ratio of water is 1:2: at 50, the final thickness of the protective layer at a reaction time of 5 minutes was 10. Mu.m When ammonia is in ammonia water: hydrogen peroxide: the ratio of water is 1:10: at 50, the final thickness of the protective layer is 13 Emi ∈ in the case of a reaction time of 5 minutes>The reaction speed is improved to 1.3 times.
Obviously, the invention can improve the oxidation rate and shorten the growth time of the protective layer by improving the concentration of the hydrogen peroxide.
Preferably, even if the apparatus for the growth of the protective layer is capable of temperature control, the second mixed liquid is enabled to etch the wafer at a set temperature to grow the sacrificial oxide film. However, the influence of the room temperature of the environment in which the apparatus is located on the temperature of the second mixed liquid still exists, so that it is difficult to form a stable thickness of the protective layer on the surface of the wafer. The thickness of the protective layer on the wafer surface was found in the inspection.
Based on this defect, the present invention provides a microprocessor. The microprocessor establishes a data connection with at least one temperature sensor for collecting room temperature in a wired or wireless manner to receive room temperature data. The microprocessor establishes a data connection relationship with the device for detecting the thickness of the protective layer in a wired or wireless mode so as to receive the thickness data of the protective layer.
The micro processor learns the association relation between the thickness of the protective layer and the ratio of the second mixed liquid and the room temperature according to the historical data of the deep learning model or the neural network model on the room temperature, the ratio of the second mixed liquid and the thickness of the protective layer, so that a prediction model or an early warning model is constructed and formed.
In the case of a decrease or increase in room temperature, the microprocessor acquires historical data of the thickness value of the protective layer corresponding to the room temperature data and the proportioning data of the second mixed liquid. When the historical data of the thickness value of the protective layer is smaller than and not in the thickness standard range, the micro-processor sends out an early warning signal of sound, light, electricity and combination thereof through the early warning component connected with the micro-processor. The early warning component is, for example, a sound playing component, a light component, a display component and the like.
The staff receives the early warning signal, and can replace the second mixed solution in time or lengthen the growth time of inoxidizing coating, realize controlling the thickness of inoxidizing coating and be in the effect of standard scope, avoid the emergence of the phenomenon that the wafer reworks that leads to because inoxidizing coating thickness is not up to standard.
And a third step of: and (5) cleaning the protective layer by deionized water and drying.
And cleaning the grown protective layer by adopting a second mixed solution to remove impurities on the surface of the protective layer. During the growth of the protective layer, the temperature is lower than 400 ℃, and if other substances are introduced between 300 and 400 ℃, the cost is increased. Therefore, the invention uses deionized water to clean the protective layer and remove the chemical liquid.
After the cleaning is completed, the protective layer on the back surface of the wafer is cleaned with deionized water to remove the residual liquid medicine on the surface of the back surface of the wafer, and then the wafer is dried. The wafer is withdrawn from the apparatus.
The invention etches the back of the wafer through a wet process, so that the back of the wafer reaches the required thickness. And oxidizing the back surface of the wafer by the second mixed solution to form a protective layer, so that the thickness change of the protective layer is controllable. Meanwhile, the second mixed liquid is adopted to form the protective layer, the protective layer can be realized without high temperature, and the influence of the high temperature on the front structure and the electrical property of the wafer is avoided.
All the steps are completed by a wet process, a high-temperature step is not needed, and the pollution prevention effect of ion implantation can be well realized under the condition of ensuring the electrical characteristics of the front surface of the wafer.
S23: ion implantation is performed on the back side of the wafer.
The implanted ions include at least various combinations of phosphorus and boron, or boron and hydrogen, or boron, phosphorus and hydrogen.
For example, the implantation conditions for the phosphorus and boron combination are:
P/500kev/1E13/tilt 0+B/20kev/1E13/tilt 0。
i.e., the implantation energy of the P ion beam is 500kev; the injection dose is 1E13; the implant tilt angle is 0. The implantation energy of the B ion beam is 20kev; the injection dose is 1E13; the implant tilt angle is 0.
As another example, the implantation conditions for the boron and hydrogen combination are:
B/20kev/1E13/tilt 0+H/400Kev/1E14/tilt 0。
i.e., the implantation energy of the B ion beam is 20kev; the injection dose is 1E13; the implant tilt angle is 0. The implantation energy of the H ion beam is 400kev; the injection dose is 1E14; the implant tilt angle is 0.
S24: annealing is performed on the back of the wafer.
Preferably, the optional annealing process comprises: laser annealing, furnace tube diffusion annealing, and the like.
For example, green light with an energy of 2 joules is used to anneal boron and/or phosphorus.
The annealing conditions of the furnace tube are as follows: the wafer was annealed in a nitrogen atmosphere at a temperature of 350 degrees for 60 minutes.
Fig. 4 is a SIMS simulation after P ion implantation and laser annealing without the protective layer. As shown in fig. 4, there is a spike in the concentration of P near the wafer surface, indicating that the implanted ions are disturbed by P contamination.
Fig. 5 is a SIMS simulation after P ion implantation and laser annealing with the protective layer provided. As shown in fig. 5, there is no significant abrupt change in the concentration of P near the wafer surface, indicating that the implanted ions are not disturbed by P ion contamination.
S25: and cleaning the back of the wafer to remove the oxide layer.
The oxide layer herein refers to a natural oxide layer.
The existence of various oxide layers forms contact obstruction between the metal coating and silicon, so that the effect of the metal coating is poor. The metal film is also not flat enough and strong. The protective layer should also be removed. The native oxide should be cleaned away.
The oxide layer is cleaned to improve the contact effect of the subsequent metal coating and silicon, so that the metal coating is fully contacted with the silicon, and the metal coating can be flatter. The cleaning liquid is, for example, hydrofluoric acid (HF).
For example, wafers are loaded into the apparatus and the back side of the wafer is etched/rinsed/dried with hydrofluoric acid. And after the completion, the wafer is withdrawn from the equipment.
S26: and depositing a metal film on the back of the wafer.
The metal film formed includes at least one of aluminum, titanium, nickel, and silver.
Specifically, a wafer is loaded in an apparatus; sequentially depositing an Al film, a Ti film, a Ni film and an Ag film. After the metal plating is completed, heating is performed at a temperature of 350 ℃ to alloy each layer of metal film. And after the completion, the wafer is withdrawn from the equipment.
The above steps and drawings can clearly show that the protection layer generated by the wet process can also prevent pollution caused by ion implantation. The adoption of the wet process to generate the protective layer does not need high temperature and does not have adverse effect on the front structure or the electrical characteristics of the wafer. The step sequence of the ion implantation effect on the back surface of the wafer with or without the protective layer shows that the arrangement of the protective layer of the invention does not add new equipment, and does not obviously increase labor cost and process flow.
Example 2
This embodiment is a further improvement of embodiment 1, and the repeated contents are not repeated.
Preferably, the method further comprises: after ion implantation, the protective layer is removed based on a wet process. And removing the protective layer, so that the invasion and interference of ion impurities in the protective layer to the thermal diffusion of the back surface of the wafer in the annealing process can be further avoided.
As shown in fig. 10, the steps of the present embodiment are as follows.
S31: grinding and thinning the back of the wafer;
s32: wet silicon etching, protective layer setting and cleaning are carried out on the back of the wafer;
s33: ion implantation is carried out on the back of the wafer;
s34: removing the protective layer on the back of the wafer based on a wet process;
s35: annealing is carried out on the back of the wafer;
s36: and cleaning the back of the wafer to remove the oxide layer. The oxide layer here includes a natural oxide layer;
s37: and depositing a metal film on the back of the wafer.
The step of removing the protective layer on the back side of the wafer based on the wet process is as follows.
As shown in fig. 4, the presence of the protective layer causes free impurity ions to be blocked out of the silicon by the protective layer and intrude into the protective layer. If the protective layer is kept for a long time, the free impurity ions may slowly diffuse in the protective layer, especially deep into the silicon during annealing, and eventually still diffuse into the silicon on the back side of the wafer. In order to avoid this, it is preferable to remove the protective layer containing impurity ions after the ion implantation step is completed.
For example, the surface of the protective layer is cleaned by using hydrofluoric acid (HF) solution, so that impurity ions on the surface of the protective layer are reduced, and further diffusion of the impurity ions to the back surface of the wafer in the annealing process is avoided. The protective layer is cleaned before the laser annealing, so that impurity ions accumulated on the surface of the protective layer in the ion implantation process can be further removed, and the possibility that the impurity ions are diffused deeper into the surface of the wafer in the laser annealing process is reduced.
For example, loading a wafer into an apparatus; etching, rinsing and/or drying the back of the wafer with a hydrofluoric acid (HF) solution; the wafer is withdrawn from the apparatus.
The cleaning speed of the protective layer can be accelerated by etching the protective layer by adopting hydrofluoric acid (HF) solution. The etched surface is cleaned with a hydrofluoric acid (HF) solution to remove residual impurities from the protective layer. And the back of the cleaned wafer is dried, so that the influence of residual solution on the annealing process can be reduced.
In this embodiment, the impurity ions in the protection layer are removed before annealing, so that the possibility of diffusing into the wafer in the annealing process is eliminated, and the effect of preventing the ion pollution of the protection layer is enhanced.
As described above, the ion implantation of this example 2 has a better contamination prevention effect than that of example 1, and there is no additional equipment, and the production cost and the process flow are both low. The ion implantation method in this embodiment does not need to form a protective layer under high temperature conditions, thereby avoiding adverse effects of high temperature on the front structure and electrical characteristics of the wafer, and effectively preventing intrusion of free ions into silicon during ion implantation from polluting, so that the ion implantation method can be widely implemented in the semiconductor field.
It should be noted that the above-described embodiments are exemplary, and that a person skilled in the art, in light of the present disclosure, may devise various solutions that fall within the scope of the present disclosure and fall within the scope of the present disclosure. It should be understood by those skilled in the art that the present description and drawings are illustrative and not limiting to the claims. The scope of the invention is defined by the claims and their equivalents. The description of the invention includes a plurality of inventive concepts, such as "preferably", "according to a preferred embodiment" or "optionally" each meaning that the corresponding paragraph discloses a separate concept, the applicant reserves the right to filed a divisional application according to each inventive concept.
Claims (10)
1. A wafer with a protective layer, the protective layer (3) being arranged on the back (1) of the wafer, characterized in that,
the protective layer (3) comprises at least two layers of silicon dioxide films,
the silicon dioxide film is formed by processing a second mixed solution containing hydrogen peroxide through a wet process;
during processing, the oxidation rates of at least two of the silica films are different.
2. The wafer with protective layer according to claim 1, wherein the oxidation rate of the silicon oxide film is adjusted by adjusting the concentration of the hydrogen peroxide.
3. The wafer with protective layer according to claim 1 or 2, wherein at least two of the silicon oxide films are formed by alternately oxidizing different second mixed liquids.
4. A wafer with a protective layer according to any one of claim 1 to 3,
a first silicon dioxide film on the back surface (1) of the wafer is formed by oxidizing the second mixed liquid comprising sulfuric acid and hydrogen peroxide;
a second silica film formed by precipitation on the surface of the first silica film is formed of the second mixed liquid including ammonia and the hydrogen peroxide;
the first layer of silicon dioxide film and the second layer of silicon dioxide film have different densities.
5. Wafer with protection layer according to any of claims 1-4, characterized in that the arrangement of the hierarchy of protection layers (3) comprises:
the silicon dioxide film on the back surface (1) of the wafer is of a first layer structure;
as the level increases, the oxidation rate of the silicon oxide film becomes gradually smaller.
6. The wafer with protective layer according to any one of claims 1 to 5, wherein the oxidation rate of the silicon dioxide film is adjusted by:
The larger the proportion of the hydrogen peroxide in the second mixed solution is, the larger the thickness value of the silicon dioxide film is, and the faster the oxidation rate is.
7. The wafer of claim 1 to 6, wherein the second mixed solution is a mixed solution of ammonia water, hydrogen peroxide and water, or,
the second mixed solution is a mixed solution of sulfuric acid, the hydrogen peroxide and water.
8. The wafer with protective layer according to any one of claims 1 to 7, wherein the ratio of the ammonia water, the hydrogen peroxide, and the water in the second mixed liquid is 1:2: 50-1: 10:50.
9. a micro-processor for processing a wafer having a protective layer, characterized in that,
an early warning model is arranged in the micro processor;
under the condition that the room temperature is reduced or increased, the micro-processor acquires historical data of the thickness value of the protective layer (3) corresponding to the room temperature data and the proportioning data of the second mixed liquid;
when the early warning model judges that the historical data of the thickness value of the protective layer (3) is smaller than and not in the thickness standard range, the micro-processor sends out early warning signals of sound, light, electricity and combination thereof through an early warning component connected with the micro-processor;
The protective layer (3) comprises at least two layers of silicon dioxide films,
the silicon dioxide film is formed by processing the second mixed solution containing hydrogen peroxide through a wet process;
during processing, the oxidation rates of at least two of the silica films are different.
10. The microprocessor according to claim 9, wherein the microprocessor establishes a data connection with at least one temperature sensor that collects room temperature in a wired or wireless manner to receive the room temperature data;
the micro processor establishes a data connection relation with equipment for detecting the thickness of the protective layer (3) in a wired or wireless mode so as to receive the thickness data of the protective layer (3);
the micro processor learns historical data of room temperature, the proportion of the second mixed liquid and the thickness of the protective layer (3) based on a deep learning model or a neural network model, and establishes an association relation between the thickness (3) of the protective layer, the proportion of the second mixed liquid and the room temperature, so as to construct the early warning model.
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