CN117476799A - Germanium-silicon photodiode - Google Patents
Germanium-silicon photodiode Download PDFInfo
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- CN117476799A CN117476799A CN202311462456.5A CN202311462456A CN117476799A CN 117476799 A CN117476799 A CN 117476799A CN 202311462456 A CN202311462456 A CN 202311462456A CN 117476799 A CN117476799 A CN 117476799A
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 121
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 34
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000002210 silicon-based material Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 40
- 230000008569 process Effects 0.000 claims description 37
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910000676 Si alloy Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 25
- 230000031700 light absorption Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 23
- 238000005468 ion implantation Methods 0.000 description 13
- 238000005530 etching Methods 0.000 description 11
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 10
- 239000000969 carrier Substances 0.000 description 9
- 238000000137 annealing Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 230000005012 migration Effects 0.000 description 5
- 238000013508 migration Methods 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000001212 derivatisation Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H01L31/105—
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- H01L31/0288—
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- H01L31/035272—
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- Light Receiving Elements (AREA)
Abstract
The invention relates to a germanium-silicon photodiode, which comprises a first semiconductor region, a first doped region, a second semiconductor region, a second doped region, an insulating layer, an isolation region, a first electrode and a second electrode, which are positioned in the first semiconductor region, and a connecting region, wherein the first semiconductor region and the second semiconductor region are separated by the insulating layer, the connecting region also extends longitudinally and penetrates through the insulating layer positioned between the first semiconductor region and the second semiconductor region, and is used for connecting the first semiconductor region and the second semiconductor region, one of the first semiconductor region and the second semiconductor region adopts silicon materials, and the other adopts germanium materials. The invention prepares the germanium film with low dislocation density by using an aspect ratio limiting (ART) technology, and the obtained epitaxial germanium layer is used as a light absorption area to form a PIN type photodiode with low dislocation density together with a silicon substrate, so that dark current and the like of the device can be effectively reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and relates to a germanium-silicon photodiode.
Background
Ge materials have attracted considerable attention due to their higher electron and hole mobility, lower forbidden bandwidth, and matching of their lattice constants to III-V semiconductor materials than silicon materials. In recent years, ge materials are widely used in the near infrared photoelectric field, such as photoelectric detectors, light emitting devices and the like, due to good process compatibility with Si devices.
The conventional Ge-on-Si PD device is mainly divided into a vertical p-i-n structure and a transverse p-i-n structure, wherein in the preparation process, an epitaxial process is generally adopted to grow Ge on a Si substrate, however, a lattice mismatch degree of 4.2% exists between a Ge epitaxial layer and the Si substrate, and the quality of an epitaxial film is seriously affected by high-density dislocation generated by the lattice mismatch degree, so that the performance of the device is reduced (such as dark current of the device is increased, the responsivity is reduced, and the like).
To reduce the probability of dislocation derivatization, the Ge-on-Si heteroepitaxy may be performed using an aspect ratio trapping (Aspect Ratio Trapping, ART) technique, as shown in FIG. 1, sidewall SiO 2 The film will hinder migration of misfit dislocations, reducing the probability of dislocation derivatization. That is, the effect of dislocation defects on device performance can be effectively improved by using an ART process to fabricate a silicon germanium photovoltaic device. The existing photoelectric detector prepared by utilizing an ART process is of a transverse p-i-nPD structure, as shown in fig. 2, an effective light absorption region of the transverse structure is mainly concentrated between two doped regions and is far smaller than a PD device of a vertical structure with the same size, so that the responsivity of the photoelectric detector is slightly poorer than that of the PD device of the vertical structure, and the requirement of high-speed weak light signal detection is difficult to meet.
Disclosure of Invention
The present invention is directed to a silicon germanium photodiode that solves the above-mentioned problems associated with the prior Ge-on-Si PD designs.
The aim of the invention can be achieved by the following technical scheme:
a silicon germanium photodiode comprising a first semiconductor region, a first doped region located within the first semiconductor region, a second doped region located within the second semiconductor region, an insulating layer, an isolation region, a first electrode and a second electrode, and further comprising a connection region, wherein the first semiconductor region is separated from the second semiconductor region by the insulating layer, the connection region further extends longitudinally through the insulating layer located between the first semiconductor region and the second semiconductor region and connects the first semiconductor region and the second semiconductor region, one of the first semiconductor region and the second semiconductor region adopts a silicon material, and the other adopts a germanium material.
The invention innovatively adopts an ART process to prepare the Ge-on-Si PD with a vertical structure, and based on the connection problem of the absorption region and the multiplication region in the preparation process, the connection region is arranged to penetrate through the insulating layer between the first semiconductor region and the second semiconductor region and connect the first semiconductor region and the second semiconductor region, and the arrangement of the structures of the other functional regions, the position relationship and the connection relationship between the functional regions belong to the known technology or conventional technical means in the field.
Further, the first semiconductor region is made of silicon material; the second semiconductor region is made of germanium material and is prepared through an ART process.
Further, forming a plurality of trenches with a certain depth-to-width ratio on the silicon substrate, epitaxially growing a germanium film in the trenches until the germanium film is higher than the silicon substrate and reaches a specific thickness, then removing the dislocation-containing portion by a thinning process, wherein the thickness of the thinned silicon substrate (i.e., the first semiconductor region) is not more than 20 μm.
Or still further, the second semiconductor region is prepared by:
forming a plurality of grooves with a certain depth-to-width ratio on a silicon substrate, epitaxially growing a germanium film in the grooves until the whole grooves are filled with the germanium film, removing dislocation-containing parts by using a thinning process, depositing an insulating layer on the back surface of a first semiconductor region, and finally, stopping the epitaxy of the germanium film exposed on the back surface until the germanium film is higher than the silicon substrate and reaches a specific thickness, wherein the thickness of the thinned silicon substrate (namely the first semiconductor region) is not more than 20 mu m.
Further, the connecting areas are provided with one or a plurality of connecting areas, and when the connecting areas are provided with a plurality of connecting areas, different connecting areas are arranged at intervals in parallel.
Further, the width of the connecting region along the transverse direction is not less than 200nm;
the material used for the connection region is selected from silicon, germanium-silicon alloy or metal.
Further, the thickness of the first semiconductor region in the longitudinal direction is not more than 20 μm; the thickness of the second semiconductor region in the longitudinal direction is not less than 0.5 μm.
Further, the doping types of the first doping region and the second doping region are opposite.
Further, the second semiconductor region has sidewall regions on both sides in the lateral direction, and the sidewall regions include a third doped region therein.
Further, the doping type of the third doped region is the same as that of the second doped region.
Further, the first electrode and the second electrode are respectively connected with the first doped region and the second doped region.
Further, the isolation region extends longitudinally through the entire diode device.
Further, the isolation region is also electrically connected with the first electrode or/and the second electrode as a circuit connection layer.
Compared with the prior ART, the invention prepares the germanium film with low dislocation density by using the depth-to-width ratio limiting (Aspect Ratio Trapping, ART) technology, and the obtained epitaxial germanium layer is used as a light absorption area to form the PIN type photodiode with low dislocation density together with the silicon substrate, so that dark current and the like of the device can be effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a Ge-on-Si heteroepitaxy structure based on an ART process;
FIG. 2 is a schematic cross-sectional structure of a conventional ART process-based germanium-silicon photodiode device;
fig. 3 is a schematic cross-sectional view of a sige photodiode device according to embodiment 1 of the present invention;
FIG. 4 is a schematic flow chart of a first process for forming a second semiconductor region by ART process;
FIG. 5 is a flow chart of a second method for forming a second semiconductor region by ART process;
FIG. 6 is a schematic view of the attachment area when one is provided;
FIG. 7 is a schematic view of a plurality of connection areas;
FIG. 8 is a schematic flow chart of the preparation of a junction region;
FIG. 9 is a schematic view of a second semiconductor region portion;
FIG. 10 is a schematic flow chart of preparing a third doped region on the second semiconductor region;
FIG. 11 is a schematic diagram of an isolation region as a circuit connection layer;
the figure indicates:
1-first semiconductor region, 2-second semiconductor region, 3-first doped region, 4-dislocation, 5-second doped region, 6-insulating layer, 7-isolation region, 8-first electrode, 9-second electrode, 10-connection region, 11-third doped region.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed implementation manner and a specific operation process are given, but the protection scope of the present invention is not limited to the following examples.
In the following embodiments, unless otherwise specified, functional components or structures are shown as conventional components or structures adopted in the art to achieve the corresponding functions; likewise, unless otherwise indicated, treatment techniques are well known in the art.
In order to reduce dark current and the like of a device, the invention provides a germanium-silicon photodiode, which comprises a first semiconductor region 1, a first doped region 3, a second semiconductor region 2, a second doped region 5, an insulating layer 6, an isolation region 7, a first electrode 8 and a second electrode 9 which are positioned in the first semiconductor region 1, and a connecting region 10, wherein the first semiconductor region 1 and the second semiconductor region 2 are separated by the insulating layer 6, the connecting region 10 also extends longitudinally and penetrates through the insulating layer 6 positioned between the first semiconductor region 1 and the second semiconductor region 2, and connects the first semiconductor region 1 and the second semiconductor region 2, one of the first semiconductor region 1 and the second semiconductor region 2 adopts silicon material, and the other adopts germanium material.
In some embodiments, the second semiconductor region 2 is fabricated using an ART process, and generates photogenerated carriers as a light absorbing region, where the ART process is conventional in the ART.
Referring to fig. 4, in some more specific embodiments, the second semiconductor region 2 is prepared by:
forming a plurality of trenches with a certain depth-to-width ratio on a silicon substrate, and then depositing a layer of SiO on the surface of the silicon substrate 2 Post-etching SiO at the bottom of the trench 2 And epitaxially growing a germanium film in the groove until the germanium film is higher than the silicon substrate and reaches a specific thickness. SiO when Ge is grown in the groove in limited mode 2 The wall may hinder migration of misfit dislocations, so that dislocation defects in the thin film disappear at a certain thickness within the trench, and then a thinning process is used to remove the portion including dislocations 4, to reduce dark current in the device due to dislocations, wherein the thinned silicon substrate (i.e., first semiconductor region 1) is no more than 20 μm thick. Here, for example, a Chemical Mechanical Polishing (CMP) process may be selected as the thinning process, which is a conventional technology in the art and will not be described herein.
In some more specific embodiments, referring to fig. 5, the second semiconductor region 2 is further prepared by:
forming a plurality of trenches with a certain depth-to-width ratio on a silicon substrate, and then depositing a layer of SiO on the surface of the silicon substrate 2 Post-etching SiO at the bottom of the trench 2 Epitaxially growing a germanium film in the trench until the germanium film fills the entire trench, and when the Ge is grown in the trench in a limited manner, performing SiO 2 The wall will hinder migration of misfit dislocations and hence dislocation defects in the film disappear at a certain thickness in the trench, then a thinning process is used to remove the portion containing dislocations 4 and deposit an insulating layer 6 on the back side of the first semiconductor region 1, finally the back-exposed germanium film is re-epitaxially grown until it reaches a certain thickness above the silicon substrateAnd wherein the thinned silicon substrate (i.e., the first semiconductor region 1) has a thickness of not more than 20 μm. Here, for the thinning process, for example, a Chemical Mechanical Polishing (CMP) process may be selected, and the "back surface" herein refers to a surface exposed after the dislocation 4 is removed by the thinning process.
In the Ge-on-Si APD structure, the intrinsic germanium layer is the absorption region of the device for absorbing light and generating photogenerated carriers under the photoelectric effect, which enter the silicon under the action of an electric field to achieve efficient transport. As can be seen from fig. 4 and 5, an insulating layer 6 is present between the thin germanium film epitaxially grown by ART and the silicon substrate, and further, the two (i.e., the first semiconductor region 1 and the second semiconductor region 2) are separated by the insulating layer 6, so that carriers cannot smoothly move between the first semiconductor region 1 and the second semiconductor region 2. The invention thus also specifically designs the connection region 10 to penetrate the insulating layer 6 between the first semiconductor region 1 and the second semiconductor region 2, thereby connecting the two regions.
Referring again to fig. 6 and 7, in some embodiments, one or more of the connection regions 10 may be provided, and when a plurality of connection regions are provided, the different connection regions 10 may be arranged in parallel at intervals.
In some more specific embodiments, the width of the connection region 10 in the lateral direction is not less than 200nm. In addition, the depth of the connection region 10 in the longitudinal direction at least penetrates the insulating layer 6 to connect the first semiconductor region 1 and the second semiconductor region 2, the specific depth of which depends on the etching depth and may further extend downward on the basis of at least penetrating the insulating layer 6.
In some embodiments, referring to fig. 8, the fabrication process of the connection region 10 includes etching longitudinally along the second semiconductor region 2, and then depositing the material of the corresponding connection region 10 in the etched trench. Specifically, the material used for the connection region 10 is selected from silicon, germanium, a germanium-silicon alloy, or a metal. More specifically, first, a trench is formed by etching longitudinally along the middle region (i.e., the boundary region of the epitaxial thin film) of the second semiconductor region 2, the etching process is stopped while penetrating the insulating layer 6, and then a material such as a germanium-silicon alloy is epitaxially grown in the trench as the connection region 10.
In some embodiments, referring again to fig. 9, the second semiconductor region 2 may have a thickness of 0.5 μm or more in the longitudinal direction, where the thickness does not include the portion of the trench in the first semiconductor region 1 during formation of the second semiconductor region 2. The thickness of the second semiconductor region 2 depends on the wavelength of the probe light, and should be not less than the absorption depth of germanium in this band so as to sufficiently absorb the probe light.
In some embodiments, the doping type of the first doped region 3 is opposite to the doping type of the second doped region 5. The doped region can be realized by ion implantation or the like. Illustratively, the first doped region 3 is n-type ion implantation (e.g., phosphorus), the second doped region 5 is p-type ion implantation (e.g., boron), or the first doped region 3 is p-type ion implantation, the second doped region 5 is n-type ion implantation, and after ion implantation, the annealing treatment may be performed by a Rapid Thermal Annealing (RTA) or the like to activate the impurities, where typical rapid thermal annealing conditions are 5 seconds to 10 seconds at 1050 ℃ to 1100 ℃, and exemplary annealing conditions are about 7 seconds at 1050 ℃, and of course, the annealing conditions may be adjusted conventionally within the foregoing range according to actual needs.
Referring again to fig. 10, in some specific embodiments, the second semiconductor region 2 has opposite sidewall regions on both sides in the lateral direction, and the sidewall regions include the third doped region 11. More preferably, the third doped region 11 is also in contact with the second doped region 5. The third doped region 11 is used for regulating and controlling the electric field distribution of the second semiconductor region 2, so that the photo-generated carriers of the second semiconductor region 2 are accelerated into the first semiconductor region 1 under the action of the electric field and are collected by the second electrode 9 to generate an effective photocurrent.
In some more specific embodiments, the doping type of the third doped region 11 is the same as the second doped region 5. The third doped region 11 may be formed by sidewall ion implantation, after the second semiconductor region 2 is prepared, etching again at the trench position, and then implanting the same dopant as the second doped region 5 at the trench sidewall position to form the third doped region 11.
In some specific embodiments, the first electrode 8 and the second electrode 9 are connected to the first doped region 3 and the second doped region 5, respectively, and the first doped region 3 and the second doped region 5 are both highly doped regions for making ohmic contact with metal electrodes (i.e., the first electrode 8 and the second electrode 9), thereby being used for applying voltage and transmitting signals.
Referring to fig. 3, in some embodiments, the isolation region 7 extends longitudinally through the entire diode device, so as to reduce cross-talk between devices. Preferably, the material of the isolation region 7 may be silicon oxide, amorphous silicon, polysilicon or metal. More specifically, the isolation region 7 is prepared after the third doped region 11, and after ion implantation of the third doped region 11 is completed, a Ti/TiN layer is deposited as a transition layer, and then a metal tungsten or the like is grown in the trench by using CVD as an isolation filling material to form the isolation region 7.
Referring again to fig. 11, in some embodiments, the isolation region 7 is also electrically connected to the first electrode 8 and/or the second electrode 9 as a circuit connection layer, so that when a back electrode is present in the device, the electrode connection may be made through the metal of the isolation region 7.
The above embodiments may be implemented singly or in any combination of two or more.
The above embodiments are described in more detail below in connection with specific examples.
Example 1:
in order to reduce dislocation defects in epitaxial germanium and, at the same time, reduce dark current of the device, etc., the present embodiment provides a silicon germanium photodiode, which, as shown in fig. 3, includes a first semiconductor region 1, a first doped region 3 located in the first semiconductor region 1, a second semiconductor region 2, a second doped region 5 located in the second semiconductor region 2, an insulating layer 6, an isolation region 7, a first electrode 8 and a second electrode 9, and a connection region 10, wherein the first semiconductor region 1 and the second semiconductor region 2 are separated by the insulating layer 6, and the connection region 10 further extends longitudinally through the insulating layer 6 located between the first semiconductor region 1 and the second semiconductor region 2 and connects the first semiconductor region 1 and the second semiconductor region 2.
In this embodiment, the first semiconductor region 1 is made of a silicon material; the second semiconductor region 2 is made of germanium material, which is manufactured by ART (i.e. depth to width ratio limitation, aspect Ratio Trapping) process, and generates photo-generated carriers as a light absorbing region. Meanwhile, the doping types of the first doping region 3 and the second doping region 4 are opposite, and the doping type of the second doping region 5 and the second doping region 4 are the same. The doped region can be realized by ion implantation or the like. In this embodiment, the first doped region 3 is n-type ion implantation (e.g. phosphorus), the second doped region 4 and the second doped region 5 are p-type ion implantation (e.g. boron), and after the ion implantation is completed, annealing treatment such as Rapid Thermal Annealing (RTA) may be performed to activate the impurities, where the annealing condition is that the annealing lasts for about 7s at 1050 ℃.
Referring to fig. 4 again, the process of preparing the second semiconductor region 2 by ART in this embodiment is as follows: forming a plurality of trenches with a certain depth-to-width ratio on a silicon substrate as a first semiconductor region 1, and then depositing a layer of SiO on the surface of the silicon substrate 2 Post-etching SiO at the bottom of the trench 2 And epitaxially growing a germanium film in the groove until the germanium film is higher than the silicon substrate and reaches a specific thickness. SiO when Ge is grown in the groove in limited mode 2 The walls may impede migration of misfit dislocations, so dislocation defects in the film disappear at a certain thickness within the trench, and then a thinning process is used to remove the portion including dislocations 4 to reduce dark current in the device due to dislocations 4. Here, a Chemical Mechanical Polishing (CMP) process, for example, may be selected as the thinning process.
Meanwhile, the connection region 10 of the present embodiment is provided with one, as shown in fig. 6, and the width of the connection region 10 in the lateral direction is not less than 200nm. In addition, the depth of the connection region 10 in the longitudinal direction depends on the etching depth, which at least penetrates the insulating layer 6, but can also continue to extend downwards. In addition, the material used for the connection region 10 is selected from any one of silicon, germanium, a germanium-silicon alloy or a metal, and in this embodiment, a germanium-silicon alloy is selected.
Please refer to fig. 9 again, whereThickness t of the second semiconductor region 2 in the longitudinal direction 1 Not less than 0.5 μm, the thickness of the present embodiment is 0.5 μm, where the thickness does not include the trench portion located in the first semiconductor region 1 during formation of the second semiconductor region 2. The device of this embodiment is mainly applied to short-wave infrared detection, the second semiconductor region 2 generates photo-generated carriers for the light absorption region, and the thickness of the photo-generated carriers should not be smaller than the absorption depth of germanium in the band, so that the photo-generated carriers can fully absorb infrared light, that is, not smaller than 0.5 μm.
Referring to fig. 3 again, the first electrode 8 and the second electrode 9 are respectively connected to the first doped region 3 and the second doped region 5, and the first doped region 3 and the second doped region 5 are both highly doped regions for forming ohmic contact with metal electrodes (i.e. the first electrode 8 and the second electrode 9), thereby being used for applying voltage and transmitting signals.
Meanwhile, referring to fig. 3, etc., the isolation region 7 extends longitudinally through the entire diode device, so as to reduce cross-talk between devices. The material of the isolation region 7 in this embodiment is preferably silicon oxide.
Example 2:
unlike example 1, the specific process of growing the second semiconductor region 2 based on the ART process of this example is:
referring to FIG. 5, a plurality of trenches having a certain aspect ratio are formed on a silicon substrate as a first semiconductor region 1, and then a layer of SiO is deposited on the surface of the silicon substrate 2 Post-etching SiO at the bottom of the trench 2 Epitaxially growing a germanium film in the trench until the germanium film fills the entire trench, and when the Ge is grown in the trench in a limited manner, performing SiO 2 The wall blocks migration of misfit dislocations and dislocation defects in the film disappear at a certain thickness in the trench, then the portion containing dislocations 4 is removed using a thinning process and an insulating layer 6 is deposited on the back side of the first semiconductor region 1, and finally the back-exposed germanium film is re-epitaxial until it reaches a certain thickness above the silicon substrate. Wherein the thickness of the thinned silicon substrate is not more than 20 mu m. Here, for example, a Chemical Mechanical Polishing (CMP) process may be selected as the thinning process, wherein "backside" refers to the surface exposed after the dislocation 4 is removed by the thinning process。
Example 3:
unlike embodiment 1, in this embodiment, three connection regions 10 are provided, different connection regions 10 are arranged in parallel at intervals, and the width of a single connection region 10 in the lateral direction is not less than 200nm.
Example 4:
on the basis of embodiment 1, the second semiconductor region 2 of this embodiment has oppositely arranged sidewall regions on both sides in the lateral direction, which contain the third doped region 11 therein, the third doped region 11 also being in contact with the second doped region 5. The third doped region 11 is used for regulating and controlling the electric field distribution of the second semiconductor region 2, so that the photo-generated carriers of the second semiconductor region 2 are accelerated into the first semiconductor region 1 under the action of the electric field and are collected by the second electrode 9 to generate an effective photocurrent. In addition, it should be noted that the doping type of the third doped region 11 is the same as that of the second doped region 5.
Referring to fig. 10 again, the third doped region 11 may be formed by sidewall ion implantation, after the second semiconductor region 2 is prepared, etching again at the trench position, and then implanting the same dopant as the second doped region 5 at the trench sidewall position to form the third doped region 11.
Example 5:
referring again to fig. 11, unlike embodiment 1, the isolation region 7 of this embodiment is also electrically connected to the first electrode 8 or the second electrode 9 as a circuit connection layer, so that when the back electrode is present in the device, the electrode can be drawn out through the metal of the isolation region 7.
The previous description of the embodiments is provided to facilitate a person of ordinary skill in the art in order to make and use the present invention. It will be apparent to those skilled in the art that various modifications can be readily made to these embodiments and the generic principles described herein may be applied to other embodiments without the use of the inventive faculty. Therefore, the present invention is not limited to the above-described embodiments, and those skilled in the art, based on the present disclosure, should make improvements and modifications without departing from the scope of the present invention.
Claims (10)
1. A germanium-silicon photodiode, characterized in that the germanium-silicon photodiode comprises a first semiconductor region, a first doped region, a second semiconductor region, a second doped region, an insulating layer, an isolation region, a first electrode and a second electrode, which are positioned in the first semiconductor region, and a connecting region, wherein the first semiconductor region and the second semiconductor region are separated by the insulating layer, the connecting region also extends longitudinally and penetrates through the insulating layer positioned between the first semiconductor region and the second semiconductor region, and connects the first semiconductor region and the second semiconductor region, one of the first semiconductor region and the second semiconductor region adopts silicon material, and the other adopts germanium material.
2. A silicon germanium photodiode according to claim 1, wherein said first semiconductor region is formed of silicon material; the second semiconductor region is made of germanium material and is prepared through an ART process.
3. A silicon germanium photodiode according to claim 1, wherein the width of the connection region in the lateral direction is not less than 200nm;
the material used for the connection region is selected from silicon, germanium-silicon alloy or metal.
4. A silicon germanium photodiode according to claim 1, wherein the thickness of the first semiconductor region in the longitudinal direction is not more than 20 μm; the thickness of the second semiconductor region in the longitudinal direction is not less than 0.5 μm.
5. The silicon germanium photodiode of claim 1 wherein the first doped region is of opposite doping type than the second doped region.
6. A silicon germanium photodiode according to claim 1, wherein the second semiconductor region has sidewall regions on both sides in the lateral direction, the sidewall regions including a third doped region therein.
7. The silicon germanium photodiode of claim 6, wherein the doping type of said third doped region is the same as said second doped region.
8. A silicon germanium photodiode according to claim 1, wherein the first and second electrodes are connected to the first and second doped regions, respectively.
9. A silicon germanium photodiode according to claim 1, wherein said isolation region extends longitudinally through the entire diode device.
10. A silicon germanium photodiode according to claim 1, wherein the isolation region is further electrically connected to the first electrode or/and the second electrode as a circuit connection layer.
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| CN202311462456.5A CN117476799A (en) | 2023-11-06 | 2023-11-06 | Germanium-silicon photodiode |
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| CN202311462456.5A CN117476799A (en) | 2023-11-06 | 2023-11-06 | Germanium-silicon photodiode |
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