CN117438394B - GaN HEMT cascade device multi-layer sealing structure and preparation method thereof - Google Patents
GaN HEMT cascade device multi-layer sealing structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000007789 sealing Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 126
- 239000000853 adhesive Substances 0.000 claims description 57
- 230000001070 adhesive effect Effects 0.000 claims description 57
- 238000005538 encapsulation Methods 0.000 claims description 10
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 238000001746 injection moulding Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 17
- 239000000243 solution Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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Abstract
The invention relates to the technical field of semiconductors and discloses a GaN HEMT cascade device multi-layer sealing structure and a preparation method thereof, wherein the GaN HEMT cascade device multi-layer sealing structure comprises a GaN chip, a substrate and a MOS chip; the middle of the substrate is an insulating layer, and both the front surface and the back surface of the substrate are provided with conducting layers; the GaN chip is provided with a source window, and any point in the source window is configured as a source of the GaN chip; the substrate and the MOS chip are of a laminated structure, the laminated structure is arranged in the source window, and the size of the source window is larger than that of the laminated structure; the stacked structure is disposed on the source window and the configuration substrate and the MOS chip are electrically connected to the GaN chip, respectively, so that the source of the MOS chip is electrically connected to the gate of the GaN chip and the drain of the MOS chip is electrically connected to the source of the GaN chip. The GaN HEMT cascade device with smaller size and better performance can be obtained.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a GaN HEMT cascade device multi-layer sealing structure and a preparation method thereof.
Background
GaN is used as a third-generation semiconductor material, and the GaN material series has low heat generation rate and high breakdown electric field, has good heat dissipation performance, and is favorable for the device to work under high-power conditions. The GaN HEMT cascade device has large energy band gap, high peak saturated electron velocity, high concentration two-dimensional electron gas and higher electron mobility, so that the on-resistance of the device reaches a very low value, and the product of the low on-resistance Ron and the grid charge Qg, namely Ron×Qg, can obviously reduce the switching loss. Therefore, the GaN HEMT cascade device is widely applied to the fields of radio frequency, microwave, power switching power supplies and the like.
As shown in fig. 1, most of the current GaN HEMT cascade devices mainly use a 2D package structure of a parallel substrate 3 and a MOS chip 4 combined with a GaN chip 2, a small window is opened on an outer layer of the GaN chip 2 to expose a source electrode thereof, and the source electrode of the GaN chip 2 is connected with the substrate 3 by a bonding wire, and referring to fig. 1, the conventional planar structure needs to electrically connect each component by a plurality of WB bonding wires. The size, number and length of the WB-wire will affect the product key parameters Ron (Receive Optimization for Next), and the WB-wire will also bring additional parasitic inductance, resulting in reduced performance of the GaN HEMT cascade device.
Therefore, the structure of the existing GaN HEMT cascade device has at least the following disadvantages:
(1) The existing parallel 2D packaging structure ensures that the outline dimension of the GaN HEMT cascading device is relatively larger, so that the packaging cost is high and the use requirement of smaller dimension cannot be met;
(2) The existing GaN chip has smaller window, which is not beneficial to interconnection and intercommunication between devices;
(3) The existing GaN HEMT cascading device needs to be electrically connected through a plurality of WB bonding wires, so that the on-resistance Ron parameter of a product can be influenced, and meanwhile, extra parasitic inductance and the like can be brought in, so that the performance of the product is reduced.
The foregoing background is only for the purpose of illustrating the general principles and aspects of the present invention and is not necessarily the prior art to the present application or for the purpose of providing a technical teaching; the above background should not be used to assess the novelty and creativity of the present application without explicit evidence that the above-mentioned content has been disclosed prior to the filing date of the present application.
Disclosure of Invention
The invention aims to provide a GaN HEMT cascade device multi-layer sealing structure and a preparation method thereof, which can obtain a GaN HEMT cascade device with smaller size and better performance.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a GaN HEMT cascade device multi-layer sealing structure comprises a GaN chip, a substrate and a MOS chip; the middle of the substrate is an insulating layer, and both the front surface and the back surface of the substrate are provided with conducting layers;
the GaN chip is provided with a source window, and any point in the source window is configured as a source of the GaN chip;
the substrate and the MOS chip are of a laminated structure, and the method comprises the following steps: the MOS chip is arranged on the front surface of the substrate, the surface provided with the source electrode is in fit connection with the front surface of the substrate, and then the laminated structure is formed, or the substrate is arranged on the MOS chip, and the back surface of the substrate is in fit connection with the surface where the source electrode of the MOS chip is located, and then the laminated structure is formed; the stacked structure is disposed within the source window, and a size of the source window is larger than a size of the stacked structure, the size of the stacked structure being defined as a projected area of the substrate and the MOS chip;
the stacked structure is arranged on the source window and is used for configuring the substrate and the MOS chip to be respectively and electrically connected with the GaN chip, so that the source electrode of the MOS chip is electrically connected with the grid electrode of the GaN chip, and the drain electrode of the MOS chip is electrically connected with the source electrode of the GaN chip.
Further, the combination of any one or more of the foregoing aspects, further comprising a lead frame base island, on which a gate, a drain, and a source of the GaN HEMT cascade device are disposed, and a conductive region configured to be electrically connected to the source of the GaN HEMT cascade device;
the GaN chip is arranged on the lead frame base island, the surface, opposite to the surface where the source window is located, of the GaN chip is connected with the lead frame base island in a bonding mode, and the grid electrode of the GaN chip is electrically connected with the conductive area.
Further, according to any one or a combination of the foregoing technical solutions, a gate, a source, and a drain of the GaN chip are all disposed on a surface where the source window is located, and the gate of the GaN chip is electrically connected to the conductive region by means of a bonding wire; or,
the source electrode and the drain electrode of the GaN chip are arranged on the surface of the source electrode window, the grid electrode of the GaN chip is arranged on the surface opposite to the surface of the source electrode window, and the grid electrode of the GaN chip is electrically connected with the conductive area through conductive adhesive.
Further, in any one or a combination of the foregoing embodiments, the MOS chip is disposed on a front surface of the substrate, and a surface on which the source is disposed is attached to the front surface of the substrate, so as to form the stacked structure;
the front surface of the substrate is provided with a first conductive layer, the source electrode of the MOS chip is electrically connected with the first conductive layer, and the first conductive layer is further configured to be electrically connected with the conductive region;
the back of the substrate is in fit connection with the source window, and a second conductive layer is arranged on the back of the substrate and is configured to be electrically connected with the source of the GaN chip.
Further, in any one or a combination of the foregoing, a drain of the MOS chip is configured to be electrically connected to the source window by way of a bonding wire; and/or the number of the groups of groups,
the first conductive layer is connected with the source electrode of the MOS chip in an adhesive mode through conductive adhesive and is electrically connected with the conductive area through a bonding wire mode; and/or the number of the groups of groups,
the second conductive layer is connected with the source electrode of the GaN chip through conductive adhesive in an adhesive mode; and/or the number of the groups of groups,
the grid electrode of the MOS chip is electrically connected with the grid electrode of the GaN HEMT cascade device in a bonding wire mode, the drain electrode of the GaN chip is arranged on the surface where the source electrode window is located, and the drain electrode of the GaN chip is electrically connected with the drain electrode of the GaN HEMT cascade device in a bonding wire mode.
Further, in any one or a combination of the foregoing aspects, the MOS chip is an LDMOS chip.
Further, in any one or a combination of the foregoing technical solutions, the substrate is disposed on the MOS chip, and the back surface of the substrate is attached to the surface where the source of the MOS chip is located, so as to form the stacked structure;
a third conductive layer is arranged on the back surface of the substrate and is electrically connected with the source electrode of the MOS chip;
the MOS chip is arranged on the source window, and the surface of the MOS chip provided with the drain electrode is in fit connection with the source window, so that the drain electrode of the MOS chip is electrically connected with the source electrode of the GaN chip;
and the front surface of the substrate is provided with a fourth conductive layer, and the fourth conductive layer is electrically connected with the source window.
Further, carrying out any one or a combination of the foregoing aspects, wherein the fourth conductive layer is electrically connected to the source window by way of a bonding wire; and/or the number of the groups of groups,
the drain electrode of the MOS chip is connected with the source electrode window through conductive adhesive in an adhesive mode; and/or the number of the groups of groups,
the third conductive layer is electrically connected with the source electrode of the MOS chip through conductive adhesive; and/or the number of the groups of groups,
the grid electrode of the MOS chip is electrically connected with the grid electrode of the GaN HEMT cascade device in a bonding wire mode, the drain electrode of the GaN chip is arranged on the surface where the source electrode window is located, and the drain electrode of the GaN chip is electrically connected with the drain electrode of the GaN HEMT cascade device in a bonding wire mode.
Further, any one or a combination of the foregoing technical solutions, the MOS chip is a VDMOS chip.
Further, in the foregoing any one or combination of the foregoing aspects, a source of the MOS chip is configured as a source of the cascade-type device, and a gate thereof is configured as a gate of the cascade-type device;
the drain of the GaN chip is configured as the drain of the tandem device.
According to another aspect of the invention, the invention provides a preparation method of a GaN HEMT cascade device multi-layer sealing structure, which comprises the following steps:
the MOS chip is arranged on the front surface of the substrate, and the source electrode of the MOS chip is connected with the first conductive layer on the front surface of the substrate in an adhesive mode and is electrically connected with the first conductive layer through conductive adhesive, so that a laminated structure of the MOS chip and the substrate is formed;
a source window is arranged on the front surface of the GaN chip, any point in the source window is configured as a source electrode of the GaN chip, and the size of the source window is larger than that of the laminated structure;
arranging the substrate in the source window, and bonding and connecting the second conductive layer on the back of the substrate with the source window through conductive adhesive, so that the second conductive layer on the back of the substrate is electrically connected with the source of the GaN chip;
the back of the GaN chip is provided with a grid electrode, the back of the GaN chip is connected with a lead frame base island in a bonding mode, and the grid electrode of the GaN chip is connected with a conductive area on the lead frame base island in an adhesive mode through conductive adhesive;
electrically connecting the first conductive layer on the front surface of the substrate with the conductive region by means of bonding wires;
electrically connecting the drain electrode of the MOS chip with the source electrode window in a bonding wire mode, wherein the surface of the drain electrode of the MOS chip is opposite to the surface of the source electrode of the MOS chip;
and electrically connecting the grid electrode of the MOS chip with the grid electrode on the lead frame base island in a wire bonding mode, and electrically connecting the drain electrode on the front side of the GaN chip with the drain electrode on the lead frame base island in a wire bonding mode.
According to another aspect of the invention, the invention provides a preparation method of a GaN HEMT cascade device multi-layer sealing structure, which comprises the following steps:
the MOS chip is arranged on the back surface of the substrate, and the source electrode of the MOS chip is bonded and connected with the third conductive layer on the back surface of the substrate through conductive adhesive, so that a laminated structure of the MOS chip and the substrate is formed;
a source window is arranged on the front surface of the GaN chip, any point in the source window is configured as a source electrode of the GaN chip, and the size of the source window is larger than that of the laminated structure;
arranging the MOS chip in the source window, attaching the surface of the MOS chip provided with the drain electrode to the source window, and bonding and electrically connecting the drain electrode of the MOS chip with the source window through conductive adhesive;
the back of the GaN chip is provided with a grid electrode, the back of the GaN chip is connected with a lead frame base island in a bonding mode, the grid electrode of the GaN chip is connected with a conductive area on the lead frame base island in an adhesive mode through conductive adhesive, and the conductive area is configured to be electrically connected with a source electrode of the GaN HEMT cascading device;
electrically connecting the fourth conductive layer on the front surface of the substrate with the source window in a bonding wire mode;
electrically connecting the source electrode of the MOS chip with the conductive region in a bonding wire mode, wherein the surface of the source electrode of the MOS chip is opposite to the surface of the grid electrode of the MOS chip;
and electrically connecting the grid electrode of the MOS chip with the grid electrode on the lead frame base island in a wire bonding mode, and electrically connecting the drain electrode of the GaN chip with the drain electrode on the lead frame base island in a wire bonding mode.
Further, any one or a combination of the foregoing technical solutions, the preparation method further includes: and packaging the integrated structure of the GaN chip, the substrate, the MOS chip and the lead frame base island which are electrically connected by adopting a mould injection molding process.
The technical scheme provided by the invention has the following beneficial effects:
a. according to the GaN HEMT cascade device with the 3D structure, the source window with the larger size is arranged on the GaN chip, the laminated structure of the substrate and the MOS chip is arranged on the source window, so that the GaN HEMT cascade device with the 3D structure is obtained, the packaging size of the GaN HEMT cascade device can be effectively reduced, the application requirement of smaller size is further met, the devices are connected more simply, the reference of WB bonding wires can be reduced, the negative influence of the WB bonding wires on the product performance is reduced, and the product performance is further improved;
b. according to the invention, the substrate and the LDMOS chip are sequentially stacked on the source window of the GaN chip, the source of the LDMOS chip is attached to the front surface of the substrate, the front surface and the back surface of the substrate are respectively provided with the first conductive layer and the second conductive layer, and 1 lead wire is bonded from the drain of the LDMOS chip to the source interconnection of the GaN chip to form a Cx capacitor, so that the dynamic capacitance matching performance of a product can be improved, and the MOS device is ensured not to generate avalanche in the switching process of the device;
c. according to the invention, the back surface of the substrate is attached to the source electrode of the VDMOS chip, the drain end of the VDMOS chip is attached to the source electrode of the GaN chip, the front surface and the back surface of the substrate are respectively provided with the third conductive layer and the fourth conductive layer, and the Cx capacitor is formed by bonding 1 lead wire from the front surface of the substrate to the source electrode interconnection of the GaN chip, so that the dynamic capacitance matching performance of a product can be improved, and the MOS device is ensured not to generate avalanche in the switching process.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a GaN HEMT cascade device with a 2D structure in the prior art;
fig. 2 is a schematic structural diagram of a GaN HEMT cascade device with a first 3D structure according to an exemplary embodiment of the present invention;
fig. 3 is a schematic structural diagram of a GaN HEMT cascade device with a second 3D structure according to an exemplary embodiment of the present invention.
Wherein, the reference numerals include: 1-lead frame base island, 2-GaN chip, 3-substrate, 4-MOS chip, 5-source window, 11-first WB bonding wire, 12-second WB bonding wire, 13-third WB bonding wire, 14-fourth WB bonding wire, 15-fifth WB bonding wire.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or device.
In one embodiment of the present invention, a GaN HEMT cascade device multi-layer encapsulation structure is provided, referring to fig. 2 and 3, including a GaN chip 2, a substrate 3, and a MOS chip 4; wherein, the middle of the base plate 3 is an insulating layer, and both the front and back surfaces of the base plate are provided with conductive layers;
a source window 5 is arranged on the GaN chip 2, and any point in the source window 5 is configured as a source of the GaN chip 2;
the substrate 3 and the MOS chip 4 are of a laminated structure, including: the MOS chip 4 is disposed on the front surface of the substrate 3, and the surface on which the source is disposed is bonded to the front surface of the substrate 3, so as to form the laminated structure, or the substrate 3 is disposed on the MOS chip 4, and the back surface of the substrate 3 is bonded to the surface on which the source of the MOS chip 4 is disposed, so as to form the laminated structure; the laminated structure is provided within the source window 5, and the size of the source window 5 is larger than the size of the laminated structure, which is defined as the projected area of the substrate 3 and the MOS chip 4;
by disposing the stacked structure on the source window 5 and configuring the substrate 3 and the MOS chip 4 to be electrically connected to the GaN chip 2, respectively, the source of the MOS chip 4 is electrically connected to the gate of the GaN chip 2, and the drain of the MOS chip 4 is electrically connected to the source of the GaN chip 2.
According to the GaN HEMT cascade device with the 3D structure, the source window with the larger size is arranged on the GaN chip, and the laminated structure of the substrate and the MOS chip is overlapped on the source window, so that the GaN HEMT cascade device with the 3D structure is obtained.
In this embodiment, the source of the MOS chip 4 is configured as the source of the GaN HEMT cascade device, and the gate thereof is configured as the gate of the GaN HEMT cascade device; the drain electrode of the GaN chip 2 is configured as the drain electrode of the GaN HEMT cascade type device.
Specifically, the GaN HEMT cascade device further includes a lead frame base 1, and the lead frame base 1 is provided with a gate, a drain and a source of the GaN HEMT cascade device, and a conductive region configured to be electrically connected with the source of the GaN HEMT cascade device. Preferably, the size of the conductive region is larger than the size of the GaN chip 2. The GaN chip 2 is arranged on the lead frame base island 1, the surface of the GaN chip 2 opposite to the surface where the source window 5 is arranged is attached to the lead frame base island 1, and the grid electrode of the GaN chip 2 is electrically connected with the conductive region. For example, if the source window is disposed on the front surface of the GaN chip 2, the back surface of the GaN chip 2 is bonded to the conductive region. Referring to fig. 2, a dashed box illustrates the source window 5, where the surface of the source window 5 is the front surface of the GaN chip 2. In this embodiment, the front surface is a surface visible in fig. 2 and 3, and the surfaces not visible in fig. 2 and 3 are opposite surfaces.
Typically, the gate, source, drain and source window 5 of the GaN chip 2 are disposed on the same surface of the GaN chip. As shown in fig. 2, the surface of the dashed-line frame is the front surface of the GaN chip 2, and the gate, the source and the drain of the GaN chip 2 are all disposed on the front surface of the GaN chip but the etching depths of the three may be different. In one embodiment of the present invention, the back surface of the GaN chip 2 is stuck on the lead frame island 1 by glue, and the gate electrode of the GaN chip 2 is electrically connected to the conductive region by means of bonding wires. As shown in fig. 2 and 3, the gate of the GaN chip 2 is electrically connected to the conductive region by a first WB-wire 11. In another embodiment of the present invention, the gate of the GaN chip 2 is led to the back surface thereof; or, for the GaN chip in which the source and the drain are disposed on the surface of the source window 5 and the gate is disposed on the surface opposite to the surface of the source window 5, that is, for the GaN chip in which the source, the drain and the source window 5 are disposed on the front and the gate is disposed on the back, the gate on the back of the GaN chip 2 is bonded to the conductive region through the conductive adhesive, so that the first WB bonding wire 11 shown in fig. 2 and 3 is avoided, and the performance of the GaN HEMT cascade device is improved.
In one embodiment of the present invention, the MOS chip is an LDMOS chip. In this embodiment, referring to fig. 2, the substrate 3 and the source window 5 in the laminated structure are bonded to each other, that is, the substrate 3 and the MOS chip 4 are sequentially stacked on the source window. Specifically, the MOS chip 4 is disposed on the front surface of the substrate 3, and the surface on which the source is disposed is bonded to the front surface of the substrate 3, thereby forming the laminated structure. The front surface of the substrate 3 is provided with a first conductive layer, to which the source of the MOS chip 4 is electrically connected, the first conductive layer being further configured to be electrically connected to the conductive region. The back surface of the substrate 3 is bonded to the source window 5, and a second conductive layer is disposed on the back surface of the substrate 3, and the second conductive layer is configured to be electrically connected to the source of the GaN chip 2. The first conductive layer and the second conductive layer are preferably silver plating layers.
In the present embodiment, the drain of the MOS chip 4 is configured to be electrically connected to the source window 5 through the second WB-wire 12. The first conductive layer is in adhesive connection with the source electrode of the MOS chip 4 through conductive adhesive and is electrically connected with the conductive region through a third WB bonding wire 13; the second conductive layer is connected with the source electrode of the GaN chip 2 through conductive adhesive in an adhesive mode. The conductive component of the conductive adhesive is silver. The gate of the MOS chip 4 is electrically connected to the gate of the GaN HEMT cascade device through a fourth WB bonding wire 14, the drain of the GaN chip 2 is disposed on the surface of the source window 5, and the drain of the GaN chip 2 is electrically connected to the drain of the GaN HEMT cascade device through a fifth WB bonding wire 15.
In the technical field, as the position change of the GaN chip and the MOS chip easily causes the mismatch of dynamic capacitance of the GaN HEMT cascade device, the MOS device can be in avalanche in the switching process; and curing the size of the opening on the GaN chip, the adoption of a parallel 2D package structure for the device is almost the technical prejudice for those skilled in the art, and it is difficult for those skilled in the art to think that the 3D stacked structure is realized by opening a source window on the GaN chip, which has a size larger than the stacked structure of the substrate and the MOS chip. According to the invention, the first conductive layer and the second conductive layer are respectively arranged on the front surface and the back surface of the substrate, and 1 lead wire (the second WB bonding lead wire 12 shown in fig. 2) is bonded from the drain electrode of the LDMOS chip to the source electrode of the GaN chip to form the Cx capacitor, so that the dynamic capacitance matching performance of a product can be improved, and the MOS device is ensured not to generate avalanche in the switching process of the device.
In another embodiment of the present invention, the MOS chip 4 is a VDMOS chip. In this embodiment, referring to fig. 3, the MOS chip 4 and the source window 5 in the laminated structure are bonded to each other, that is, the MOS chip 4 and the substrate 3 are stacked in sequence on the source window. Specifically, the substrate 3 is disposed on the MOS chip 4, and the back surface of the substrate 3 is bonded to the surface where the source of the MOS chip 4 is located, so as to form the laminated structure. A third conductive layer is disposed on the back surface of the substrate 3, and the third conductive layer is electrically connected to the source electrode of the MOS chip 4. The MOS chip 4 is disposed on the source window 5, and a surface of the MOS chip 4 on which the drain thereof is disposed is bonded to the source window 5, so that the drain of the MOS chip 4 is electrically connected to the source of the GaN chip 2. A fourth conductive layer is disposed on the front surface of the substrate 3, and the fourth conductive layer is electrically connected to the source window 5. The third conductive layer and the fourth conductive layer are preferably silver plating layers.
In this embodiment, the fourth conductive layer is electrically connected to the source window 5 through a second WB-wire 12. The drain electrode of the MOS chip 4 is bonded to the source window 5 by a conductive adhesive, and the source electrode thereof is electrically connected to the conductive region by a third WB bonding wire 13. The third conductive layer is electrically connected with the source electrode of the MOS chip 4 through conductive adhesive. The gate of the MOS chip 4 is electrically connected to the gate of the GaN HEMT cascade device by means of a fourth WB bonding wire 14, the drain of the GaN chip 2 is disposed on the surface of the source window 5, and the drain of the GaN chip 2 is electrically connected to the drain of the GaN HEMT cascade device by means of a fifth WB bonding wire 15.
In this embodiment, the back surface of the substrate 3 is attached to the source electrode of the MOS chip 4, the drain end of the MOS chip 4 is attached to the source electrode of the GaN chip, and a Cx capacitor is formed by bonding 1 wire (the second WB bonding wire 12 shown in fig. 3) from the front surface of the substrate 3 to the source electrode of the GaN chip, so that the dynamic capacitance matching performance of the product can be improved, and the MOS device is ensured not to generate avalanche in the switching process.
In one embodiment of the invention, a preparation method of a GaN HEMT cascade device multi-layer sealing structure is provided, comprising the following steps:
the LDMOS chip is arranged on the front side of the substrate, and the source electrode of the LDMOS chip is connected with the first conductive layer on the front side of the substrate in an adhesive mode and is electrically connected with the first conductive layer through conductive adhesive, so that a laminated structure of the LDMOS chip and the substrate is formed;
a source window is arranged on the front surface of the GaN chip, any point in the source window is configured as a source electrode of the GaN chip, and the size of the source window is larger than that of the laminated structure;
arranging the substrate in the source window, and bonding and connecting the second conductive layer on the back of the substrate with the source window through conductive adhesive, so that the second conductive layer on the back of the substrate is electrically connected with the source of the GaN chip;
the back of the GaN chip is provided with a grid electrode, the back of the GaN chip is connected with a lead frame base island in a bonding mode, and the grid electrode of the GaN chip is connected with a conductive area on the lead frame base island in an adhesive mode through conductive adhesive;
electrically connecting the first conductive layer on the front surface of the substrate with the conductive region by means of bonding wires;
electrically connecting the drain electrode of the LDMOS chip with the source electrode window in a bonding wire mode, wherein the surface of the drain electrode of the LDMOS chip is opposite to the surface of the source electrode of the LDMOS chip;
the grid electrode of the LDMOS chip is electrically connected with the grid electrode on the lead frame base island in a wire bonding mode, and the drain electrode on the front surface of the GaN chip is electrically connected with the drain electrode on the lead frame base island in a wire bonding mode;
and packaging the integrated structure of the GaN chip, the substrate, the LDMOS chip and the lead frame base island which are electrically connected by adopting a die injection molding process.
It should be noted that, the present invention is not limited to the order of the specific implementation steps of the preparation method, and the order of the specific implementation steps of the preparation method may be adjusted according to the needs, and each step may also be adjusted appropriately, so as to prepare the multi-layer sealing structure of the GaN HEMT cascade device described in any embodiment. For example, in one embodiment of the present invention, a source window is first disposed on the front surface of the GaN chip, any point in the source window is configured as a source of the GaN chip, and the size of the source window is larger than the size of the stacked structure; the LDMOS chip is arranged on the front side of the substrate, and the source electrode of the LDMOS chip is bonded and connected with the first conductive layer on the front side of the substrate through conductive adhesive, so that a laminated structure of the LDMOS chip and the substrate is formed; then arranging the substrate in the source window, and bonding and connecting a second conductive layer on the back of the substrate with the source window through conductive adhesive; and then further steps are performed. In another embodiment of the present invention, a source window is first disposed on the front surface of the GaN chip, any point in the source window is configured as a source of the GaN chip, and the size of the source window is larger than the size of the stacked structure; setting the substrate in the source window, and bonding and connecting the second conductive layer on the back of the substrate with the source window through conductive adhesive; then arranging the LDMOS chip on the front surface of the substrate, and bonding and connecting a source electrode of the LDMOS chip with a first conductive layer on the front surface of the substrate through conductive adhesive; and then further steps are performed.
In another embodiment of the present invention, a method for manufacturing a GaN HEMT cascade device multi-layer encapsulation structure is provided, including the following steps:
the VDMOS chip is arranged on the back surface of the substrate, and the source electrode of the VDMOS chip is bonded and connected with the third conductive layer on the back surface of the substrate through conductive adhesive, so that a laminated structure of the VDMOS chip and the substrate is formed;
a source window is arranged on the front surface of the GaN chip, any point in the source window is configured as a source electrode of the GaN chip, and the size of the source window is larger than that of the laminated structure;
arranging a VDMOS chip in the source window, attaching the surface of the VDMOS chip provided with the drain electrode to the source window, and bonding and electrically connecting the drain electrode of the VDMOS chip with the source window through conductive adhesive;
the back of the GaN chip is provided with a grid electrode, the back of the GaN chip is connected with a lead frame base island in a bonding mode, the grid electrode of the GaN chip is connected with a conductive area on the lead frame base island in an adhesive mode through conductive adhesive, and the conductive area is configured to be electrically connected with a source electrode of the GaN HEMT cascading device;
electrically connecting the fourth conductive layer on the front surface of the substrate with the source window in a bonding wire mode;
electrically connecting a source electrode of the VDMOS chip with the conductive region in a bonding wire mode, wherein the surface of the source electrode of the VDMOS chip is opposite to the surface of the grid electrode of the VDMOS chip;
the grid electrode of the VDMOS chip is electrically connected with the grid electrode on the lead frame base island in a wire bonding mode, and the drain electrode of the GaN chip is electrically connected with the drain electrode on the lead frame base island in a wire bonding mode;
and packaging the integrated structure of the GaN chip, the substrate, the VDMOS chip and the lead frame base island which are electrically connected by adopting a die injection molding process.
Also, the order of the specific implementation steps of the preparation method is not limited, and the order of the specific implementation steps of the preparation method can be adjusted according to the requirement, and each step can be adjusted appropriately, so as to prepare the GaN HEMT cascade device multi-layer encapsulation structure described in any embodiment. For example, in one embodiment of the present invention, a source window is first disposed on the front side of the GaN chip, then the substrate is disposed in the source window, and the second conductive layer on the back side of the substrate is bonded to the source window through the conductive adhesive, then the VDMOS chip is disposed on the front side of the substrate, and the source of the VDMOS chip is bonded to the first conductive layer on the front side of the substrate through the conductive adhesive; after which other steps are performed.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely exemplary of the application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the application and are intended to be comprehended within the scope of the application.
Claims (13)
1. The multi-layer laminated structure of the GaN HEMT cascade device is characterized by comprising a GaN chip (2), a substrate (3) and a MOS chip (4); wherein, the middle of the base plate (3) is an insulating layer, and both the front and back surfaces of the base plate are provided with conducting layers;
the GaN chip (2) is provided with a source window (5), and any point in the source window (5) is configured as a source electrode of the GaN chip (2);
the substrate (3) and the MOS chip (4) are of a laminated structure, and comprise: the MOS chip (4) is arranged on the front surface of the substrate (3), the surface provided with the source electrode is in fit connection with the front surface of the substrate (3) to form the laminated structure, or the substrate (3) is arranged on the MOS chip (4), and the back surface of the substrate (3) is in fit connection with the surface of the source electrode of the MOS chip (4) to form the laminated structure; the laminated structure is arranged in the source window (5), and the size of the source window (5) is larger than that of the laminated structure, and the size of the laminated structure is defined as the projection area of the substrate (3) and the MOS chip (4);
the stacked structure is arranged on the source window (5) and is used for configuring the substrate (3) and the MOS chip (4) to be respectively and electrically connected with the GaN chip (2), so that the source electrode of the MOS chip (4) is electrically connected with the grid electrode of the GaN chip (2), and the drain electrode of the MOS chip (4) is electrically connected with the source electrode of the GaN chip (2).
2. The GaN HEMT cascade device multi-layer encapsulation structure of claim 1, further comprising a lead frame base island (1), the lead frame base island (1) having a gate, a drain, and a source of the GaN HEMT cascade device disposed thereon, and a conductive region configured to electrically connect with the source of the GaN HEMT cascade device;
the GaN chip (2) is arranged on the lead frame base island (1), the surface, opposite to the surface where the source window (5) is arranged, of the GaN chip (2) is connected with the lead frame base island (1) in a bonding mode, and the grid electrode of the GaN chip (2) is electrically connected with the conductive area.
3. The GaN HEMT cascade device multi-layer encapsulation structure according to claim 2, wherein the gate, the source and the drain of the GaN chip (2) are all disposed on the surface of the source window (5), and the gate of the GaN chip (2) is electrically connected with the conductive region by means of a bonding wire; or,
the source electrode and the drain electrode of the GaN chip (2) are arranged on the surface of the source electrode window (5), the grid electrode of the GaN chip is arranged on the surface opposite to the surface of the source electrode window (5), and the grid electrode of the GaN chip (2) is electrically connected with the conductive area through conductive adhesive.
4. The GaN HEMT cascade device multi-layer sealing structure according to claim 2, wherein the MOS chip (4) is disposed on the front surface of the substrate (3), and the surface on which the source is disposed is bonded to the front surface of the substrate (3), so as to form the laminated structure;
the front surface of the substrate (3) is provided with a first conductive layer, and the source electrode of the MOS chip (4) is electrically connected with the first conductive layer, and the first conductive layer is further configured to be electrically connected with the conductive region;
the back surface of the substrate (3) is in bonding connection with the source window (5), and a second conductive layer is arranged on the back surface of the substrate (3) and is configured to be electrically connected with the source of the GaN chip (2).
5. The GaN HEMT cascade device multi-layer encapsulation structure of claim 4, wherein the drain of the MOS chip (4) is configured to be electrically connected to the source window (5) by means of a bonding wire; and/or the number of the groups of groups,
the first conductive layer is connected with the source electrode of the MOS chip (4) through conductive adhesive in an adhesive mode and is electrically connected with the conductive area through a bonding wire mode; and/or the number of the groups of groups,
the second conductive layer is connected with the source electrode of the GaN chip (2) through conductive adhesive in an adhesive mode; and/or the number of the groups of groups,
the grid electrode of the MOS chip (4) is electrically connected with the grid electrode of the GaN HEMT cascade device in a bonding wire mode, the drain electrode of the GaN chip (2) is arranged on the surface of the source window (5), and the drain electrode of the GaN chip (2) is electrically connected with the drain electrode of the GaN HEMT cascade device in a bonding wire mode.
6. The GaN HEMT cascade device multi-layer encapsulation structure of claim 5, wherein the MOS chip (4) is an LDMOS chip.
7. The GaN HEMT cascade device multi-layer sealing structure according to claim 2, wherein the substrate (3) is arranged on the MOS chip (4), and the back surface of the substrate (3) is bonded with the surface of the source electrode of the MOS chip (4), so as to form the laminated structure;
a third conductive layer is arranged on the back surface of the substrate (3), and the third conductive layer is electrically connected with the source electrode of the MOS chip (4);
the MOS chip (4) is arranged on the source window (5), and the surface of the MOS chip (4) provided with the drain electrode is in fit connection with the source window (5), so that the drain electrode of the MOS chip (4) is electrically connected with the source electrode of the GaN chip (2);
the front surface of the substrate (3) is provided with a fourth conductive layer, and the fourth conductive layer is electrically connected with the source window (5).
8. The GaN HEMT cascade device multi-layer encapsulation structure of claim 7, wherein the fourth conductive layer is electrically connected to the source window (5) by means of a bonding wire; and/or the number of the groups of groups,
the drain electrode of the MOS chip (4) is connected with the source electrode window (5) through conductive adhesive in an adhesive mode; and/or the number of the groups of groups,
the third conductive layer is electrically connected with the source electrode of the MOS chip (4) through conductive adhesive; and/or the number of the groups of groups,
the grid electrode of the MOS chip (4) is electrically connected with the grid electrode of the GaN HEMT cascade device in a bonding wire mode, the drain electrode of the GaN chip (2) is arranged on the surface of the source window (5), and the drain electrode of the GaN chip (2) is electrically connected with the drain electrode of the GaN HEMT cascade device in a bonding wire mode.
9. The GaN HEMT cascade device multi-layer encapsulation structure of claim 8, wherein the MOS chip (4) is a VDMOS chip.
10. The GaN HEMT cascade device multi-layer encapsulation structure of claim 1, wherein the source of the MOS chip (4) is configured as the source of the cascade device and the gate thereof is configured as the gate of the cascade device;
the drain of the GaN chip (2) is configured as the drain of the tandem device.
11. The preparation method of the GaN HEMT cascade device multi-layer sealing structure is characterized by comprising the following steps of:
the MOS chip is arranged on the front surface of the substrate, and the source electrode of the MOS chip is connected with the first conductive layer on the front surface of the substrate in an adhesive mode and is electrically connected with the first conductive layer through conductive adhesive, so that a laminated structure of the MOS chip and the substrate is formed;
a source window is arranged on the front surface of the GaN chip, any point in the source window is configured as a source electrode of the GaN chip, and the size of the source window is larger than that of the laminated structure;
arranging the substrate in the source window, and bonding and connecting the second conductive layer on the back of the substrate with the source window through conductive adhesive, so that the second conductive layer on the back of the substrate is electrically connected with the source of the GaN chip;
the back of the GaN chip is provided with a grid electrode, the back of the GaN chip is connected with a lead frame base island in a bonding mode, and the grid electrode of the GaN chip is connected with a conductive area on the lead frame base island in an adhesive mode through conductive adhesive;
electrically connecting the first conductive layer on the front surface of the substrate with the conductive region by means of bonding wires;
electrically connecting the drain electrode of the MOS chip with the source electrode window in a bonding wire mode, wherein the surface of the drain electrode of the MOS chip is opposite to the surface of the source electrode of the MOS chip;
and electrically connecting the grid electrode of the MOS chip with the grid electrode on the lead frame base island in a wire bonding mode, and electrically connecting the drain electrode on the front side of the GaN chip with the drain electrode on the lead frame base island in a wire bonding mode.
12. The preparation method of the GaN HEMT cascade device multi-layer sealing structure is characterized by comprising the following steps of:
the MOS chip is arranged on the back surface of the substrate, and the source electrode of the MOS chip is bonded and connected with the third conductive layer on the back surface of the substrate through conductive adhesive, so that a laminated structure of the MOS chip and the substrate is formed;
a source window is arranged on the front surface of the GaN chip, any point in the source window is configured as a source electrode of the GaN chip, and the size of the source window is larger than that of the laminated structure;
arranging the MOS chip in the source window, attaching the surface of the MOS chip provided with the drain electrode to the source window, and bonding and electrically connecting the drain electrode of the MOS chip with the source window through conductive adhesive;
the back of the GaN chip is provided with a grid electrode, the back of the GaN chip is connected with a lead frame base island in a bonding mode, the grid electrode of the GaN chip is connected with a conductive area on the lead frame base island in an adhesive mode through conductive adhesive, and the conductive area is configured to be electrically connected with a source electrode of the GaN HEMT cascading device;
electrically connecting the fourth conductive layer on the front surface of the substrate with the source window in a bonding wire mode;
electrically connecting the source electrode of the MOS chip with the conductive region in a bonding wire mode, wherein the surface of the source electrode of the MOS chip is opposite to the surface of the grid electrode of the MOS chip;
and electrically connecting the grid electrode of the MOS chip with the grid electrode on the lead frame base island in a wire bonding mode, and electrically connecting the drain electrode of the GaN chip with the drain electrode on the lead frame base island in a wire bonding mode.
13. The production method according to claim 11 or 12, characterized in that the production method further comprises: and packaging the integrated structure of the GaN chip, the substrate, the MOS chip and the lead frame base island which are electrically connected by adopting a mould injection molding process.
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