CN117438310A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN117438310A CN117438310A CN202210837440.7A CN202210837440A CN117438310A CN 117438310 A CN117438310 A CN 117438310A CN 202210837440 A CN202210837440 A CN 202210837440A CN 117438310 A CN117438310 A CN 117438310A
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- 238000000034 method Methods 0.000 title claims abstract description 114
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 69
- 239000010410 layer Substances 0.000 description 114
- 229910052581 Si3N4 Inorganic materials 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- 238000010586 diagram Methods 0.000 description 12
- 238000001459 lithography Methods 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000002344 surface layer Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
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- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The embodiment of the application provides a method for manufacturing a semiconductor device, the semiconductor device, a chip and electronic equipment, wherein the method comprises the following steps: forming a hard mask layer over a substrate; forming a sacrificial material layer over the hard mask layer; etching the sacrificial material layer to obtain a first virtual fin pattern; etching part of the side wall in the first virtual fin pattern to obtain a second virtual fin pattern; and etching the hard mask layer and the substrate according to the second virtual fin pattern to obtain the semiconductor device with the first fin pattern, wherein the first fin pattern comprises two first fins and K second fins. The semiconductor device manufactured by the method provided by the embodiment of the application can meet the CD requirement among the fins, and the etching of the semiconductor device can be simpler.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a method for designing and manufacturing a semiconductor device and the semiconductor device.
Background
As semiconductor processes evolve, the size of semiconductor devices is getting smaller and smaller, as are the channels of transistors. Quantum tunneling tends to occur when the transistor channel is shortened to some extent. Quantum tunneling can result in free serial connection of electrons between source and drain without a voltage applied, thereby disabling the transistor.
To break through the process limitations, fin field effect transistors (finfets) have been proposed. In the conventional transistor structure, a gate for controlling the passage of current can only control the on/off of a circuit at one side of the gate, and belongs to a planar architecture. In the FinFET architecture, the gate is a fin-like structure that controls the switching on and off of the circuit on both sides of the circuit. This design can greatly improve circuit control and reduce leakage current (leakage) and can also greatly shorten the gate length of the transistor.
Current methods of manufacturing finfets are to Etch (ET) the substrate and the hard mask layer to obtain a plurality of fins, and then etch the plurality of fins to etch away more fins and to etch recesses in some of the fins for placement of the gate. But limited by the process, the depth-to-width ratio of the recess etched by this fabrication method for placing the gate is large. Meanwhile, the critical dimensions (critical dimension, CD) of the yellow light used for etching cannot meet the CD requirements between fins.
Disclosure of Invention
The embodiment of the application provides a method for manufacturing a semiconductor device, the semiconductor device, a chip and electronic equipment, which can meet the critical dimension requirement between fins.
In a first aspect, embodiments of the present application provide a method for manufacturing a semiconductor device, including: forming a hard mask layer over a substrate; forming a sacrificial material layer over the hard mask layer; etching the sacrificial material layer to obtain a first virtual fin pattern, wherein the first virtual fin pattern comprises N first side walls; etching M first side walls of the N first side walls to obtain a second virtual fin pattern, wherein the second virtual fin pattern comprises K second side walls and two first side walls of the N first side walls, the K second side walls are positioned between the two first side walls, the second side walls comprise first recesses, and N, M and K meet the following relations: n, M and K are positive integers, N is greater than M, M is greater than K, and the difference between N and M is 2; and etching the hard mask layer and the substrate according to the second virtual fin pattern to obtain a semiconductor device with a first fin pattern, wherein the first fin pattern comprises two first fins and K second fins, and the second fins comprise second recesses.
In the method for manufacturing the semiconductor device, the side wall etching process only etches the side wall to be etched, but does not etch the hard mask layer and the substrate. The semiconductor device manufactured by the method can meet the CD requirement between fins. Furthermore, the aspect ratio of the recess of the second fin may be less than 18, and may even be less than 13, according to the methods provided by embodiments of the present application. This may make the etching of the semiconductor device simpler.
With reference to the first aspect, in a possible implementation manner of the first aspect, before the etching the hard mask layer and the substrate according to the second virtual fin pattern, the method further includes: and forming a dielectric layer above the K second side walls, the two first side walls and the hard mask layer.
The addition of a dielectric layer prior to the fin etch process may achieve better accuracy. The etching process is mainly longitudinal etching, so that the distance of the fin in the Y direction can be reduced by adding a dielectric layer.
With reference to the first aspect, in a possible implementation manner of the first aspect, the etching the M first side walls of the N first side walls to obtain a second virtual fin pattern includes: etching a first group of side walls in the M first side walls to obtain a third virtual fin pattern, wherein the third virtual fin pattern comprises the two first side walls, a second group of side walls and a third group of side walls, each group of side walls in the first group of side walls, the second group of side walls and the third group of side walls comprises at least one first side wall, and the total number of the first side walls in the first group of side walls, the second group of side walls and the third group of side walls is M; and etching the second group of side walls and the third group of side walls to obtain the second virtual fin pattern, wherein the second group of side walls and the third group of side walls are positioned between the two first side walls, the first group of side walls are positioned between the second group of side walls and the third group of side walls, and the total number of the first side walls included by the second group of side walls and the third group of side walls is K.
With reference to the first aspect, in a possible implementation manner of the first aspect, the etching the M first side walls of the N first side walls to obtain a second virtual fin pattern includes: and etching the M first side walls by using a multilayer photoresist process to obtain the second virtual fin pattern.
With reference to the first aspect, in a possible implementation manner of the first aspect, etching the hard mask layer and the substrate according to the second virtual fin pattern to obtain a semiconductor device with a first fin pattern includes: and etching the hard mask and the substrate by using a multilayer photoresist process to obtain the semiconductor device with the first fin pattern.
The multilayer photoresist technique can achieve higher accuracy and thus can control CD between fins more precisely.
With reference to the first aspect, in a possible implementation manner of the first aspect, the semiconductor device further includes at least two protruding portions, where each protruding portion of the at least two protruding portions corresponds to at least two second side walls.
With reference to the first aspect, in a possible implementation manner of the first aspect, the protruding portion is concave.
In a second aspect, embodiments of the present application provide a semiconductor device fabricated according to the first aspect or any one of the possible implementations of the first aspect.
In a third aspect, the present application provides a chip comprising at least one semiconductor device as described in the second aspect.
In a fourth aspect, embodiments of the present application provide an electronic device, where the electronic device includes the chip in the third aspect.
Drawings
Fig. 1 is a schematic flow chart of a method for fabricating a semiconductor device according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a manufacturing process of a semiconductor device according to an embodiment of the present application.
Fig. 3 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 4 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 5 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 6 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 7 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 8 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 9 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 10 is another schematic diagram of a manufacturing process of the semiconductor device according to the embodiment of the present application.
Fig. 11 is a schematic flow chart of a method of fabricating a semiconductor device.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.
It is to be understood that the following description is of embodiments only and is not intended to be limiting. For example, in the following description, forming a second component over or on a first component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed directly in the first component and the second component, such that the first component and the second component may not be in direct contact.
Fig. 1 is a schematic flow chart of a method for fabricating a semiconductor device according to an embodiment of the present application.
A hard mask layer is formed 101 on a substrate.
102, forming a sacrificial material layer over the hard mask layer.
And 103, etching the sacrificial material layer to obtain a first virtual fin pattern. The first dummy fin pattern includes N spacers.
104, etching the M side walls in the N side walls to obtain a second virtual fin pattern.
The second dummy fin pattern includes k+2 sidewalls, wherein the K sidewalls have recesses and the 2 sidewalls have no recesses. In order to distinguish between a sidewall with a recess and a sidewall without a recess, the sidewall without a recess may be referred to as a first sidewall and the sidewall with a first recess may be referred to as a second sidewall. In other words, the second dummy fin pattern includes K second sidewalls and two first sidewalls. The side walls in the first virtual fins are all first side walls. The K second side walls are positioned between the two first side walls. The M side walls are positioned between the two first side walls included in the second virtual fin pattern.
N, M and K satisfy the following relationship: n, M and K are positive integers, N is greater than M, M is greater than K, and the difference between N and M is 2.
Etching the fin in a subsequent step may also result in a fin with recesses. To distinguish between recesses of the fins and recesses of the sidewalls, the recesses included in the second sidewall may be referred to as first recesses.
And 105, etching the hard mask layer and the substrate according to the second virtual fin pattern to obtain the semiconductor device with the first fin pattern.
The first fin image includes fins with recesses and fins without recesses. For ease of distinction, a fin without a recess may be referred to as a first fin and a fin with a recess may be referred to as a second fin. The first fin pattern comprises two first fins and K second fins. As described above, to distinguish between recesses included in the sidewalls, the second fin including recesses may be referred to as second recesses.
Two first fins in the first fin pattern are in one-to-one correspondence with two first side walls in the second virtual fin pattern, and K second fins in the first fin pattern are in one-to-one correspondence with K second side walls in the second virtual fin pattern.
The method of manufacturing the semiconductor device shown in fig. 1 is described in detail below with reference to fig. 2 to 10.
Referring to fig. 2, a semiconductor substrate 201 is provided. The semiconductor substrate 201 may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The semiconductor substrate 201 may be doped with a p-type impurity or an n-type impurity. The thickness of the semiconductor substrate 201 is typically 1000 angstromsTo between 1800 angstroms. It will be appreciated by those skilled in the art that the materials and thicknesses of the various layers involved in fabricating the semiconductor device disclosed in the embodiments of the present application are merely for the purpose of facilitating a better understanding of the technical solutions of the present application by those skilled in the art, and are not limiting of the technical solutions of the present application.
A hard mask layer 210 may be formed on the semiconductor substrate 201. In some embodiments, the hard mask layer may be a dielectric layer.
The hard mask layer 210 as shown in fig. 2 includes an oxide layer 211, a silicon nitride layer 212, and an oxide layer 213.
The material of the oxide layer 211 may be any commonly used oxide material. The oxide layer 211 may be formed by chemical vapor deposition (chemical vapor deposition, CVD), such as low temperature chemical vapor deposition (low-temperature chemical vapor deposition, LTCVD), low pressure chemical vapor deposition (low-pressure chemical vapor deposition, LPCVD), and plasma chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD); sputtering, physical vapor deposition (physical vapor deposition, PVD), and the like.
The material of the silicon nitride layer 212 may be silicon nitride. The silicon nitride layer 211 may be formed by CVD, PVD, or the like.
The material of the oxide layer 213 may be any commonly used oxide material. The oxide layer 213 may be formed by CVD or PVD or the like.
The thickness of the hard mask layer 210 may be controlled to be between 420 and 1180 angstroms, wherein the thickness of the oxide layer 211 may be between 300 and 900 angstroms, the thickness of the silicon nitride layer 212 may be between 100 and 300 angstroms, and the thickness of the oxide layer 213 may be between 20 and 100 angstroms.
It will be appreciated by those skilled in the art that the hard mask layer shown in fig. 2 comprising oxide layer 211, silicon nitride layer 212, and oxide layer 213 is only an example of one hard mask layer. In other embodiments, the hard mask layer formed on the substrate may be other structures. For example, only the oxide layer 211 and the silicon nitride layer 212 may be included, or only the silicon nitride layer 212 and the oxide layer 213 may be included, or only the silicon nitride layer 212 or the oxide layer 211 may be included. As another example, the silicon nitride layer 212 may also replace components of nitride, oxynitride, silicon-rich oxide, fluorine-containing silicon dioxide, or carbon-doped silicon oxide.
A sacrificial material layer 220 is formed on the hard mask layer 210. The sacrificial material layer 220 may be nitride, oxynitride, or the like. The sacrificial material layer 220 may be formed by CVD or PVD or the like. The thickness of the sacrificial material layer 220 ranges from 600 angstroms to 1300 angstroms.
Referring to fig. 3, fig. 3 is the result of etching the sacrificial material layer 220. After etching the sacrificial material layer, a plurality of side walls can be obtained. The post-etch includes sidewalls 221 through 228 as shown in fig. 2.
Fig. 4 (a) is a top view of fig. 3. The dummy fin pattern shown in (a) of fig. 4 is the first dummy fin pattern in the method shown in fig. 1.
Fig. 4 (b) is a sectional view of section A-A' in fig. 3.
Fig. 4 (c) is a sectional view of section B-B' in fig. 3.
Fig. 5 is a schematic diagram after step 104 shown in fig. 1 is performed. Corresponding to the method shown in fig. 1, N equals 8, m equals 6,K equals 4 in the devices shown in fig. 3 and 5.
Fig. 6 (a) is a top view of the device shown in fig. 5. The dummy fin pattern shown in (a) of fig. 6 is a second dummy fin pattern called in the method shown in fig. 1.
Fig. 6 (b) is a sectional view of section A-A' in fig. 5.
Fig. 6 (c) is a sectional view of section B-B' in fig. 5.
As shown in fig. 6 (c), the sidewall 223 includes a recess 231 therein. Recess 231 corresponds to the so-called first recess in the method shown in fig. 1. Referring to fig. 6 (a), it can be seen that the side walls 222, 226 and 227 also have the same recessed structure as the side wall 223, while the side walls 221 and 228 have no recessed structure. Thus, sidewall 221 and sidewall 228 are two first sidewalls included in the second dummy fin pattern referred to in the method of fig. 1, and sidewall 222, sidewall 223, sidewall 226, and sidewall 227 are K second sidewalls (where K is equal to 4) included in the second dummy fin pattern.
It can be seen that, by etching, part of the side wall in the first virtual fin pattern can be etched, part of the side wall is etched, and the rest of the side wall is kept unchanged. For convenience of description, the sidewalls in the first dummy fin pattern may be divided into four groups: the first group of side walls, the second group of side walls, the third group of side walls and the fourth group of side walls, wherein the first group of side walls are completely etched side walls, the second group of side walls and the third group of side walls are partially etched side walls, and the fourth group of side walls are side walls which are not etched. For ease of description, assume that N is used 1 Representing the number of the side walls included in the first group of side walls by N 2 Representing the number of the side walls included in the second group of side walls by N 3 Representing the number of the side walls included in the third group of side walls by N 4 And the number of the side walls included in the fourth group of side walls is represented.
N 1 、N 2 And N 3 Are positive integers greater than or equal to 1, and N 1 、N 2 And N 3 Sum is M, N 2 And N 3 The sum of (2) is K. Alternatively, N 2 Can be equal to N 3 . In other words, each of the first, second, and third sets of side walls includes at least one side wall. The first set of side walls, the second set of side walls and the third set of side walls comprise M side walls which need to be etched in step 104. For the second group of sidesAnd etching the wall and the third group of side walls to obtain K second side walls in the K second virtual fin patterns.
N 4 Has a value of 2. In other words, the fourth set of side walls includes two side walls. The two side walls included in the fourth set of side walls are the two first side walls in the second virtual fin pattern.
The first set of side walls is located between the second set of side walls and the third set of side walls, the second set of side walls is located between one of the first set of side walls and the fourth set of side walls, and the third set of side walls is located between the other of the first set of side walls and the fourth set of side walls.
Corresponding to fig. 3 and 5,N 1 =N 2 =N 3 =N 4 Wherein the first set of side walls includes side walls 224 and 225, the second set of side walls includes side walls 222 and 223, the third set of side walls includes side walls 226 and 227, and the fourth set of side walls includes side walls 221 and 228.
In some embodiments, the following scheme (hereinafter referred to as scheme 1) may be used for etching the M side walls (i.e., the first set of side walls, the second set of side walls, and the third set of side walls): the first step: etching the first group of side walls; and a second step of: and etching the second set of side walls and the third set of side walls.
In other embodiments, the following scheme (hereinafter referred to as scheme 2) may be used for etching the M side walls: the first step: etching the first group of side walls; and a second step of: etching the second group of side walls; and a third step of: and etching the third group of side walls.
In other embodiments, the following scheme (hereinafter referred to as scheme 3) may be used for etching the M side walls: the first step: etching the second set of side walls and the third set of side walls; and a second step of: and etching the first group of side walls.
In other embodiments, the following scheme (hereinafter referred to as scheme 4) may be used for etching the M side walls: the first step: etching the second group of side walls; and a second step of: etching the first group of side walls; and a third step of: and etching the third group of side walls.
Of course, other ways of etching the M side walls may be used in addition to the schemes 1 to 4. For example, the etching of the M side walls may be divided into M steps, one side wall being etched in each step.
Fig. 7 and 8 show the etching process of scheme 1.
Fig. 7 shows a process of etching the first set of sidewalls in scheme 1.
Fig. 7 (a) is a top view of the device shown in fig. 3 after the surface of the device has been coated with photoresist (photoresist).
Fig. 7 (b) is a cross-sectional view of section A-A' after the photoresist has been applied to the device surface as shown in fig. 3.
Fig. 7 (c) is a cross-sectional view of section B-B' after the device surface shown in fig. 3 has been coated with photoresist.
As shown in fig. 7 (b) and fig. 7 (c), a three-layer photoresist technique is applied during etching of the first set of sidewalls. The three layers of photoresist are respectively a surface layer photoresist 233, a middle layer photoresist 232 and a bottom layer photoresist 231.
The material of the top layer photoresist 233 may be various commonly used photoresist materials. The thickness may be 600 angstroms to 1000 angstroms. As shown in (b) of fig. 7, there is a recess 241 in the surface layer photoresist 233. Recess 241 is located over intermediate layer photoresist 233.
The material of the intermediate layer photoresist 232 may be various commonly used silicon anti-reflective coatings (Si-anti-reflection coating, siARC). The thickness may be 300 angstroms to 700 angstroms. As shown in fig. 7 (a) and fig. 7 (b), the projection range of the intermediate layer photoresist 233 is larger than the projection range of the first set of side walls (side walls 224 and 225).
The material of the underlying photoresist 231 can be a variety of commonly used photoresist materials. The thickness may be 1400 angstroms to 2400 angstroms. The thickness of the underlayer photoresist 231 referred to herein refers to the thickness from the top surface of the sidewall to the bottom surface of the surface layer photoresist 233.
The multilayer photoresist technique can achieve higher accuracy and thus can control CD between fins more precisely.
It will be appreciated that the three-layer photoresist shown in fig. 7 is only one example of a multi-layer photoresist technique. In some embodiments, the first set of sidewalls may also be etched using two, four, or other multi-layer photoresist techniques. Of course, in some embodiments, the first set of sidewalls may also be etched using a single layer photoresist technique.
Fig. 7 (d) is a top view of the first set of sidewalls after etching.
Fig. 7 (e) is a cross-sectional view of section A-A' after etching the first set of sidewalls.
Fig. 7 (f) is a cross-sectional view of section B-B' after etching the first set of sidewalls.
As shown in fig. 7 (d) and 7 (e), after etching the first set of sidewalls (i.e., sidewall 224 and sidewall 225), the original 8 sidewalls only left 5 sidewalls. The dummy fin pattern of the top view shown in (d) of fig. 7 may be referred to as a third dummy fin pattern.
As shown in (d) of fig. 7 and (f) of fig. 7, after etching the first set of sidewalls, the sidewalls in the remaining dummy fin pattern do not include recesses. In other words, the sidewalls included in the third dummy fin pattern are all the first sidewalls.
The process shown in fig. 7 for etching the first set of sidewalls may be referred to as a horizontal active area (active regions horizontal, ARH) process.
Fig. 8 shows a process of etching the second set of side walls and the third set of side walls in scheme 1.
Fig. 8 (a) is a top view of the device after the ARH process is completed after the photoresist is coated on the device surface.
Fig. 8 (b) is a cross-sectional view of section A-A' after the photoresist has been applied to the device surface after the ARH process has been completed.
FIG. 8 (c) is a cross-sectional view of section B-B' after the device surface has been coated with photoresist after the ARH process has been completed.
Similar to etching the first set of sidewalls, in the example shown in fig. 8, the three-layer photoresist technique is used to etch the second set of sidewalls and the third set of sidewalls. The three layers of photoresist are respectively a surface layer photoresist 233, a middle layer photoresist 232 and a bottom layer photoresist 231. The specific materials and thicknesses of the three layers of photoresist may be described with reference to fig. 7, and will not be described herein for brevity.
It will be appreciated that the photoresist technique used in etching the first set of side walls shown in fig. 7 is the same as the photoresist technique used in etching the second and third sets of side walls shown in fig. 8. In other embodiments, the photoresist technique used to etch the first set of sidewalls may be different from the photoresist technique used to etch the second and third sets of sidewalls. For example, in some embodiments, the etching of the first set of sidewalls may use a multi-layer photoresist technique (e.g., a two-layer photoresist technique, a three-layer photoresist technique, etc.), and the etching of the second and third sets of sidewalls may use a single-layer photoresist technique. For another example, in some embodiments, etching the first set of sidewalls may be performed using a single layer photoresist technique, and etching the second and third sets of sidewalls may be performed using a multi-layer photoresist technique. For another example, three layers of photoresist technology are used for etching the first set of side walls, two or four layers of photoresist technology are used for etching the second set of side walls and the third set of side walls, and the like.
As shown in fig. 8 (b), the surface layer photoresist 233 has a recess 242 and a recess 243 therein. Recesses 242 and 243 are located over the intermediate layer photoresist, respectively.
Fig. 8 (d) is a top view of the second and third sets of side walls after etching.
Fig. 8 (e) is a cross-sectional view of section A-A' after etching the second and third sets of side walls.
Fig. 8 (f) is a cross-sectional view of section B-B' after etching the second and third sets of side walls.
As shown in fig. 8 (d) and 8 (e), after etching the second set of side walls (i.e., side walls 222 and 223) and the third set of side walls (i.e., side walls 226 and 227), each of the second set of side walls and the third set of side walls includes a recess. The dummy fin pattern of the top view shown in (d) of fig. 8 is the second dummy fin pattern referred to above. The second set of side walls and the third set of side walls are the side walls comprising the second side walls in the second virtual fin pattern. The fourth set of spacers (i.e., spacers 221 and 228) are not etched. Therefore, the two side walls included in the fourth set of side walls are the first side walls in the second virtual fin pattern.
The process shown in fig. 8 for etching the second set of sidewalls and the third set of sidewalls may be referred to as a single diffusion break (single diffusion break, SDB) process.
It will be appreciated by those skilled in the art that the number of the first, second and third sets of side walls etched by the ARH and SDB processes shown in fig. 7 and 8 is merely an example. In other embodiments, the first set of side walls, the second set of side walls, and the third set of side walls may include other numbers of side walls. For example, the first set of side walls may include 3 side walls, and the second and third sets of side walls may include 4 side walls. As another example, each of the first set of side walls, the second set of side walls, and the third set of side walls may include 4 side walls. For another example, the first set of side walls may include 2 side walls, and each of the second set of side walls and the third set of side walls may include 3 side walls.
Figure 9 illustrates a schematic diagram of an etch-away process for a hard mask layer and a substrate according to a second fin pattern.
As in fig. 9 (a), fig. 9 (B) and fig. 9 (c) are top views of the device after the second fin pattern is obtained, a cross-sectional view of section A-A 'and a cross-sectional view of section B-B', respectively. It can be seen that (a) in fig. 9, (b) in fig. 9 and (c) in fig. 9 are identical to (d) in fig. 8, and (e) in fig. 8 and (f) in fig. 8, respectively. For brevity, description of fig. 9 (a), fig. 9 (b) and fig. 9 (c) will not be repeated here.
In some embodiments, a dielectric layer may be formed over the hard mask layer prior to etching the hard mask layer and the substrate.
Fig. 9 (d) is a top view of the device after the dielectric layer is formed.
Fig. 9 (e) is a cross-sectional view of the A-A' cross-section of the device after formation of the dielectric layer.
Fig. 9 (f) is a cross-sectional view of the B-B' section of the device after the dielectric layer is formed.
As shown in fig. 9 (e) and 9 (f), a dielectric layer 250 is formed over the hard mask layer 210. The material of the dielectric layer 250 may be silicon nitride or other dielectric material that may be formed over the hard mask layer by atomic layer deposition (atom layer deposition) techniques, etc. The thickness of dielectric layer 250 may be 40 angstroms to 100 angstroms.
After the dielectric layer is formed, the hard mask layer including the dielectric layer and the substrate may be etched, and the result after etching is shown in fig. 9 (g), fig. 9 (h), and fig. 9 (i).
Fig. 9 (g) is a top view of the hard mask layer and the substrate after etching is completed.
Fig. 9 (h) is a cross-sectional view of section A-A' after the hard mask layer and substrate etch are completed.
Fig. 9 (i) is a cross-sectional view of section B-B' after the hard mask layer and substrate etch are completed.
As shown in fig. 9 (h), the semiconductor device after the etching is completed includes a fin 261 and a fin 262. Further, the semiconductor device further includes two protruding portions (bumps), respectively protruding portion 271 and protruding portion 272. As shown in fig. 9, the protruding portion 271 and the protruding portion 272 are protruding portions in a concave shape. The reason for forming the concave-shaped protruding part is that the concave obtained after etching the two side walls is arranged above the protruding part before etching. Etching the substrate below the two side walls with the recesses can obtain concave-shaped protruding portions.
As shown in fig. 9 (g), the completed etched semiconductor device further includes fin 263, fin 264, fin 265, and fin 266. The section B-B' shown in fig. 9 is a cross-sectional view of fin 264. The cross-sections of fins 263, 265 and 266 are the same as the cross-section of fin 264. As shown in fig. 9 (i), the fin 264 includes one recess 245, and the recess 245 is a second recess called the upper question. In other words, fins 263 through 266 are the second fins referred to above. Fin 261 and fin 262 do not include recesses. Thus, fin 261 and fin 262 are the first fins referred to above.
The etching hard mask layer and substrate process may be referred to as a fin etching process. The fin etching process shown in fig. 9 further includes a step of forming a dielectric layer.
In other embodiments, the dielectric layer may not be required to be formed prior to the fin etching process. In other words, the hard mask layer and the substrate of the device shown in fig. 9 (a), fig. 9 (b) and fig. 9 (c) may be directly etched to obtain the semiconductor device shown in fig. 9 (g), fig. 9 (h) and fig. 9 (i).
After the fin etching process is completed, the hard mask layer and the substrate of the semiconductor device can be further etched as required.
Figure 10 is a schematic diagram of the etching process after the fin etching process is completed.
Fig. 10 (a) is a top view of the fin after the fin etching process is completed.
Fig. 10 (b) is a cross-sectional view of section A-A' after the fin etching process is completed.
Fig. 10 (c) is a cross-sectional view of section B-B' after the fin etching process is completed.
As shown in fig. 10 (b) and fig. 10 (c), the photoresist still employs a three-layer photoresist technique. The three layers of photoresist are respectively a surface layer photoresist 233, a middle layer photoresist 232 and a bottom layer photoresist 231. The specific materials and thicknesses of the three layers of photoresist may be described with reference to fig. 7, and will not be described herein for brevity.
Similarly, in some embodiments, the photoresist technique shown in FIG. 10 may be different from the photoresist technique used in the process shown in FIG. 7 or FIG. 8.
As shown in fig. 10 (c), the fin 264 is recessed into a longer and a shorter portion. For ease of description, the longer portion may be referred to as a first portion and the shorter portion as a second portion. As shown in fig. 10 (a) and 10 (c), the interlayer photoresist 232 is located over the first portion of fin 264 and over the first portion of fin 265.
Fig. 10 (d) is a top view after etching is completed.
Fig. 10 (e) is a sectional view of section A-A' after etching is completed.
Fig. 10 (f) is a sectional view of section B-B' after etching is completed.
As shown in fig. 10 (d) and fig. 10 (f), after the hard mask layer and substrate etch is completed, only the second portions of fin 264 and fin 265 remain. In other words, the first portions of fins 264 and 265 (i.e., the portion with the intermediate photoresist layer over them) are etched away. Distinguishing between the first fin without recesses (i.e., fin 261 and fin 262) and the second fin with recesses (i.e., fin 263 and fin 266) may be referred to as a third fin by the etching process shown in fig. 10.
The fin pattern shown in fig. 10 (d) may be referred to as a second fin pattern. The second fin pattern may include two first fins, two second fins, and two third fins.
The process illustrated in fig. 10 for etching fin 264 and fin 265 may be referred to as a vertical active area (active regions vertical, ARV) process.
It will be appreciated by those skilled in the art that the second fin pattern obtained by performing the ARV process according to the method shown in fig. 10 is merely an example of one type of second fin pattern obtained according to design requirements. Different second fin patterns can be obtained according to different design requirements. For example, in some embodiments, the second fin pattern may include a different number of first fins (or second fins, or third fins) than the second fin pattern as shown in fig. 10. As another example, in some embodiments, a fourth fin may be further included in the second fin pattern, the fourth fin being different from any of the first fin, the second fin, or the third fin. As another example, in other embodiments, the cross-section of the third fin may be different than the cross-section of the third fin shown in fig. 10. For example, the ARV process etches the hard mask layer and the substrate with the second portions of fins 264 and 265 being the etched object and the first portions being left.
After the ARV process is completed, operations such as filling dielectric film (dielectric film) and gate material may be performed in the semiconductor device, resulting in a FinFET. The specific implementation process of filling dielectric film (dielectric film) and gate material to obtain FinFET is the same as the existing process, and will not be repeated here for brevity.
Fig. 11 is a flowchart for reflecting the process shown in fig. 2 to 10.
The completed sidewall etch (post spacer ET) shown in fig. 11 is a process for forming the first dummy pattern.
As shown in fig. 11, the ARH process is divided into two steps, the first step may be called ARH Lithography (LT), and the second step may be called ARH ET. ARH LT is to coat photoresist on the device after the side wall etching is completed, and ARH ET is to etch the device after the photoresist coating is completed. Fig. 7 (a) - (c) are views of the device after the ARH LT is completed, and fig. 7 (d) - (f) are views of the device after the ARH ET is completed.
As shown in fig. 11, the SDB process may also be divided into two steps, the first step may be referred to as SDB LT and the second step may be referred to as SDB ET. SDB LT is to coat a photoresist on the device after ARH is completed, and SDB ET is to etch the device after the photoresist is coated. Fig. 8 (a) - (c) are views of the device after SDB LT is completed, and fig. 8 (d) - (f) are views of the device after SDB ET is completed.
A dielectric layer is formed of a silicon nitride (SiN) overlap (recap) as shown in fig. 11. Fig. 9 (d) - (f) are views of the device after SiN recap is completed.
It is understood that SiN recap is an alternative process. The addition of SiN recap prior to the fin etch process may achieve better accuracy. The etching process is mainly longitudinal etching, so that the distance in the Y direction (namely, the B-B' direction) of the fin can be reduced by adding a dielectric layer.
In other embodiments, the SDB process may be followed by a Fin ET.
Fin ET as shown in fig. 11 is the Fin etching process mentioned above. Fig. 9 (g) - (i) are views of the device after Fin ET is completed.
As shown in fig. 11, the ARV process may also be divided into two steps, the first step may be referred to as ARV LT and the second step may be referred to as ARV ET. ARV LT is the coating of photoresist on the device after Fin ET is completed, and ARV ET is the etching of the device after photoresist coating. Fig. 10 (a) - (c) are views of the device after the ARV LT is completed, and fig. 10 (d) - (f) are views of the device after the ARV ET is completed.
In the method for manufacturing the semiconductor device, the side wall etching process only etches the side wall to be etched, but does not etch the hard mask layer and the substrate. In addition, the ARH process and the SDB process are performed before the fin etching process. Thus, CD requirements between fins can be met. Furthermore, the aspect ratio of the recess of the second fin may be less than 18, and may even be less than 13, according to the methods provided by embodiments of the present application. This may make the etching of the semiconductor device simpler.
The embodiment of the application also provides a semiconductor device manufactured according to the method.
In some embodiments, the semiconductor device may be a FinFET.
The embodiment of the application also provides a chip, which is provided with the semiconductor device provided by the embodiment of the application. The embodiment of the application also provides electronic equipment, which comprises the chip.
The chip may be a central processing unit (central processing unit, CPU), a graphics processing unit (graphics processing unit, GPU), a data processing unit (data processing unit, DPU), an embedded neural Network Processor (NPU), a system on chip (SoC), or the like.
The electronic device may be a terminal device, such as a mobile phone, a personal computer, a notebook computer, a tablet computer, etc. The electronic device may also be a network-side device, e.g., a server, an access point, a router, a switch, etc. The electronic device may also be an electronic device such as a headset, a camera, a display, a memory, etc.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of fabricating a semiconductor device, comprising:
forming a hard mask layer over a substrate;
forming a sacrificial material layer over the hard mask layer;
etching the sacrificial material layer to obtain a first virtual fin pattern, wherein the first virtual fin pattern comprises N first side walls;
etching M first side walls of the N first side walls to obtain a second virtual fin pattern, wherein the second virtual fin pattern comprises K second side walls and two first side walls of the N first side walls, the K second side walls are located between the two first side walls, the second side walls comprise first recesses, and N, M and K meet the following relations: n, M and K are positive integers, N is greater than M, M is greater than K, and the difference between N and M is 2;
and etching the hard mask layer and the substrate according to the second virtual fin pattern to obtain a semiconductor device with a first fin pattern, wherein the first fin pattern comprises two first fins and K second fins, and the second fins comprise second recesses.
2. The method of claim 1, wherein prior to the etching the hard mask layer and the substrate according to the second virtual fin pattern, the method further comprises:
and forming a dielectric layer above the K second side walls, the two first side walls and the hard mask layer.
3. The method of claim 1 or 2, wherein etching M first sidewalls of the N first sidewalls to obtain a second virtual fin pattern includes:
etching a first group of side walls in the M first side walls to obtain a third virtual fin pattern, wherein the third virtual fin pattern comprises the two first side walls, a second group of side walls and a third group of side walls, each group of side walls in the first group of side walls, the second group of side walls and the third group of side walls comprises at least one first side wall, and the total number of the first side walls in the first group of side walls, the second group of side walls and the third group of side walls is M;
and etching the second group of side walls and the third group of side walls to obtain the second virtual fin pattern, wherein the second group of side walls and the third group of side walls are positioned between the two first side walls, the first group of side walls are positioned between the second group of side walls and the third group of side walls, and the total number of the first side walls included by the second group of side walls and the third group of side walls is K.
4. A method according to any one of claims 1 to 3, wherein etching M first sidewalls of the N first sidewalls to obtain a second virtual fin pattern includes:
and etching the M first side walls by using a multilayer photoresist process to obtain the second virtual fin patterns.
5. The method of any one of claims 1 to 4, wherein etching the hard mask layer and the substrate according to the second dummy fin pattern results in a semiconductor device having a first fin pattern, comprising:
and etching the hard mask and the substrate by using a multilayer photoresist process to obtain the semiconductor device with the first fin pattern.
6. The method of any of claims 1-5, wherein the semiconductor device further comprises at least two protrusions, each of the at least two protrusions corresponding to at least two second sidewalls.
7. The method of claim 6, wherein the protrusions are concave.
8. A semiconductor device manufactured according to the method of any one of claims 1 to 7.
9. A chip comprising at least one semiconductor device according to claim 8.
10. An electronic device comprising the chip of claim 9.
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