CN117422041A - Training method for automatic wiring model of analog chip and automatic wiring method - Google Patents
Training method for automatic wiring model of analog chip and automatic wiring method Download PDFInfo
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Abstract
The invention relates to the technical field of design of simulation chips, and provides an automatic wiring model training method and an automatic wiring method for a simulation chip. And the netlist information of the whole simulation chip is decomposed into various sub-network information, and the sub-network training of various circuit diagrams is utilized to obtain an automatic wiring model of the simulation chip, so that the searching range of a target genetic algorithm and a deep Q network can be reduced, and the training efficiency of the deep Q network can be further improved. The automatic wiring model of the simulation chip obtained by the training method can be suitable for wiring in the range of a circuit diagram sub-network, has a small searching range, can quickly obtain an optimal wiring scheme, can improve wiring efficiency, and provides convenience for quick production and batch application of the simulation chip.
Description
Technical Field
The invention relates to the technical field of simulation chip design, in particular to a simulation chip automatic wiring model training method and an automatic wiring method.
Background
The analog chip is a circuit for producing, amplifying and processing various analog signals, and the automatic wiring of the analog chip is a key technology, so that the efficiency and the accuracy of chip design can be remarkably improved. Automated routing typically uses computer aided design (Computer Aided Design, CAD) techniques to assist users in automatically generating optimized routing schemes.
The process of automated wiring typically includes the following key steps:
wiring planning: routing planning, prior to starting routing, according to the chip's layout and design specifications, may include determining available routing resources, clock distribution schemes, routing constraints, and the like.
And (3) path generation: the routing paths are generated based on the connection requirements and constraints of the circuit. These paths define how the different circuit elements are interconnected to achieve the intended function.
Network allocation: the signal network of the circuit is distributed and each signal is connected to the appropriate wiring channel. It is desirable to take into account interference and coupling between signals to minimize power consumption and delay.
Clock distribution: the clock signal is automatically distributed and is ensured to be uniformly distributed on the whole chip so as to meet the time sequence requirement. There is also a need to optimize clock wiring to reduce clock delay and jitter.
Optimization and iteration: algorithms and optimization techniques are used to improve the routing scheme. A number of factors, such as signal integrity, power consumption, noise, etc., are considered and iterative optimization is performed until an optimal routing solution is found.
Visualization and analysis: a visual interface can be provided to help the user analyze and adjust the wiring results. The user can view the routing path, signal delay, power consumption, etc. information to evaluate and optimize the routing scheme.
The automatic wiring scheme can not only greatly accelerate the chip design speed and reduce the time and effort required by manual wiring, but also help users avoid wiring errors and defects and improve the quality and reliability of the design.
However, the existing analog chip has a large wiring searching range, and the optimal wiring scheme is difficult to solve, so that the wiring efficiency is low, and the rapid production and batch application of chips are not facilitated.
Disclosure of Invention
The invention provides an automatic wiring model training method and an automatic wiring method for an analog chip, which are used for solving the defects in the prior art.
The invention provides an automatic wiring model training method for an analog chip, which comprises the following steps:
sample layout information, sample constraint information and sample netlist information of a simulation chip sample are obtained, and each sample circuit diagram sub-network in the simulation chip sample is determined based on the sample netlist information;
For any sample circuit diagram sub-network, converting the any sample circuit diagram sub-network into each pin pair with priority sequence based on a minimum spanning tree algorithm, and determining wiring path information between each pin pair by adopting a target genetic algorithm;
and placing the wiring path information into a playback buffer area of a deep Q network, training the deep Q network based on the sample layout information, the sample constraint information and the sample netlist information to obtain a trained deep Q network, and taking a target strategy network in the trained deep Q network as an automatic wiring model of the simulation chip.
According to the training method of the automatic wiring model of the analog chip, which is provided by the invention, any sample circuit diagram sub-network is converted into a pin pair with a priority order based on a minimum spanning tree algorithm, and the method comprises the following steps:
carrying out wiring priority sequencing on the sub-networks of the circuit diagrams of the samples;
and taking each sample circuit diagram sub-network as any sample circuit diagram sub-network in turn according to the order of the priority from high to low.
According to the training method of the automatic wiring model of the analog chip, which is provided by the invention, the wiring priority of each sample circuit diagram sub-network is ordered, and the training method comprises the following steps:
Determining the electrical signal frequency of each sample circuit diagram sub-network, and determining the wiring priority order of each sample circuit diagram sub-network from high to low based on the order of the electrical signal frequency of each sample circuit diagram sub-network from high to low; or,
determining the line length of each sample circuit diagram sub-network, and determining the wiring priority sequence of each sample circuit diagram sub-network from high to low based on the sequence of the line length of each sample circuit diagram sub-network from short to long.
According to the training method of the automatic wiring model of the simulation chip, provided by the invention, the depth Q network is trained based on the sample layout information, the sample constraint information and the sample netlist information, and the trained depth Q network is obtained, and the training method comprises the following steps:
determining a sample environment of a sample wiring intelligent agent based on the sample layout information, the sample constraint information and the sample netlist information, and determining a sample action space of the sample wiring intelligent agent;
determining the current state of the sample wiring intelligent body based on the current position of the sample wiring intelligent body on the wiring path information, sending the current state of the sample wiring intelligent body into a strategy network of a depth Q network, and selecting a first action from the sample action space by the strategy network;
Based on the sample wiring intelligent agent, the first action and the sample environment are interacted at the current position to obtain the next state of the sample wiring intelligent agent, the next state is input into a value network of a depth Q network to obtain the value of each action in the next state, and the second action with the maximum value in the next state is calculated;
and calculating a total return value corresponding to the current position, calculating a loss function based on the total return value and the second action, and carrying out iterative updating on the structural parameters of the depth Q network based on the loss function to obtain the trained depth Q network.
According to the training method of the automatic wiring model of the simulation chip provided by the invention, the total return value corresponding to the current position is calculated, and the method comprises the following steps:
if the current position is an arrival pin in the pin pair, determining that the total return value corresponding to the current position is a preset value;
and if the current position is a non-arrival pin, determining that the total return value corresponding to the current position is the sum of the return value of the current position and the return values of all positions before the current position.
The invention also provides an automatic wiring method of the analog chip, which comprises the following steps:
Acquiring target layout information, target constraint information and target netlist information of a simulation chip to be wired, and determining each target circuit diagram sub-network in the simulation chip to be wired based on the target netlist information;
for any target circuit diagram sub-network, converting the any target circuit diagram sub-network into each pin pair with priority order based on a minimum spanning tree algorithm, traversing each pin pair, inputting the state of the initial pin in the traversed current pin pair into an analog chip automatic wiring model to obtain a wiring strategy output by the analog chip automatic wiring model, and carrying out iterative wiring between the current pin pairs based on the wiring strategy.
According to the automatic wiring method of the analog chip provided by the invention, any target circuit diagram sub-network is converted into each pin pair with priority order based on a minimum spanning tree algorithm, and the method comprises the following steps:
carrying out wiring priority sequencing on each target circuit diagram sub-network;
and taking each target circuit diagram sub-network as any target circuit diagram sub-network in turn according to the order of the priority from high to low.
According to the automatic wiring method of the analog chip, the wiring strategy comprises the prediction action of a target wiring intelligent body; inputting the state of the initial pin in the traversed current pin pair to an analog chip automatic wiring model to obtain a wiring strategy output by the analog chip automatic wiring model, and performing iterative wiring between the current pin pair based on the wiring strategy, wherein the method comprises the following steps:
Determining a target environment of the target wiring agent based on the target layout information, the target constraint information and the target netlist information;
determining the current position of the target wiring intelligent body based on the state of the starting pin, determining the current state of the target wiring intelligent body based on the current position, interacting the predicted action with the target environment at the current position based on the target wiring intelligent body to obtain the next state of the target wiring intelligent body, iteratively inputting the next state into the simulated chip automatic wiring model, and updating the predicted action of the target wiring intelligent body until the current position is the arrival pin of the current pin pair.
The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the training method of the automatic wiring model of the simulation chip or the automatic wiring method of the simulation chip when executing the computer program.
The present invention also provides a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the simulated chip automated wiring model training method or the simulated chip automated wiring method as described in any one of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements the simulated chip automated wiring model training method or the simulated chip automated wiring method as described in any one of the above.
The invention provides an automatic wiring model training method and an automatic wiring method for a simulation chip, wherein the training method firstly obtains sample layout information, sample constraint information and sample netlist information of a simulation chip sample, and determines each sample circuit diagram sub-network in the simulation chip sample based on the sample netlist information; then, for any sample circuit diagram sub-network, converting the any sample circuit diagram sub-network into each pin pair with priority order based on a minimum spanning tree algorithm, and determining wiring path information between each pin pair by adopting a target genetic algorithm; and finally, placing the wiring path information into a playback buffer area of the deep Q network, training the deep Q network based on sample layout information, sample constraint information and sample netlist information to obtain a trained deep Q network, and taking a target strategy network in the trained deep Q network as an automatic wiring model of the simulation chip. According to the training method, the wiring path information obtained by the target genetic algorithm is used as playback experience of the deep Q network, so that training efficiency of the deep Q network can be improved. And the simulation chip sample is divided into various sample circuit diagram sub-networks, and the simulation chip automatic wiring model is obtained by utilizing the training of various sample circuit diagram sub-networks, so that the searching range of a target genetic algorithm and a deep Q network can be reduced, and the training efficiency of the deep Q network can be further improved. The automatic wiring model of the simulation chip obtained by the training method can be suitable for wiring in the range of a circuit diagram sub-network, has a small searching range, can quickly obtain an optimal wiring scheme, can improve wiring efficiency, and provides convenience for quick production and batch application of the simulation chip.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to these drawings without inventive effort.
FIG. 1 is a schematic flow chart of an automatic wiring model training method for an analog chip;
FIG. 2 is a schematic flow chart of an automated wiring method for an analog chip according to the present invention;
FIG. 3 is a second flow chart of the automatic wiring method of the analog chip provided by the invention;
FIG. 4 is a schematic flow chart of an automated wiring method for an analog chip, which is provided by the invention, for automatically wiring a pin A and a pin B on a second layer in the analog chip to be wired;
FIG. 5 is a schematic diagram of a target minimum spanning tree in an automated wiring method for an analog chip according to the present invention;
FIG. 6 is a schematic diagram of the structure of the training device for the automatic wiring model of the analog chip;
FIG. 7 is a schematic diagram of an automated wiring device for an analog chip according to the present invention;
Fig. 8 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The features of the invention "first", "second" and the like in the description and in the claims may be used for the explicit or implicit inclusion of one or more such features. In the description of the invention, unless otherwise indicated, the meaning of "a plurality" is two or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The existing simulation chip wiring scheme has the defects of large searching range, difficult solving, low wiring efficiency and the like, and is not beneficial to the rapid production and batch application of chips.
Based on the above, the embodiment of the invention provides a training method for an automatic wiring model of an analog chip, which is used for training out the automatic wiring model of the analog chip with high wiring efficiency and is beneficial to the rapid production and batch application of the analog chip.
Fig. 1 is a schematic flow chart of an automatic wiring model training method for an analog chip according to an embodiment of the present invention. As shown in fig. 1, the training method includes:
s11, sample layout information, sample constraint information and sample netlist information of a simulation chip sample are obtained, and each sample circuit diagram sub-network in the simulation chip sample is determined based on the sample netlist information;
s12, for any sample circuit diagram sub-network, converting the any sample circuit diagram sub-network into each pin pair with priority sequence based on a minimum spanning tree algorithm, and determining wiring path information between each pin pair by adopting a target genetic algorithm;
s13, placing the wiring path information into a playback buffer area of a deep Q network, training the deep Q network based on the sample layout information, the sample constraint information and the sample netlist information to obtain a trained deep Q network, and taking a target strategy network in the trained deep Q network as an automatic wiring model of the simulation chip.
Specifically, in the method for training an automatic wiring model of an analog chip provided in the embodiment of the present invention, the execution subject is an automatic wiring model training device of an analog chip, and the device may be configured in a computer, where the computer may be a local computer or a cloud computer, and the local computer may be a computer, a tablet, etc., and is not limited herein specifically.
Step S11 is executed first, and sample layout information, sample constraint information and sample netlist information of a sample of the simulation chip are obtained. The analog chip sample refers to an analog chip which is not wired after being laid out and is used for training an automatic wiring model of the analog chip.
The sample layout information may include position information and pin information of each device in the analog chip sample, the sample constraint information may include position information of each device in the analog chip sample, symmetry information of each device, DRC rule information, etc., the sample netlist information may include connection relations required for each device in the analog chip sample, and the DRC rule information may include design rule checking, electrical rule checking, short circuit checking, etc. It will be appreciated that each device is an obstacle to the signal line at the time of wiring, and therefore the positional information of each device is included in the sample constraint information to indicate that the devices need to be bypassed at the time of wiring.
And determining each sample circuit diagram sub-network in the analog chip sample by using the sample netlist information. The sample netlist information may be considered as a whole-sample circuit-schematic network of analog chip samples, and one or more sample circuit-schematic sub-networks may be obtained by partitioning the whole-sample circuit-schematic network. The sample circuit diagram sub-networks can be obtained by dividing the whole sample circuit diagram sub-network from different function realization angles, and further, the sample circuit diagram sub-networks can have different functions respectively.
The devices in each sample circuit diagram sub-network are connected by pins. It will be appreciated that the same or different devices may be included in different sub-networks of the same circuit diagram, and that the connections of the same devices in different sub-networks of the same circuit diagram may be implemented using different pins.
For example, the sample circuit diagram sub-network a and the sample circuit diagram sub-network B each include a device a, the device a in the sample circuit diagram sub-network a is connected to a device B, the device a in the sample circuit diagram sub-network B is connected to a device C, and then the device a in the sample circuit diagram sub-network a may be connected to one pin of the device B through a pin p1, and the device a in the sample circuit diagram sub-network B may be connected to one pin of the device C through a pin p 2.
Then, step S12 is performed, where each sample circuit diagram sub-network may be routed separately, and the routing order of each sample circuit diagram sub-network may be obtained by random sorting.
For any sample circuit diagram sub-network, a minimum spanning tree (Minimun Spanning Tree, MST) algorithm may be employed first to convert any sample circuit diagram sub-network to pin pairs with a priority order. Wherein, the MST algorithm can be a Primam algorithm or a Cruskarl algorithm. Each converted pin pair can form a sample minimum spanning tree, namely each node in the sample minimum spanning tree is a pin of a device. The multi-pin problem can be converted to a two-pin problem by a minimum spanning tree algorithm.
Thereafter, wiring path information between each pin pair is determined by using a target genetic algorithm in order of higher to lower wiring priority of each pin pair.
The target genetic algorithm is used for searching a wiring path between each pin pair, and the starting point of the wiring path is start, and the end point of the wiring path is G. The routing path information may include routing paths between pairs of pins.
The target genetic algorithm may be obtained by training the initial genetic algorithm. The initial genetic algorithm may be an a-algorithm, for example, a 3D A-algorithm.
In training the initial genetic algorithm, the loss function employed may be:
f(t)＝g(t)+h(t)；
where t represents a time step, g (t) represents a bus length from a start pin (start) to a current position in any pin pair, and h (t) represents a distance between the current position and an arriving pin in any pin pair.
Finally, step S13 is executed, and a Deep Q-network (DQN) is introduced, where the Deep Q-network refers to a Q learning algorithm based on Deep learning, combines a value function approximation and a neural network technology, and performs training of the network by adopting a target network and a playback experience method. The deep Q network may include a policy network and a value network, and the deep Q network employed in embodiments of the present invention may be a Double DQN.
Here, the routing path information may be placed in a playback buffer (replay buffer) of the deep Q network, providing a priori knowledge for training of the deep Q network. Therefore, by using the playback buffer and combining the sample layout information, the sample constraint information and the sample netlist information, the depth Q network can be trained, namely, the strategy network and the value network of the DQN are updated, so that a solution better than a target genetic algorithm is obtained.
After the trained deep Q network is obtained, the target strategy network in the trained deep Q network can be used as an automatic wiring model of the simulation chip. The input of the automatic wiring model of the simulation chip is the current state of the target wiring agent, the output is the prediction action of the target wiring agent, the wiring from the current position to the next position of the target layout agent can be realized through the prediction action, the next state of the target layout agent is obtained, and the automatic wiring can be realized through iterative operation.
In the embodiment of the invention, a target genetic algorithm is combined with a deep Q network, so that the method is a simulated chip automatic wiring model training method combining reinforcement learning and genetic algorithm.
According to the simulation chip automatic wiring model training method provided by the embodiment of the invention, firstly, sample layout information, sample constraint information and sample netlist information of a simulation chip sample are obtained, and each sample circuit diagram sub-network in the simulation chip sample is determined based on the sample netlist information; then, for any sample circuit diagram sub-network, converting any sample circuit diagram sub-network into each pin pair with priority sequence based on a minimum spanning tree algorithm, and determining wiring path information between each pin pair by adopting a target genetic algorithm; and finally, placing the wiring path information into a playback buffer area of the deep Q network, training the deep Q network based on sample layout information, sample constraint information and sample netlist information to obtain a trained deep Q network, and taking a target strategy network in the trained deep Q network as an automatic wiring model of the simulation chip. According to the training method, the wiring path information obtained by the target genetic algorithm is used as playback experience of the deep Q network, so that the prediction accuracy of the deep Q network can be improved. And the simulation chip sample is divided into various sample circuit diagram sub-networks, and the simulation chip automatic wiring model is obtained by utilizing the training of various sample circuit diagram sub-networks, so that the searching range of a target genetic algorithm and a deep Q network can be reduced, and the training efficiency of the deep Q network can be further improved. The automatic wiring model of the simulation chip obtained by the training method can be suitable for wiring in the range of a circuit diagram sub-network, has a small searching range, can quickly obtain an optimal wiring scheme, can improve wiring efficiency, and provides convenience for quick production and batch application of the simulation chip.
Based on the above embodiment, based on the minimum spanning tree algorithm, converting the arbitrary sample circuit diagram sub-network into a pin pair with priority order, previously includes:
carrying out wiring priority sequencing on the sub-networks of the circuit diagrams of the samples;
and taking each sample circuit diagram sub-network as any sample circuit diagram sub-network in turn according to the order of the priority from high to low.
Specifically, in the embodiment of the present invention, after determining each sample circuit diagram sub-network, the routing priority of each sample circuit diagram sub-network may be first ordered. The criteria for wiring prioritization may be set as desired, and are not particularly limited herein.
Further, steps S12 and S13 may be performed to train and obtain the simulated chip automation wiring model by taking each sample circuit diagram sub-network as any sample circuit diagram sub-network in turn in the order of the priority from high to low.
In the embodiment of the invention, the adverse effect on the wiring result caused by different wiring sequences of each sample circuit diagram subnetwork can be reduced by introducing the wiring priority ordering of each sample circuit diagram subnetwork.
On the basis of the above embodiment, the routing prioritization of the sub-networks of the circuit diagrams of each sample includes:
Determining the electrical signal frequency of each sample circuit diagram sub-network, and determining the wiring priority order of each sample circuit diagram sub-network from high to low based on the order of the electrical signal frequency of each sample circuit diagram sub-network from high to low; or,
determining the line length of each sample circuit diagram sub-network, and determining the wiring priority sequence of each sample circuit diagram sub-network from high to low based on the sequence of the line length of each sample circuit diagram sub-network from short to long.
Specifically, the line length of each sample circuit diagram sub-network may be the sum of the lengths of all flying lines in the sample circuit diagram sub-network, where the length of each flying line may be calculated by the euclidean distance between two pins connected by the flying line.
That is, when wiring each sample circuit pattern sub-network, a first wiring having a high frequency of an electric signal and a second wiring having a low frequency of an electric signal can be selected, and thus, the influence on the sample circuit pattern sub-network wiring having a low frequency electric signal when wiring the sample circuit pattern sub-network having a high frequency electric signal can be avoided, and the wiring quality can be ensured. When each sample circuit diagram subnetwork is wired, the first wiring with short flying line length can be selected, and the second wiring with long flying line length can be selected, so that the situation that the required signal line is lengthened due to the second wiring of the sample circuit diagram subnetwork with short flying line length can be avoided, and the signal line required by wiring can be saved.
Based on the above embodiment, training the deep Q network based on the sample layout information, the sample constraint information and the sample netlist information to obtain a trained deep Q network, including:
determining a sample environment of a sample wiring intelligent agent based on the sample layout information, the sample constraint information and the sample netlist information, and determining a sample action space of the sample wiring intelligent agent;
determining the current state of the sample wiring intelligent body based on the current position of the sample wiring intelligent body on the wiring path information, sending the current state of the sample wiring intelligent body into a strategy network of a depth Q network, and selecting a first action from the sample action space by the strategy network;
based on the sample wiring intelligent agent, the first action and the sample environment are interacted at the current position to obtain the next state of the sample wiring intelligent agent, the next state is input into a value network of a depth Q network to obtain the value of each action in the next state, and the second action with the maximum value in the next state is calculated;
and calculating a total return value corresponding to the current position, calculating a loss function based on the total return value and the second action, and carrying out iterative updating on the structural parameters of the depth Q network based on the loss function to obtain the trained depth Q network.
Specifically, when training the deep Q network, a sample environment of the sample simulation chip wiring can be defined first; defining a sample state space and a sample action space of sample simulation chip wiring corresponding to deep reinforcement learning; and defining a return value calculation function, a value network, a strategy network and related parameters applicable to sample simulation chip wiring.
The sample layout information, the sample constraint information and the sample netlist information can be utilized to determine a sample environment of the sample wiring intelligent agent and determine a sample action space of the sample wiring intelligent agent. The sample environment may include a size of grid (1000 x 1000), a connection relationship between devices in the sample netlist information, sample layout information, sample constraint information, and the like.
The sample state space may be a six-dimensional space, where the six dimensions are three-dimensional position information (x, y, z) of the current point, and three-dimensional distance information (distance_x, distance_y, distance_z) of the current point and the arrival node, respectively.
The sample motion space may also be a six-dimensional space including, but not limited to: upper, lower, front, back, left, right dimensions. Wherein upper and lower represent different wiring layers. For example, CMOS 180nm process has four wiring layers.
The return value calculation function may be:
wherein r is t The total return value of the current position is K, which is a preset threshold value and can be 100, and M is the sum of the return values of all positions before the current position.
This allows the sample wiring agent to learn as much as possible a shortest path because any action that is not productive will make the cumulative prize smaller. In addition, limiting the maximum step length T of the sample wiring agent max . Based on the report value calculation function setting mechanism, the accumulated total report value is always (K-T) max ) Between K, after the action between the pin pairs is completed, if r t =k, explaining the completion of wiring between pin pairs, if r t ＝-T max Indicating that there is no feasible solution between the pin pairs, and the wiring is incomplete.
The value network may comprise a hidden layer and three fully connected layers, the hidden layer having dimensions of hiddimhddimhidimhidimhddim, hidimi, and hidimi may be equal to 128, 64, 32, etc., depending on the size of the analog chip.
Each fully connected layer is followed by an activation function LeakyReLU (x):
wherein c is a constant.
In the deep Q network, an E-greedy strategy is used for action selection:
wherein Q(s) t A; w) is the state s of the current point location t The value of each action a is given, w is the structural parameter of the value network in the deep Q network, and E is a random number.
Thus, when training the deep Q network, the current state of the sample wiring agent is determined using the current position of the sample wiring agent on the wiring path information, and the current state is input to the policy network of the deep Q network.
Thereafter, the policy network may select a first action from the sample action space using the e-greedy policy described above, and based on the sample wiring agent, interact the first action with the sample environment at the current location of the sample wiring agent to obtain a next state s of the sample wiring agent t+1 And will be the next state s t+1 Inputting into a value network of a deep Q network to obtain the next state s t+1 The value Q(s) of each action a t+1 A; w) and calculates a second action argmax having the greatest value in the next state a Q(s t+1 ，a；w)。
Thereafter, the total return value r corresponding to the current position of the sample wiring agent can be calculated by using the return value calculation function t Using the total return value r t Second action argmax a Q(s t+1 A; w), the loss function L is calculated using the following formula:
L＝1/2[y t -Q(s t ，a；w)] 2
y t ＝r t +γ·argmax a Q(s t+1 ，a；w)
wherein γ is a discount factor.
Thereafter, counter-propagating is performed on the depth Q network to obtain a gradient g t ：
Updating the structural parameters of the depth Q network through gradient descent, and iteratively updating the structural parameters of the depth Q network by utilizing the loss function L to ensure that Q (s t A; w) as close as possible to y t 。
And when the iteration termination condition is met, ending the iteration updating process to obtain the trained depth Q network. Here, the iteration termination condition may be that the loss function L converges, or a preset number of iterations is reached.
As shown in fig. 2, on the basis of the above embodiment, the embodiment of the present invention further provides an automatic wiring method for an analog chip, including:
s21, obtaining target layout information, target constraint information and target netlist information of a simulation chip to be wired, and determining each target circuit diagram sub-network in the simulation chip to be wired based on the target netlist information;
s22, for any target circuit diagram sub-network, converting the any target circuit diagram sub-network into pin pairs with priority order based on a minimum spanning tree algorithm, traversing each pin pair, inputting the state of the initial pin in the traversed current pin pair into an analog chip automatic wiring model, obtaining a wiring strategy output by the analog chip automatic wiring model, and performing iterative wiring between the current pin pairs based on the wiring strategy.
Specifically, in the method for automatically wiring an analog chip provided in the embodiment of the present invention, the execution body is an automatic wiring device for an analog chip, and the device may be configured in a computer, where the computer may be a local computer or a cloud computer, and the local computer may be a computer, a tablet, or the like, and is not limited herein specifically.
Step S21 is executed first, and target layout information, target constraint information and target netlist information of the simulated chip to be wired are obtained.
The target layout information may include position information and pin information of each device in the to-be-wired analog chip, the target constraint information may include position information of each device in the to-be-wired analog chip, symmetry information of each device, DRC rule information, and the like, and the target netlist information may include connection relations required for each device in the to-be-wired analog chip. It will be appreciated that each device is an obstacle with respect to the signal lines at the time of wiring, and therefore the positional information of each device is included in the target constraint information to indicate that the devices need to be bypassed at the time of wiring.
Thereafter, each target circuit diagram sub-network in the analog chip to be wired is determined using the target netlist information. The target netlist information may be considered as a whole circuit diagram network, and one or more target circuit diagram sub-networks may be obtained by partitioning the whole circuit diagram network. The division mode of the whole circuit diagram network is consistent with that of the whole sample circuit diagram network.
The devices in each target circuit diagram sub-network are connected through pins. It will be appreciated that different target circuit diagram sub-networks may include the same or different devices, and that the connection of the same devices in different target circuit diagram sub-networks may be implemented using different pins.
And then, executing a step S22, for any target circuit diagram sub-network, converting any target circuit diagram sub-network into each pin pair with priority order based on a minimum spanning tree algorithm, traversing each pin pair, inputting the state of the initial pin in the traversed current pin pair into the simulated chip automatic wiring model, and obtaining the wiring strategy output by the simulated chip automatic wiring model. The routing strategy includes a predictive action of the target routing agent.
Furthermore, with the routing strategy, iterative routing between current pin pairs is possible. The wiring strategy can be used for obtaining the next state, namely wiring is carried out between the current position and the next position, then the current state is updated to be the next state, the current state is continuously input into the automatic wiring model of the simulation chip, the wiring strategy output by the automatic wiring model of the simulation chip is obtained, the process is iteratively executed until the current position is the arrival pin of the current pin pair, and at the moment, the automatic wiring between the current pin pair is completed.
And when wiring is completed among the pin pairs, wiring of the analog chip to be wired is completed.
Thereafter, the disconnection reconnection may be further performed on the portion that does not satisfy the capacity requirement. For example, the edge capacity exceeds the actual capacity, and wire stripping and re-routing are required, after which the final routing result can be obtained.
According to the automatic wiring method for the simulation chip, firstly, target layout information, target constraint information and target netlist information of the simulation chip to be wired are obtained, and each target circuit diagram sub-network in the simulation chip to be wired is determined based on the target netlist information; and then for any target circuit diagram sub-network, converting any target circuit diagram sub-network into each pin pair with priority order based on a minimum spanning tree algorithm, traversing each pin pair, inputting the state of the initial pin in the traversed current pin pair into an automatic wiring model of the simulation chip to obtain a wiring strategy output by the automatic wiring model of the simulation chip, and carrying out iterative wiring between the current pin pairs based on the wiring strategy. The wiring method utilizes the automatic wiring model of the analog chip, can realize the automatic wiring of the analog chip to be wired, can be suitable for wiring in the range of a circuit diagram sub-network, has a small searching range, can quickly obtain an optimal wiring scheme, can improve the wiring efficiency, and provides convenience for the quick production and batch application of the analog chip.
Based on the foregoing embodiment, the automatic wiring method for an analog chip provided in the embodiment of the present invention converts, based on a minimum spanning tree algorithm, the sub-network of any one of the target circuit diagrams into each pin pair having a priority order, including:
Carrying out wiring priority sequencing on each target circuit diagram sub-network;
and taking each target circuit diagram sub-network as any target circuit diagram sub-network in turn according to the order of the priority from high to low.
Specifically, in the embodiment of the present invention, after determining each target circuit diagram sub-network, the routing priority of each target circuit diagram sub-network may be first ordered. The criteria for wiring prioritization may be set as desired, and are not particularly limited herein.
Further, step S22 may be performed by sequentially taking each target circuit diagram sub-network as any target circuit diagram sub-network in order of priority from high to low, so as to implement automatic wiring of the analog chip to be wired.
In the embodiment of the invention, the adverse effect on the wiring result caused by different wiring sequences of each target circuit diagram sub-network can be reduced by introducing the wiring priority ordering of each target circuit diagram sub-network.
On the basis of the embodiment, the automatic wiring method for the analog chip provided by the embodiment of the invention comprises the steps that the wiring strategy comprises the prediction action of the target wiring intelligent agent; inputting the state of the initial pin in the traversed current pin pair to an analog chip automatic wiring model to obtain a wiring strategy output by the analog chip automatic wiring model, and performing iterative wiring between the current pin pair based on the wiring strategy, wherein the method comprises the following steps:
Determining a target environment of the target wiring agent based on the target layout information, the target constraint information and the target netlist information;
determining the current position of the target wiring intelligent body based on the state of the starting pin, determining the current state of the target wiring intelligent body based on the current position, interacting the predicted action with the target environment at the current position based on the target wiring intelligent body to obtain the next state of the target wiring intelligent body, iteratively inputting the next state into the simulated chip automatic wiring model, and updating the predicted action of the target wiring intelligent body until the current position is the arrival pin of the current pin pair.
Specifically, as shown in fig. 3, when iterative routing is performed between pin pairs, a target environment of a target routing agent may be determined according to target layout information, target constraint information, and target netlist information. Furthermore, a target state space may be determined, which is identical to the sample state space.
The target environment may include a size of grid, a connection relationship between devices in the target netlist information, target layout information, target constraint information, and the like.
And then, utilizing the target wiring intelligent agent to interact the predicted action with the target environment at the current position to obtain the next state, and iteratively inputting the next state into the simulated chip automatic wiring model to update the predicted action of the target wiring intelligent agent until the current position is an arrival pin in the current pin pair.
As shown in fig. 4, taking automatic wiring for the pins a and B on the second Layer in the analog chip to be wired as an example, since each Layer is intelligently wired in one direction during wiring, for example, the first Layer (Layer 1) is wired in the vertical direction, and the second Layer (Layer 2) is wired in the horizontal direction, the first Layer and the second Layer can be wired through the through holes (via), and then the target wiring agent starts the signal line from the pin a, enters the first Layer through the first through holes (via 1), enters the second Layer through the second through holes (via 2), enters the first Layer through the third through holes (via 3), and enters the second Layer through the fourth through holes (via 4) and is connected with the pin B.
As shown in fig. 5, the structure diagram of the target minimum spanning tree formed by each pin Pair obtained by converting any target circuit diagram sub-network is shown, and two adjacent nodes in the target minimum spanning tree form one pin Pair, for example, pair1, pair2, pair3 in fig. 5, and the like.
As shown in fig. 6, on the basis of the above embodiment, an embodiment of the present invention provides an apparatus for training an automated wiring model of an analog chip, including:
a first information obtaining module 61, configured to obtain sample layout information, sample constraint information, and sample netlist information of a sample of a simulation chip, and determine a sub-network of each sample circuit diagram in the sample of the simulation chip based on the sample netlist information;
a routing path determining module 62, configured to, for any sample circuit diagram subnet, convert the any sample circuit diagram subnet into each pin pair having a priority order based on a minimum spanning tree algorithm, and determine routing path information between each pin pair by adopting a target genetic algorithm;
the model training module 63 is configured to put the routing path information into a playback buffer of the deep Q network, train the deep Q network based on the sample layout information, the sample constraint information and the sample netlist information, obtain a trained deep Q network, and use a target strategy network in the trained deep Q network as an automatic routing model of the simulation chip.
On the basis of the above embodiment, the device for training an automatic wiring model of an analog chip provided in the embodiment of the present invention further includes a first ordering module, configured to:
Carrying out wiring priority sequencing on the sub-networks of the circuit diagrams of the samples;
and taking each sample circuit diagram sub-network as any sample circuit diagram sub-network in turn according to the order of the priority from high to low.
On the basis of the foregoing embodiments, the device for training an automatic wiring model of an analog chip provided in the embodiment of the present invention, where the first sorting module is specifically configured to:
determining the electrical signal frequency of each sample circuit diagram sub-network, and determining the wiring priority order of each sample circuit diagram sub-network from high to low based on the order of the electrical signal frequency of each sample circuit diagram sub-network from high to low; or,
determining the line length of each sample circuit diagram sub-network, and determining the wiring priority sequence of each sample circuit diagram sub-network from high to low based on the sequence of the line length of each sample circuit diagram sub-network from short to long.
On the basis of the above embodiment, the device for training an automatic wiring model of an analog chip provided in the embodiment of the present invention is specifically configured to:
determining a sample environment of a sample wiring intelligent agent based on the sample layout information, the sample constraint information and the sample netlist information, and determining a sample action space of the sample wiring intelligent agent;
Determining the current state of the sample wiring intelligent body based on the current position of the sample wiring intelligent body on the wiring path information, sending the current state of the sample wiring intelligent body into a strategy network of a depth Q network, and selecting a first action from the sample action space by the strategy network;
based on the sample wiring intelligent agent, the first action and the sample environment are interacted at the current position to obtain the next state of the sample wiring intelligent agent, the next state is input into a value network of a depth Q network to obtain the value of each action in the next state, and the second action with the maximum value in the next state is calculated;
and calculating a total return value corresponding to the current position, calculating a loss function based on the total return value and the second action, and carrying out iterative updating on the structural parameters of the depth Q network based on the loss function to obtain the trained depth Q network.
On the basis of the above embodiment, the device for training an automatic wiring model of an analog chip provided in the embodiment of the present invention, the model training module is further specifically configured to:
if the current position is an arrival pin in the pin pair, determining that the total return value corresponding to the current position is a preset value;
And if the current position is a non-arrival pin, determining that the total return value corresponding to the current position is the sum of the return value of the current position and the return values of all positions before the current position.
Specifically, the functions of each module in the simulation chip automatic wiring model training device provided in the embodiment of the present invention are in one-to-one correspondence with the operation flow of each step in the above method embodiment, and the achieved effects are consistent.
As shown in fig. 7, on the basis of the above embodiment, an embodiment of the present invention further provides an automatic wiring device for an analog chip, including:
a second information obtaining module 71, configured to obtain target layout information, target constraint information, and target netlist information of a to-be-wired analog chip, and determine each target circuit diagram sub-network in the to-be-wired analog chip based on the target netlist information;
and the automated wiring module 72 is configured to, for any target circuit diagram sub-network, convert the any target circuit diagram sub-network into each pin pair with a priority order based on a minimum spanning tree algorithm, traverse each pin pair, input the state of the starting pin in the traversed current pin pair to the simulated chip automated wiring model, obtain the wiring strategy output by the simulated chip automated wiring model, and perform iterative wiring between the current pin pairs based on the wiring strategy.
On the basis of the above embodiment, the automatic wiring device for an analog chip provided in the embodiment of the present invention further includes a second sorting module, configured to:
carrying out wiring priority sequencing on each target circuit diagram sub-network;
and taking each target circuit diagram sub-network as any target circuit diagram sub-network in turn according to the order of the priority from high to low.
On the basis of the above embodiment, the automatic wiring device for an analog chip provided in the embodiment of the present invention is specifically configured to:
determining a target environment of the target wiring agent based on the target layout information, the target constraint information and the target netlist information;
determining the current position of the target wiring intelligent body based on the state of the starting pin, determining the current state of the target wiring intelligent body based on the current position, interacting the predicted action with the target environment at the current position based on the target wiring intelligent body to obtain the next state of the target wiring intelligent body, iteratively inputting the next state into the simulated chip automatic wiring model, and updating the predicted action of the target wiring intelligent body until the current position is the arrival pin of the current pin pair.
Specifically, the functions of each module in the automatic wiring device for the analog chip provided in the embodiment of the present invention are in one-to-one correspondence with the operation flows of each step in the above method embodiment, and the achieved effects are consistent.
Fig. 8 illustrates a physical structure diagram of an electronic device, as shown in fig. 8, which may include: processor 810, communication interface (Communications Interface) 820, memory 830, and communication bus 840, wherein Processor 810, communication interface 820, memory 830 accomplish communication with each other through communication bus 840. The processor 810 may invoke logic instructions in the memory 830 to perform the simulated chip automated wiring model training method or the simulated chip automated wiring method provided in the embodiments described above.
Further, the logic instructions in the memory 830 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, and when the computer program is executed by a processor, the computer can execute the simulated chip automated wiring model training method or the simulated chip automated wiring method provided in the foregoing embodiments.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the simulated chip automated wiring model training method or the simulated chip automated wiring method provided in the above embodiments.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. An automated wiring model training method for an analog chip is characterized by comprising the following steps:
sample layout information, sample constraint information and sample netlist information of a simulation chip sample are obtained, and each sample circuit diagram sub-network in the simulation chip sample is determined based on the sample netlist information;
for any sample circuit diagram sub-network, converting the any sample circuit diagram sub-network into each pin pair with priority sequence based on a minimum spanning tree algorithm, and determining wiring path information between each pin pair by adopting a target genetic algorithm;
and placing the wiring path information into a playback buffer area of a deep Q network, training the deep Q network based on the sample layout information, the sample constraint information and the sample netlist information to obtain a trained deep Q network, and taking a target strategy network in the trained deep Q network as an automatic wiring model of the simulation chip.
2. The method of claim 1, wherein converting the arbitrary sample circuit diagram sub-network into pin pairs with priority order based on a minimum spanning tree algorithm, previously comprises:
Carrying out wiring priority sequencing on the sub-networks of the circuit diagrams of the samples;
and taking each sample circuit diagram sub-network as any sample circuit diagram sub-network in turn according to the order of the priority from high to low.
3. The method of training an automated wiring model for a simulation chip of claim 2, wherein prioritizing wiring for each of the sub-networks of sample circuit diagrams comprises:
determining the electrical signal frequency of each sample circuit diagram sub-network, and determining the wiring priority order of each sample circuit diagram sub-network from high to low based on the order of the electrical signal frequency of each sample circuit diagram sub-network from high to low; or,
determining the line length of each sample circuit diagram sub-network, and determining the wiring priority sequence of each sample circuit diagram sub-network from high to low based on the sequence of the line length of each sample circuit diagram sub-network from short to long.
4. The method for training an automated wiring model for a simulation chip according to any one of claims 1 to 3, wherein training the depth Q network based on the sample layout information, the sample constraint information, and the sample netlist information to obtain a trained depth Q network comprises:
Determining a sample environment of a sample wiring intelligent agent based on the sample layout information, the sample constraint information and the sample netlist information, and determining a sample action space of the sample wiring intelligent agent;
determining the current state of the sample wiring intelligent body based on the current position of the sample wiring intelligent body on the wiring path information, sending the current state of the sample wiring intelligent body into a strategy network of a depth Q network, and selecting a first action from the sample action space by the strategy network;
based on the sample wiring intelligent agent, the first action and the sample environment are interacted at the current position to obtain the next state of the sample wiring intelligent agent, the next state is input into a value network of a depth Q network to obtain the value of each action in the next state, and the second action with the maximum value in the next state is calculated;
and calculating a total return value corresponding to the current position, calculating a loss function based on the total return value and the second action, and carrying out iterative updating on the structural parameters of the depth Q network based on the loss function to obtain the trained depth Q network.
5. The method for training an automated wiring model for a simulation chip according to claim 4, wherein calculating the total return value corresponding to the current position comprises:
if the current position is an arrival pin in the pin pair, determining that the total return value corresponding to the current position is a preset value;
and if the current position is a non-arrival pin, determining that the total return value corresponding to the current position is the sum of the return value of the current position and the return values of all positions before the current position.
6. An automated wiring method for an analog chip, comprising:
acquiring target layout information, target constraint information and target netlist information of a simulation chip to be wired, and determining each target circuit diagram sub-network in the simulation chip to be wired based on the target netlist information;
for any target circuit diagram sub-network, converting the any target circuit diagram sub-network into each pin pair with priority order based on a minimum spanning tree algorithm, traversing each pin pair, inputting the state of the initial pin in the traversed current pin pair into an analog chip automatic wiring model to obtain a wiring strategy output by the analog chip automatic wiring model, and carrying out iterative wiring between the current pin pairs based on the wiring strategy.
7. The method of automated wiring for an analog chip according to claim 6, wherein converting the arbitrary target circuit diagram sub-network into pin pairs having a priority order based on a minimum spanning tree algorithm, previously comprises:
carrying out wiring priority sequencing on each target circuit diagram sub-network;
and taking each target circuit diagram sub-network as any target circuit diagram sub-network in turn according to the order of the priority from high to low.
8. The method of automated wiring for an analog chip according to claim 6, wherein the wiring strategy comprises a predictive action of a target wiring agent; inputting the state of the initial pin in the traversed current pin pair to an analog chip automatic wiring model to obtain a wiring strategy output by the analog chip automatic wiring model, and performing iterative wiring between the current pin pair based on the wiring strategy, wherein the method comprises the following steps:
determining a target environment of the target wiring agent based on the target layout information, the target constraint information and the target netlist information;
determining the current position of the target wiring intelligent body based on the state of the starting pin, determining the current state of the target wiring intelligent body based on the current position, interacting the predicted action with the target environment at the current position based on the target wiring intelligent body to obtain the next state of the target wiring intelligent body, iteratively inputting the next state into the simulated chip automatic wiring model, and updating the predicted action of the target wiring intelligent body until the current position is the arrival pin of the current pin pair.
9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the simulated chip automated wiring model training method of any of claims 1-5 or the simulated chip automated wiring method of any of claims 6-8 when the computer program is executed.
10. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the simulated chip automated wiring model training method of any of claims 1-5 or the simulated chip automated wiring method of any of claims 6-8.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117829085A (en) * | 2024-03-04 | 2024-04-05 | 中国科学技术大学 | Connection diagram generation method suitable for chip wiring |
| CN117972812A (en) * | 2024-03-26 | 2024-05-03 | 中国石油大学(华东) | Engineering drawing layout optimization method, device, equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117829085A (en) * | 2024-03-04 | 2024-04-05 | 中国科学技术大学 | Connection diagram generation method suitable for chip wiring |
| CN117829085B (en) * | 2024-03-04 | 2024-05-17 | 中国科学技术大学 | Connection diagram generation method suitable for chip wiring |
| CN117972812A (en) * | 2024-03-26 | 2024-05-03 | 中国石油大学(华东) | Engineering drawing layout optimization method, device, equipment and medium |
| CN117972812B (en) * | 2024-03-26 | 2024-06-07 | 中国石油大学(华东) | Engineering drawing layout optimization method, device, equipment and medium |
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