CN117425336A - Memory cell, array and manufacturing method of memory cell - Google Patents

Abstract

The embodiment of the application relates to a semiconductor technology and discloses a memory cell, an array and a manufacturing method of the memory cell, wherein the memory cell comprises the following components: a reference voltage layer, a read transistor, a read bit line, a read word line, a read bit line, a write transistor, a write bit line, and a write word line stacked on a substrate; the read transistor channel layer surrounds the side wall of the first grid electrode of the read transistor, the second grid electrode of the read transistor surrounds the periphery of the outer side of the read transistor channel layer, and the second grid electrode is connected with the read word line; the read bit line extends in a first direction parallel to the substrate plane; forming a surrounding channel layer around the third gate side wall by the channel layer of the write transistor; the writing bit line is wound around the outer periphery of the writing transistor channel layer and extends along a first direction; the write transistor channel layer is connected with the first grid electrode; the read word line and the write word line extend in a second direction parallel to the substrate plane. The embodiment scheme enables the memory cell to be manufactured easily, reduces the size of the memory cell, supports multiple stacking, and increases the memory density, thereby reducing the production cost.

Description

Memory cell, array and manufacturing method of memory cell

Technical Field

Embodiments of the present disclosure relate to semiconductor technology, and more particularly, to a memory cell, an array, and a method for manufacturing the memory cell.

Background

Conventional memory cells for Dynamic Random Access Memory (DRAM) include a transistor and a capacitor, and the capacitor of the conventional memory cell cannot be significantly reduced, and it is difficult to reduce the cost.

The 2T0C structure memory cell does not have the problem, the read operation is non-destructive, the problem that the capacitance in the 1T1C structure memory cell cannot be small is solved, and a novel 2T0C memory cell containing an auxiliary grid is provided, which is an energy-saving, high-density and integrated structure. However, the process of such a 2T0C memory cell is difficult to realize, and no suitable manufacturing method is currently available for manufacturing such a 2T0C memory cell.

Disclosure of Invention

The embodiment of the application provides a memory cell, an array and a manufacturing method of the memory cell, which can be manufactured easily, reduce the size of the memory cell, support multiple stacking, increase the memory density and reduce the production cost.

The embodiment of the application provides a memory cell, which may include:

a reference voltage layer M disposed on the substrate;

a read transistor tr_r;

read bit line R_BL;

a read word line R_WL;

a write transistor tr_w;

write bit line w_bl; the method comprises the steps of,

write word line w_wl;

the reference voltage layer M, the read transistor tr_r, the read word line r_wl, the read bit line r_bl, the write transistor tr_w, the write word line w_wl and the write bit line w_bl are stacked on the substrate;

a surrounding channel layer is formed on the side wall of the first grid G1 of the read transistor TR_R in a surrounding mode, and the first grid G1 serves as a storage node; the second gate G2 of the read transistor tr_r surrounds the outer periphery of the channel layer of the read transistor tr_r, and the second gate G2 is connected to the read word line r_wl; the read bit line R_BL extends along a first direction on a plane parallel to the substrate;

forming a surrounding channel layer around the side wall of the third gate G3 of the write transistor TR_W by the channel layer of the write transistor TR_W; the write bit line w_bl surrounds the outer periphery of the channel layer of the write transistor tr_w, and extends in a first direction on a plane parallel to the substrate; the channel layer of the write transistor tr_w is connected to the first gate G1;

the read word line r_wl extends in a second direction on a plane parallel to the substrate;

the write word line w_wl extends in a second direction on a plane parallel to the substrate.

In an exemplary embodiment of the present application, a first gate medium GM1 is disposed between the first gate G1 and the channel layer of the read transistor tr_r;

a second gate medium GM2 is disposed between the second gate G2 and the channel layer of the read transistor tr_r;

a third gate medium GM2 is disposed between the third gate G3 and the channel layer of the write transistor tr_w.

In an exemplary embodiment of the present application, a length direction of a channel layer of the read transistor tr_r and a length direction of the first gate G1 are perpendicular to the substrate;

the length direction of the channel layer of the write transistor tr_w and the length direction of the third gate G3 are perpendicular to the substrate.

The embodiment of the application also provides a memory array which can comprise a plurality of memory cells.

The embodiment of the application also provides a manufacturing method of the memory cell, and based on the memory cell, the method comprises the following steps:

sequentially stacking a reference voltage layer, a sacrificial layer and a read bit line of the memory cell on a substrate;

setting a channel layer of a read transistor of the memory cell, and setting a first gate medium and a first gate of the read transistor in the channel layer of the read transistor;

setting a mask, removing the sacrificial layer, growing a second gate medium and a second gate of the read transistor, and generating a read word line;

removing the mask and setting a write bit line above the first gate;

setting a channel layer of a write transistor of the memory cell, and setting a third gate medium and a third gate corresponding to the write transistor in the channel layer of the write transistor;

and a writing line is arranged above the third grid electrode.

In an exemplary embodiment of the present application, the sequentially stacking the reference voltage layer, the sacrificial layer and the read bit line of the memory cell on the substrate may include:

disposing the reference voltage layer on the substrate;

growing a first layer of insulating medium, and carrying out planarization treatment on the reference voltage layer and the first layer of insulating medium so that the reference voltage layer is flush with the upper surface of the first layer of insulating medium;

forming the sacrificial layer; the sacrificial layer extends in a second direction on a plane parallel to the substrate;

growing a second layer of insulating medium, and carrying out planarization treatment on the sacrificial layer and the second layer of insulating medium so that the sacrificial layer is flush with the upper surface of the second layer of insulating medium;

disposing the read bit line on the sacrificial layer such that the read bit line extends in a first direction on a plane parallel to the substrate;

and growing a third layer of insulating medium, and carrying out planarization treatment on the read bit line and the third layer of insulating medium so that the read bit line is flush with the upper surface of the third layer of insulating medium.

In an exemplary embodiment of the present application, the disposing a channel layer of a read transistor of the memory cell, disposing a first gate dielectric and a first gate of the read transistor in the channel layer of the read transistor may include:

etching downwards from the upper surface of the read bit line, and etching a first hole penetrating through the read bit line and the sacrificial layer until reaching the upper surface of the reference voltage layer;

providing a channel layer of the read transistor on an inner wall of the first hole;

growing a first gate dielectric on the inner wall of the channel layer of the read transistor;

the first gate is grown within a space surrounded by the first gate dielectric.

In an exemplary embodiment of the present application, the disposing a mask, removing the sacrificial layer, growing the second gate dielectric and the second gate of the read transistor, and generating the read word line may include:

disposing the mask on the first gate;

etching all the sacrificial layers by adopting an etching technology, and etching part of the third layer insulating medium around the read bit line;

growing a layer of second gate dielectric in a space formed after etching away the sacrificial layer and part of the third layer of insulating dielectric;

growing a second gate in a space surrounded by the second gate dielectric;

etching the second grid electrode to a required size, enabling the second grid electrode to extend along a second direction on a plane parallel to the substrate, and growing a fourth layer of insulating medium in a space where the second grid electrode is etched;

and the area where the second gates of different read transistors are connected with each other is used as the read word line.

In an exemplary embodiment of the present application, the disposing a write bit line above the first gate may include:

providing a write bit line on the first gate, such that the write bit line extends in a first direction on a plane parallel to the substrate;

and growing a fifth-layer insulating medium, and carrying out planarization treatment on the write bit line and the fifth-layer insulating medium so that the write bit line is flush with the upper surface of the fifth-layer insulating medium.

In an exemplary embodiment of the present application, the disposing a channel layer of a write transistor of the memory cell, disposing a third gate medium and a third gate corresponding to the write transistor in the channel layer of the write transistor may include:

etching downwards from the upper surface of the write bit line to form a second hole penetrating through the write bit line to the upper surface of the first grid electrode;

setting a channel layer of the write transistor on the inner wall of the second hole, and connecting the channel layer of the write transistor with the first grid electrode;

growing a third gate dielectric on the inner wall of the channel layer of the write transistor;

and growing the third grid in the space surrounded by the third grid dielectric.

Compared with the related art, the memory cell of the embodiment of the present application may include: a reference voltage layer, a read transistor, a read bit line, a read word line, a write transistor, a write bit line, and a write word line disposed on the substrate; the reference voltage layer, the read transistor, the read word line, the read bit line, the write transistor, the write word line and the write bit line are stacked on the substrate; forming a surrounding channel layer on the side wall of a first grid electrode of the reading transistor, wherein the surrounding channel layer surrounds the channel layer of the reading transistor, and the first grid electrode is used as a storage node; the second grid electrode of the reading transistor surrounds the periphery of the outer side of the channel layer of the reading transistor, and is connected with the reading word line; the read bit line extends in a first direction on a plane parallel to the substrate; forming a surrounding channel layer around the side wall of the third grid electrode of the writing transistor by the channel layer of the writing transistor; the writing bit line is wound around the outer periphery of the channel layer of the writing transistor and extends along a first direction on a plane parallel to the substrate; the channel layer of the write transistor is connected with the first grid electrode; the read word line extends in a second direction on a plane parallel to the substrate; the write word line extends in a second direction on a plane parallel to the substrate. By the embodiment, the manufacturing is easy, the size of the storage unit is reduced, multiple stacking is supported, the storage density is increased, and therefore the production cost is reduced.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

FIG. 1 is a schematic diagram of a memory cell structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memory array with write bit line W_BL and read bit line R_BL separately arranged according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a memory array with a combination of write bit line W_BL and read bit line R_BL according to an embodiment of the present application;

FIG. 4 is a flowchart of a method for fabricating a memory cell according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the arrangement of the reference voltage layer and the sacrificial layer according to the embodiment of the present application;

FIG. 6 is a schematic diagram illustrating a read bit line configuration in an embodiment of the present application;

FIG. 7 is a schematic view of a first hole arrangement in accordance with an embodiment of the present application;

FIG. 8 is a schematic diagram of a first channel arrangement in an embodiment of the present application;

FIG. 9 is a schematic diagram of a first gate dielectric and a first gate arrangement according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a mask arrangement according to an embodiment of the present application;

FIG. 11 is a schematic view of removing a sacrificial layer and a portion of a third insulating medium according to an embodiment of the present disclosure;

fig. 12 is a schematic diagram of a second gate dielectric arrangement according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a read word line and a second gate arrangement in an embodiment of the present application;

FIG. 14 is a schematic diagram of a read wordline after trimming in an embodiment of the present application;

FIG. 15 is a schematic diagram of an embodiment of the present application after mask removal;

FIG. 16 is a schematic diagram of a write bit line setup in an embodiment of the present application;

FIG. 17 is a schematic diagram of a second hole arrangement in accordance with an embodiment of the present application;

FIG. 18 is a schematic diagram of a second channel layer, a third gate dielectric, and a third gate arrangement according to an embodiment of the present disclosure;

fig. 19 is a schematic diagram of a write word line arrangement in an embodiment of the present application.

Detailed Description

The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

An embodiment of the present application provides a memory cell, as shown in fig. 1, may include:

a reference voltage layer M disposed on the substrate;

a read transistor tr_r;

read bit line R_BL;

a read word line R_WL;

a write transistor tr_w;

write bit line w_bl; the method comprises the steps of,

write word line w_wl;

the reference voltage layer M, the read transistor tr_r, the read word line r_wl, the read bit line r_bl, the write transistor tr_w, the write word line w_wl and the write bit line w_bl are stacked on the substrate.

In an exemplary embodiment of the present application, the channel layer of the read transistor tr_r may be referred to as a first channel layer CH1, and the channel layer of the write transistor may be referred to as a second channel layer CH2; the read transistor tr_r may include a first channel layer CH1, a first gate G1, and a second gate G2, and the write transistor tr_w may include a second channel layer CH2 and a third gate G3;

a channel layer (i.e., a first channel layer CH 1) of the read transistor tr_r surrounds a sidewall of a first gate G1 of the read transistor tr_r to form a surrounding channel layer, and the first gate G1 serves as a storage node; the second gate G2 of the read transistor tr_r surrounds the outer periphery of the channel layer of the read transistor tr_r, and the second gate G2 is connected to the read word line r_wl; the read bit line R_BL extends along a first direction on a plane parallel to the substrate;

a channel layer (i.e., a second channel layer) of the write transistor tr_w surrounds a sidewall of the third gate G3 of the write transistor tr_w to form a surrounding channel layer; the write bit line w_bl surrounds the outer periphery of the channel layer of the write transistor tr_w, and extends in a first direction on a plane parallel to the substrate; the channel layer of the write transistor tr_w is connected to the first gate G1.

In the exemplary embodiment of the present application, a first gate medium GM1 is disposed between the first gate G1 and the channel layer (first channel layer CH 1) of the read transistor tr_r;

a second gate medium GM2 is disposed between the second gate G2 and the channel layer (first channel layer CH 1) of the read transistor tr_r;

a third gate dielectric GM2 is disposed between the third gate G3 and the channel layer (second channel layer CH 2) of the write transistor tr_w.

In an exemplary embodiment of the present application, a length direction of a channel layer of the read transistor tr_r and a length direction of the first gate G1 are perpendicular to the substrate;

the length direction of the channel layer of the write transistor tr_w and the length direction of the third gate G3 are perpendicular to the substrate;

the read word line r_wl extends in a second direction on a plane parallel to the substrate;

the write word line w_wl extends in a second direction on a plane parallel to the substrate.

In an exemplary embodiment of the present application, the memory cells may be stacked in multiple layers.

In an exemplary embodiment of the present application, the write transistor tr_w may be located above the read transistor tr_r, and an embodiment of the present application will be described below taking the write transistor tr_w located above the read transistor tr_r as an example.

In the exemplary embodiment of the present application, the write transistor tr_w is located above the read transistor tr_r, which is advantageous in saving area and improving the structure density.

In the exemplary embodiment of the present application, the first end of the first channel layer CH1 serves as the first pole P1 of the read transistor tr_r, and the second end of the first channel layer CH1 serves as the second pole P2 of the read transistor tr_r; one of the first pole P1 and the second pole P2 serves as a source of the read transistor tr_r, and the other serves as a drain of the read transistor tr_r;

a first end of the second channel layer CH2 is used as the third pole P3, and a second end of the second channel layer CH2 is used as the fourth pole P4; the third pole P3 and the fourth pole P4 serve as the source of the write transistor tr_w and the other as the drain of the write transistor tr_w.

In the exemplary embodiment of the present application, the read transistor tr_r and the write transistor tr_w may each be an N-type transistor, may each be a P-type transistor, may each be an N-type transistor, and may each be a P-type transistor, and the selection of the types of the read transistor tr_r and the write transistor tr_w is not limited.

In an exemplary embodiment of the present application, the first pole P1, the second pole P2, the third pole P3, and the fourth pole P4 as sources or drains may be determined according to the selection type of the read transistor tr_r and the write transistor tr_w.

In an exemplary embodiment of the present application, the first electrode P1 may be connected to a read bit line r_bl, the second electrode P2 is connected to a reference voltage layer M, the first gate G1 is used as a storage node and is disposed in the first channel layer CH1, a first gate medium GM1 is disposed between the first gate G1 and the first channel layer CH1, the second gate G2 is located below the read bit line r_bl, the second gate G2 is disposed around the first channel layer CH1, a second gate medium GM2 is disposed between the second gate G2 and the first channel layer, and an area where the second gates G2 of different read transistors tr_r are connected to each other is used as a read word line r_wl; a vertical distance between an upper surface of the read word line r_wl and a lower surface of the read bit line r_bl is used as a gate length of the first gate G1 of the read transistor;

the third pole P3 is connected with the write bit line W_BL, the fourth pole P4 is connected with the first grid G1, and the third grid G3 is connected with the write word line W_WL; the distance between the upper surface of the first gate G1 and the lower surface of the write bit line w_bl is the gate length of the third gate G3 of the write transistor.

The embodiment of the application also provides a memory array which can comprise a plurality of memory cells.

In the exemplary embodiment of the present application, the read bit line r_bl included in the read transistor tr_r and the write bit line w_bl included in the write transistor tr_w in the memory cell may be respectively disposed in the peripheral area of the memory array, or may share one common bit line BL; as shown in fig. 2 and 3.

In an exemplary embodiment of the present application, fig. 2 is a schematic diagram of a memory array in which a write bit line w_bl and a read bit line r_bl are separately disposed, where w_bl1, w_bl2, w_bl3, …, w_bln refer to different write bit lines, and n is a positive integer; R_BL1, R_BL2, R_BL3, …, R_BLn refer to different read bit lines; W_WL1, W_WL2, W_WL3, …, W_WLm refer to different write word lines, y is a positive integer; R_WL1, R_WL2, R_WL3, …, R_WLm refer to different read word lines.

In an exemplary embodiment of the present application, fig. 3 is a schematic diagram of a memory array in which a write bit line w_bl and a read bit line r_bl are combined, where BL1, BL2, BL3, …, BLn refer to different common bit lines, and n is a positive integer; W_WL1, W_WL2, W_WL3, …, W_WLm refer to different write word lines, m is a positive integer; R_WL1, R_WL2, R_WL3, …, R_WLm refer to different read word lines.

In the exemplary embodiment of the present application, the first gate G1 (as a storage node) in each of the storage units in fig. 2 and 3 is represented by a capacitance symbol, which does not represent capacitance here, for convenience of viewing.

In the exemplary embodiment of the application, by combining the read bit line r_bl and the write bit line w_bl, only one via hole is needed, and the two bit lines overlap and share one common bit line BL, so that the actually occupied area is only the area of one tube, and the read bit line r_bl and the write bit line w_bl are connected together at the periphery of the memory array, so that the structure density is greatly improved, the technical foundation is provided for the commercialization of the embodiment of the application, and the practicability of the memory array of the embodiment of the application is improved.

The embodiment of the application also provides a manufacturing method of the memory cell, based on the memory cell, as shown in fig. 4, the method comprises steps S101-S106:

s101, a reference voltage layer M, a sacrificial layer S and a read bit line R_BL of the memory cell are sequentially stacked and arranged on a substrate.

In an exemplary embodiment of the present application, as shown in fig. 5 and 6, the sequentially stacking the reference voltage layer M, the sacrificial layer S, and the read bit line r_bl of the memory cell on the substrate may include:

disposing the reference voltage layer M on the substrate;

growing a first insulating medium CM1, and flattening the reference voltage layer M and the first insulating medium CM1 so that the reference voltage layer M is flush with the upper surface of the first insulating medium CM 1;

forming the sacrificial layer S;

growing a second layer of insulating medium CM2 (not shown in the figure due to shielding of the sacrificial layer), and performing planarization treatment on the sacrificial layer S and the second layer of insulating medium CM2 so that the sacrificial layer S is flush with the upper surface of the second layer of insulating medium CM 2;

setting the read bit line R_BL on the sacrificial layer, so that the read bit line R_BL extends along a first direction on a plane parallel to the substrate;

and growing a third layer of insulating medium CM3, and carrying out planarization treatment on the read bit line R_BL and the third layer of insulating medium CM3 so that the read bit line R_BL is flush with the upper surface of the third layer of insulating medium CM 3.

In exemplary embodiments of the present application, materials for the sacrificial layer may include, but are not limited to, siGe and polysilicon.

In an exemplary embodiment of the present application, a dummy, replaceable read word line r_wl may be provided using doped Si and SiGe growth techniques with SiGe as the sacrificial layer.

In an exemplary embodiment of the present application, the detailed arrangement of the reference voltage layer M, the sacrificial layer and the read bit line r_bl may include, but is not limited to, deposition, photolithography, etching, planarization, and the like.

S102, a channel layer (namely a first channel layer CH 1) of a read transistor TR_R of the memory cell is arranged, and a first gate medium GM1 and a first gate G1 of the read transistor are arranged in the channel layer of the read transistor.

In an exemplary embodiment of the present application, the disposing the channel layer of the read transistor tr_r of the memory cell, and disposing the first gate dielectric GM1 and the first gate G1 of the read transistor in the channel layer of the read transistor may include:

etching downwards from the upper surface of the read bit line R_BL to form a first hole H1 penetrating through the read bit line R_BL and the sacrificial layer to the upper surface of the reference voltage layer M, as shown in FIG. 7;

a channel layer of the read transistor (i.e., a first channel layer CH 1) is disposed on an inner wall of the first hole H1, as shown in fig. 8;

growing a first gate dielectric GM1 on the inner wall of the channel layer of the read transistor, as shown in FIG. 9;

the first gate G1 is grown in the space surrounded by the first gate dielectric GM1 as shown in fig. 9.

In an exemplary embodiment of the present application, the first hole H1 may be disposed in a manner including, but not limited to, photolithography, etching, and the like.

In an exemplary embodiment of the present application, an ALD (atomic layer deposition ) method may be used to sequentially deposit the first channel layer CH1 and the first gate dielectric GM1 on the inner wall of the first hole H1, and a first conductive material, for example, a conductive metal material, may be grown in the cavity of the first gate dielectric GM1 as the first gate G1.

In an exemplary embodiment of the present application, the first channel layer CH1 may be provided using IGZO (indium gallium zinc oxide ), poly (polysilicon), silicon (silicon-based material), or the like.

S103, setting a mask YM, removing the sacrificial layer S, growing a second gate dielectric GM2 and a second gate G2 of the read transistor, and generating a read word line R_WL.

In an exemplary embodiment of the present application, the setting the mask YM, removing the sacrificial layer S, growing the second gate dielectric GM2 and the second gate G2 of the read transistor, and generating the read word line r_wl may include:

the mask YM is provided on the first gate G1 as shown in fig. 10;

etching all the sacrificial layer S by adopting an etching technology, and etching part of the third layer insulating medium CM3 around the read bit line R_BL, as shown in FIG. 11;

growing a layer of second gate dielectric GM2 in the space formed after etching the sacrificial layer S and the third layer of insulating dielectric CM3, as shown in fig. 12;

growing a second gate G2 in a space surrounded by the second gate dielectric GM2, as shown in FIG. 13;

etching the second gate G2 to a desired size, as shown in fig. 14, such that the second gate G2 extends in a second direction on a plane parallel to the substrate, and growing a fourth layer of insulating medium in a space where the second gate is etched;

the region where the second gates of different read transistors are connected to each other is referred to as the read word line r_wl.

In an exemplary embodiment of the present application, the mask YM may be a flexible mask, and the mask YM may mask an upper surface of the first gate G1.

In an exemplary embodiment of the present application, the sacrificial layer S may be removed by photolithography or etching technology, for example, a wet etching technology may be used to remove the sacrificial layer S.

In an exemplary embodiment of the present application, a layer of the second gate dielectric GM2 may be grown by an ALD method, the second gate G2 may be grown by an ALD method by extending the second gate G2 from the space surrounded by the second gate dielectric GM2, and the size of the second gate G2 may be cut, as shown in fig. 14, the second gate G2 with the required size may be etched, and the fourth insulating dielectric CM4 may be grown in the space after the second gate G2 is etched.

In an exemplary embodiment of the present application, a support structure may be provided for the read transistor tr_r that has been provided when the sacrificial layer S is removed.

In an exemplary embodiment of the present application, a distance between an upper surface of the second gate dielectric GM2 and a lower surface of the read bit line r_bl is a gate length of the first gate G1 of the read transistor.

S104, the mask is removed (as shown in fig. 15), and a write bit line w_bl is disposed above the first gate G1.

In an exemplary embodiment of the present application, as shown in fig. 16, the setting the write bit line w_bl above the first gate G1 may include:

setting a write bit line W_BL on the first gate G1, so that the write bit line W_BL extends along a first direction on a plane parallel to the substrate;

and growing a fifth layer of insulating medium GM5, and carrying out planarization treatment on the write bit line W_BL and the fifth layer of insulating medium CM5 so that the write bit line W_BL is flush with the upper surface of the fifth layer of insulating medium CM 5.

In an exemplary embodiment of the present application, the detailed arrangement of the write bit line w_bl may include, but is not limited to, deposition, photolithography, etching, planarization, and the like.

S105, a channel layer (i.e., a second channel layer CH 2) of the write transistor tr_w of the memory cell is provided, and a third gate medium GM3 and a third gate G3 corresponding to the write transistor tr_w are provided in the channel layer of the write transistor tr_w.

In an exemplary embodiment of the present application, the setting the channel layer (i.e., the second channel layer CH 2) of the write transistor tr_w of the memory cell, and setting the third gate medium GM3 and the third gate G3 corresponding to the write transistor tr_w in the channel layer of the write transistor tr_w may include:

etching downwards from the upper surface of the write bit line w_bl to form a second hole H2 penetrating through the write bit line w_bl to the upper surface of the first gate G1, as shown in fig. 17;

providing a channel layer of the write transistor (i.e., a second channel layer CH 2) on an inner wall of the second hole H2, and connecting the channel layer of the write transistor tr_w to the first gate G1, as shown in fig. 18;

growing a third gate dielectric GM3 on the inner wall of the channel layer (i.e., the second channel layer CH 2) of the write transistor tr_w, as shown in fig. 18;

the third gate G3 is grown in the space surrounded by the third gate dielectric GM3 as shown in fig. 18.

In an exemplary embodiment of the present application, the second hole H2 may be disposed in a manner including, but not limited to, photolithography, etching, and the like.

In an exemplary embodiment of the present application, an ALD (atomic layer deposition ) method may be used to sequentially deposit the second channel layer CH2 and the third gate dielectric GM3 on the inner wall of the second hole H2, and a third conductive material, for example, a conductive metal material, may be grown in the cavity of the third gate dielectric GM3 as the third gate electrode G3.

In an exemplary embodiment of the present application, the second channel layer CH2 may be provided using IGZO (indium gallium zinc oxide ), poly (polysilicon), silicon (silicon-based material), or the like.

In an exemplary embodiment of the present application, a distance between an upper surface of the first gate G1 and a lower surface of the write bit line w_bl is a gate length of the third gate G3 of the write transistor tr_w.

S106, a write word line w_wl is disposed above the third gate G3, as shown in fig. 19.

In exemplary embodiments of the present application, the write word line w_wl may be provided in a manner including, but not limited to, deposition, photolithography, etching, planarization, and the like.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (10)

1. A memory cell, comprising:

a reference voltage layer disposed on the substrate;

a read transistor;

reading a bit line;

a read word line;

a write transistor;

writing a bit line; the method comprises the steps of,

a write word line;

wherein the reference voltage layer, the read transistor, the read word line, the read bit line, the write transistor, the write word line, and the write bit line are stacked on the substrate;

forming a surrounding channel layer on the side wall of a first grid electrode of the read transistor, wherein the first grid electrode serves as a storage node; the second grid electrode of the reading transistor surrounds the periphery of the outer side of the channel layer of the reading transistor, and the second grid electrode is connected with the reading word line; the read bit line extends in a first direction on a plane parallel to the substrate;

forming a surrounding channel layer around the side wall of the third grid electrode of the writing transistor by the channel layer of the writing transistor; the write bit line surrounds the outer periphery of the channel layer of the write transistor and extends along a first direction on a plane parallel to the substrate; the channel layer of the write transistor is connected with the first grid electrode;

the read word line extends in a second direction on a plane parallel to the substrate;

the write word line extends in a second direction on a plane parallel to the substrate.

2. The memory cell of claim 1, wherein a first gate dielectric is disposed between the first gate and a channel layer of the read transistor;

a second gate dielectric is arranged between the second gate and the channel layer of the read transistor;

a third gate dielectric is disposed between the third gate and the channel layer of the write transistor.

3. A memory cell according to claim 1 or 2, wherein,

the length direction of the channel layer of the read transistor and the length direction of the first grid electrode are perpendicular to the substrate;

the length direction of the channel layer of the write transistor and the length direction of the third gate are perpendicular to the substrate.

4. A memory array comprising a plurality of memory cells as claimed in any one of claims 1 to 3.

5. A method of manufacturing a memory cell, characterized in that it is based on a memory cell according to any of claims 1-3, the method comprising:

sequentially stacking a reference voltage layer, a sacrificial layer and a read bit line of the memory cell on a substrate;

setting a channel layer of a read transistor of the memory cell, and setting a first gate medium and a first gate of the read transistor in the channel layer of the read transistor;

setting a mask, removing the sacrificial layer, growing a second gate medium and a second gate of the read transistor, and generating a read word line;

removing the mask and setting a write bit line above the first gate;

setting a channel layer of a write transistor of the memory cell, and setting a third gate medium and a third gate corresponding to the write transistor in the channel layer of the write transistor;

and a writing line is arranged above the third grid electrode.

6. The method for manufacturing a memory cell according to claim 5, wherein the step of sequentially stacking the reference voltage layer, the sacrificial layer, and the read bit line of the memory cell on the substrate comprises:

disposing the reference voltage layer on the substrate;

growing a first layer of insulating medium, and carrying out planarization treatment on the reference voltage layer and the first layer of insulating medium so that the reference voltage layer is flush with the upper surface of the first layer of insulating medium;

forming a sacrificial layer; the sacrificial layer extends in a second direction on a plane parallel to the substrate;

growing a second layer of insulating medium, and carrying out planarization treatment on the sacrificial layer and the second layer of insulating medium so that the sacrificial layer is flush with the upper surface of the second layer of insulating medium;

disposing the read bit line on the sacrificial layer such that the read bit line extends in a first direction on a plane parallel to the substrate;

and growing a third layer of insulating medium, and carrying out planarization treatment on the read bit line and the third layer of insulating medium so that the read bit line is flush with the upper surface of the third layer of insulating medium.

7. The method of manufacturing a memory cell according to claim 5, wherein the disposing a channel layer of a read transistor of the memory cell, disposing a first gate dielectric and a first gate of the read transistor in the channel layer of the read transistor, comprises:

etching downwards from the upper surface of the read bit line, and etching a first hole penetrating through the read bit line and the sacrificial layer to the upper surface of the reference voltage layer;

providing a channel layer of the read transistor on an inner wall of the first hole;

growing a first gate dielectric on the inner wall of the channel layer of the read transistor;

the first gate is grown within a space surrounded by the first gate dielectric.

8. The method of claim 6, wherein the disposing a mask, removing the sacrificial layer, growing the second gate dielectric and the second gate of the read transistor, and generating the read word line, comprises:

disposing the mask on the first gate;

etching all the sacrificial layers by adopting an etching technology, and etching part of the third layer insulating medium around the read bit line;

growing a layer of second gate dielectric in the space formed after etching the sacrificial layer and the third layer of insulating dielectric;

growing a layer of second gate dielectric in the space formed after etching the sacrificial layer and the third layer of insulating dielectric;

growing a second gate in a space surrounded by the second gate dielectric;

etching the second grid electrode to a required size, enabling the second grid electrode to extend along a second direction on a plane parallel to the substrate, and growing a fourth layer of insulating medium in a space where the second grid electrode is etched;

and the area where the second gates of different read transistors are connected with each other is used as the read word line.

9. The method of claim 5, wherein the disposing a write bit line over the first gate comprises:

providing a write bit line on the first gate, such that the write bit line extends in a first direction on a plane parallel to the substrate;

and growing a fifth-layer insulating medium, and carrying out planarization treatment on the write bit line and the fifth-layer insulating medium so that the write bit line is flush with the upper surface of the fifth-layer insulating medium.

10. The method for manufacturing a memory cell according to claim 9, wherein the step of providing the channel layer of the write transistor of the memory cell, and providing the third gate dielectric and the third gate corresponding to the write transistor in the channel layer of the write transistor, comprises:

etching downwards from the upper surface of the write bit line to form a second hole penetrating through the write bit line to the upper surface of the first grid electrode;

setting a channel layer of the write transistor on the inner wall of the second hole, and connecting the channel layer of the write transistor with the first grid electrode;

growing a third gate dielectric on the inner wall of the channel layer of the write transistor;

and growing the third grid in the space surrounded by the third grid dielectric.