CN117411312A - Bootstrap capacitor shared circuit driven by multipath high-side field effect transistors and electronic equipment - Google Patents
Bootstrap capacitor shared circuit driven by multipath high-side field effect transistors and electronic equipment Download PDFInfo
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- CN117411312A CN117411312A CN202210800528.1A CN202210800528A CN117411312A CN 117411312 A CN117411312 A CN 117411312A CN 202210800528 A CN202210800528 A CN 202210800528A CN 117411312 A CN117411312 A CN 117411312A
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- voltage
- circuit
- bootstrap capacitor
- field effect
- driving
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- 239000003990 capacitor Substances 0.000 title claims abstract description 70
- 230000005669 field effect Effects 0.000 title claims abstract description 68
- 238000007667 floating Methods 0.000 claims abstract description 23
- 230000001105 regulatory effect Effects 0.000 claims description 11
- 238000004146 energy storage Methods 0.000 claims description 8
- 230000000087 stabilizing effect Effects 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 102100029824 ADP-ribosyl cyclase/cyclic ADP-ribose hydrolase 2 Human genes 0.000 description 8
- 101000794082 Homo sapiens ADP-ribosyl cyclase/cyclic ADP-ribose hydrolase 2 Proteins 0.000 description 8
- 101001099051 Homo sapiens GPI inositol-deacylase Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention provides a bootstrap capacitor shared circuit driven by multipath high-side field effect transistors and electronic equipment, wherein the bootstrap capacitor shared circuit comprises more than two field effect transistor control loops, each field effect transistor control loop comprises a field effect transistor and a driving circuit, the driving circuit outputs driving voltage to the field effect transistor, and the driving circuit comprises at least one inverter; the bootstrap capacitor sharing circuit also comprises a charge pump circuit, and the charge pump circuit outputs working voltages to the driving circuits of the field effect transistor control circuits; the driving circuit of each field effect transistor control loop comprises an adjusting module, wherein the adjusting module receives the working voltage and maintains the pressure difference between the working voltage end and the floating voltage end of the inverter of the driving circuit. The invention also provides electronic equipment with the bootstrap capacitor sharing circuit driven by the multipath high-side field effect transistors. The invention can reduce the pin number used by the bootstrap capacitor sharing circuit.
Description
Technical Field
The invention relates to the technical field of power supply circuits, in particular to a bootstrap capacitor sharing circuit driven by a multipath high-side field effect transistor and electronic equipment with the same.
Background
Some existing electronic devices require the use of circuits with larger power, such as a dc buck circuit (buck circuit), a dc boost circuit (boost circuit), a half-bridge driving circuit of a power transistor, a full-bridge driving circuit, etc., which often require a field-effect transistor as a switching device. When the field effect transistor works, the state of the field effect transistor needs to be in a high-frequency switching state, namely the state of the field effect transistor is continuously switched between an on state and an off state.
A conventional dc voltage step-down circuit is shown in fig. 1. The circuit comprises two field effect transistors M1 and M2, each field effect transistor needs to be driven by a driving circuit, and the driving circuit outputs driving signals to the field effect transistors to drive the field effect transistors to be turned on or turned off. In fig. 1, two field effect transistors M1 and M2 are an upper tube and a lower tube, respectively, and the drain of the field effect transistor M1 is connected to the input voltage Vin through one pin 11. When the field effect transistor M1 is turned on, the input voltage Vin charges the inductor L and the capacitor C2 through the field effect transistor M1, and one end of the capacitor C2 is connected to the output end. When the fet M1 is in the off state, the input voltage Vin cannot charge the inductor L and the capacitor C2 through the fet M1. The source of the FET M1 is connected to the floating voltage terminal SW and to the inductor L via pin 13.
When the fet M2 is turned on, the inductor L and the capacitor C2 can discharge through the fet M2, and if the fets M1 and M2 are turned on simultaneously, the input voltage Vin is equivalent to ground, and the inductor L and the capacitor C2 are not charged. Thus, by controlling the on time of the field effect transistors M1 and M2, the voltage at the output terminal can be adjusted, thereby realizing the step-down output of the input voltage Vin.
Because in the power management chip of the system-on-chip SOC, a plurality of DCDC circuits are usually required to supply power to each subsystem of the system-on-chip, it is common practice to form a field effect transistor capable of bearing a larger current by using a PMOS transistor and an NMOS transistor of 5V in a common CMOS transistor process, for example, the upper transistor M1 adopts a PMOS transistor and the lower transistor M2 adopts an NMOS transistor.
Since the field effect transistors M1 and M2 are in the state of the high-frequency switch, the conduction loss formed when the field effect transistors M1 and M2 are turned on is large. In order to reduce the power consumption of the electronic device, it is desirable that the on-resistances of the two field effect transistors M1, M2 are as small as possible. The on-resistance of the NMOS tube with the same area is smaller than that of the PMOS tube. Therefore, in the dc voltage step-down circuit with larger current, the field effect transistors M1 and M2 are usually NMOS transistors to reduce damage to the electronic devices.
However, if both the upper tube and the lower tube use NMOS tubes as the switching devices, the field effect tube M1 as the upper tube needs to set a driving voltage Vdrv higher than the input voltage Vin of the dc voltage reducing circuit to drive the field effect tube M1 to be turned on, for example, the driving voltage Vdrv is generally about 5V higher than the input voltage Vin with reference to the withstand voltage parameter of the gate-source voltage Vgs of the NMOS tube.
On the other hand, as the current demand of the system on chip is larger and larger, a large amount of damage is generated by using the PMOS transistor, and the damage will cause serious heating of the whole power management chip. In order to improve the efficiency of the power management chip, it is also considered to replace the PMOS transistor as the upper transistor M1 with an NMOS transistor, but this method needs to add a bootstrap capacitor C1, and the bootstrap capacitor C1 forms the working voltage required for the inverter to work.
After the bootstrap capacitor C1 is set, a pin, i.e. pin 12, needs to be added to the driving circuit, and in the power management chip, the pin resources are relatively tight, so that the existing technology will cause the difficulty in pin allocation of the power management chip, and increase the cost of circuit design.
Disclosure of Invention
It is a first object of the present invention to provide a bootstrap capacitor sharing circuit capable of reducing the number of multiple high-side fet driving using pins.
The second object of the present invention is to provide an electronic device using the bootstrap capacitor common circuit driven by the multipath high-side field effect transistor.
In order to achieve the first object of the present invention, the bootstrap capacitor common circuit for driving multiple high-side field effect transistors provided by the present invention includes more than two field effect transistor control loops, each field effect transistor control loop includes a field effect transistor and a driving circuit, the driving circuit outputs a driving voltage to the field effect transistor, and the driving circuit includes at least one inverter; the bootstrap capacitor sharing circuit also comprises a charge pump circuit, and the charge pump circuit outputs working voltages to the driving circuits of the field effect transistor control circuits; the driving circuit of each field effect transistor control loop comprises an adjusting module, wherein the adjusting module receives the working voltage and maintains the pressure difference between the working voltage end and the floating voltage end of the inverter of the driving circuit.
According to the scheme, the charge pump circuit can output working voltages to the driving circuits of the field effect transistor control loops at the same time, so that only one charge pump circuit is arranged and the charge pump circuit is used for lifting the input voltage to the sum of the input voltage and the reference driving voltage, the working requirements of the field effect transistor control loops can be met at the same time, and a separate bootstrap capacitor is not required to be arranged on each driving circuit, so that the number of used pins is reduced.
In a preferred scheme, the charge pump circuit charges a bootstrap capacitor, and a positive plate of the bootstrap capacitor outputs an operating voltage to the regulating module.
Therefore, the voltage output by the charge pump circuit is stabilized through the bootstrap capacitor, so that the working voltage loaded to the regulating module is stabilized.
Further, the charge pump circuit increases the voltage of the positive plate of the bootstrap capacitor to the sum of the input voltage and the reference driving voltage.
Therefore, the scheme can ensure that the voltage recorded in the regulating module is higher than the input voltage, and meets the driving requirement of the field effect transistor.
Still further, a positive plate of the bootstrap capacitor is connected to one pin. Therefore, only the bootstrap capacitor is connected with one pin, no additional pin is needed to be arranged in each field effect tube control loop to be connected with the capacitor, and in the scene of having a plurality of field effect tube control loops, the number of pins can be introduced, so that the design difficulty of a circuit is reduced.
In a further scheme, the regulating module comprises an energy storage capacitor and a voltage stabilizing diode, wherein two ends of the energy storage capacitor are respectively connected to the working voltage end and the floating voltage end of the inverter, and the voltage stabilizing diode is used for maintaining the voltage difference between the working voltage end and the floating voltage end of the inverter.
Therefore, the voltage difference between the working voltage end and the floating voltage end of the inverter can be kept stable through the voltage stabilizing diode, and the conduction voltage of the field effect transistor is ensured to be stable.
In a further scheme, the regulating module further comprises an NMOS tube, a source electrode of the NMOS tube is connected to a first end of the energy storage capacitor, and two ends of the zener diode are respectively connected to a grid electrode of the NMOS tube and a second end of the energy storage capacitor. Preferably, the drain electrode of the NMOS tube receives the output working voltage of the adjusting module.
Because the conducting condition of the NMOS tube is that the voltage difference between the grid electrode and the source electrode meets the preset voltage, the voltage difference between the working voltage end of the inverter and the floating voltage end can be ensured to be kept stable by setting the voltage difference between the grid electrode and the source electrode of the voltage stabilizing diode as the sum of the conducting voltage of the NMOS tube and the voltage difference between the working voltage end of the inverter and the floating voltage end.
In a further scheme, each field effect transistor control loop is further provided with a driving module, and the driving module outputs voltage to the inverter.
It can be seen that the reference driving voltage is output to the inverters through the driving module to drive the operation of each inverter, thereby driving the operation of the field effect transistor.
In a further scheme, each field effect transistor control loop is further provided with a level transfer module, and the level transfer module receives the voltage output by the driving module and outputs the voltage to the inverter.
Therefore, the level generated by the driving module can be transferred to the working voltage end of the inverter or the floating voltage end through the action of the level transfer module, and finally the field effect transistor is driven to be opened.
In order to achieve the second object, the electronic device provided by the invention comprises an electricity utilization module; and the bootstrap capacitor sharing circuit driven by the multipath high-side field effect transistors is also included, and the bootstrap capacitor sharing circuit supplies power to the power utilization module.
Drawings
Fig. 1 is an electrical schematic diagram of a prior art bootstrap drive circuit.
FIG. 2 is an electrical schematic diagram of an embodiment of a bootstrap capacitor common circuit driven by multiple high-side field effect transistors according to the present invention.
Fig. 3 is an electrical schematic diagram of an adjustment module and a fet control loop in an embodiment of a bootstrap capacitor common circuit driven by multiple high-side fets according to the present invention.
The invention is further described below with reference to the drawings and examples.
Detailed Description
The bootstrap capacitor shared circuit driven by the multipath high-side field effect transistor is applied to electronic equipment, and preferably, the electronic equipment is provided with an electricity utilization module, and the bootstrap capacitor shared circuit is used for supplying power to the electricity utilization module. The bootstrap capacitor shared circuit is internally provided with a plurality of field effect transistors, and the shared charge pump circuit outputs working voltage to the field effect transistor driving circuits, so that the number of pins used is reduced.
Bootstrap capacitor shared circuit embodiment driven by multipath high-side field effect transistors:
referring to fig. 2, the present embodiment is provided with two fet control circuits, each including a fet and a driving circuit. It should be noted that fig. 2 is only a schematic illustration of two fet control loops, and more fet control loops may be provided in practical applications.
The driving circuit of each fet control loop includes an adjusting module, a driving module, a level shifting module, and a plurality of inverters, for example, the driving circuit of the first fet control loop includes an adjusting module 31, a driving module 32, a level shifting module 33, and two inverters 34, the two inverters 34 are connected in series, and the inverter 34 of the subsequent stage outputs a driving signal to the fet M21.
The field effect transistor M21 is a switching device that operates at a high frequency, and has a drain connected to an input voltage Vin via a pin 21, a gate connected to one of the inverters 34, and receives a driving voltage output from the inverter 34, and operates at the driving voltage output from the inverter 34. The source of the fet M21 is connected to the floating voltage terminal SW through the pin 22, and the floating voltage terminal SW can be connected to a load, an inductor, a diode, etc. according to the requirements of the actual circuit. For example, in the dc voltage step-down circuit shown in fig. 1, a diode or an NMOS tube is connected between the floating voltage terminal SW and the ground terminal GND, and is further connected to one end of the inductor.
The driving circuit of the second fet control loop includes an adjusting module 41, a driving module 42, a level shifting module 43, and two inverters 44, the two inverters 44 are connected in series, and the inverter 44 of the subsequent stage outputs a driving signal to the fet M22. In addition, the drain of the field effect transistor M22 is connected to the input voltage Vin via the pin 26, the gate is connected to an inverter 44, and the source is connected to the floating voltage terminal SW via the pin 27.
The embodiment is further provided with a charge pump 20, the charge pump 20 receives an input voltage Vin and a reference driving voltage Vdrv, the charge pump 20 is connected to the bootstrap capacitor C21 through a pin 28, and the charge pump 20 can boost the voltage of the positive plate of the bootstrap capacitor C21 to the sum of the input voltage Vin and the reference driving voltage Vdrv, that is, the voltage VCP at the positive plate of the bootstrap capacitor C21 is the input voltage vin+the reference driving voltage Vdrv. The charge pump 20 outputs an operating voltage to the driving circuits of the two fet control loops, wherein the voltage VCP at the positive plate of the bootstrap capacitor C21 is the operating voltage output by the charge pump 20, and thus the operating voltage is the sum of the input voltage Vin and the reference driving voltage Vdrv. Typically, the reference driving voltage Vdrv is 5V to 7V.
Taking the driving circuit of the first fet control loop as an example, the adjusting module 31 can provide the voltage to the inverter 34 after receiving the operating voltage, and maintain the voltage difference between the operating voltage terminal BST1 and the floating voltage terminal SW of the inverter 34 of the driving circuit. Specifically, referring to fig. 3, the adjusting module 31 includes a resistor R1, a zener diode Z1, and an NMOS tube MR1 as a switching device, where one end of the resistor R1 is connected to the operating voltage VCP, and the other end is connected to the gate of the NMOS tube MR 1. The drain of the NMOS transistor MR1 receives the operating voltage VCP output by the charge pump 20, and the source thereof is connected to the first end of the storage capacitor C31. A second terminal of the storage capacitor C31 is connected to the voltage-voltage terminal SW. The first terminal of the zener diode Z1 is connected to the gate of the NMOS transistor MR1, and the second terminal of the zener diode Z1 is connected to the voltage-to-ground terminal SW.
The adjusting module 31 is configured to form a preset voltage difference between the working voltage terminal BST1 of the inverter 34 and the floating voltage terminal SW, for example, a voltage difference of 5V, so as to meet the working requirement of the fet M21. Since the conduction condition of the NMOS MR1 is that the voltage difference between the gate voltage and the source voltage is higher than the conduction voltage, a suitable zener diode Z1 is provided, so that the voltage difference across the zener diode Z1 is +5v of the conduction voltage of the NMOS MR1, that is, the conduction voltage of the NMOS MR1 plus the voltage difference between the preset inverter 34 operating voltage terminal BST1 and the floating voltage terminal SW. Thus, after the NMOS tube MR1 is turned on, the voltage value obtained by subtracting the on voltage of the NMOS tube MR1 from the voltage across the zener diode Z1 is 5V, which is just the voltage difference between the operating voltage terminal BST1 of the inverter 34 and the floating voltage terminal SW. It can be seen that the voltage difference between the operation voltage terminal BST1 of the inverter 34 and the floating voltage terminal SW can be kept stable by providing the zener diode Z1.
The driving module 32 outputs a signal to the level shifting module 33, the signal output by the driving module 32 is received by the level shifting module 33, and the level shifting module 33 shifts the received signal to the working voltage terminal BST1 or the floating voltage terminal SW of the inverter 34, and thereby drives the fet M21 to open. For example, when the driving module 32 outputs a high level, the level shift module 33 outputs a high level signal to the inverter 34 operation voltage terminal BST1, and when the driving module 32 outputs a low level, the level shift module 33 outputs a low level signal to the floating voltage terminal SW. In addition, the level shift module 33 outputs a voltage to the inverter 34. The level shift module 33 may be implemented by using a known level shift circuit, which will not be described in detail.
Under the level signal output by the level shift module 33, the two inverters 34 operate according to the voltage of the operating voltage terminal BST1 of the inverter 34 and the level signal output by the level shift module 33, and drive the field effect transistor M21 to operate.
The working principle of the driving circuit of the second field effect tube control loop is the same as that of the driving circuit of the first field effect tube control loop, and the description is omitted.
In this embodiment, only two pins are used for the driving circuit of each fet control loop, and one pin is used for the bootstrap capacitor C21 of the charge pump 20, and since the charge pump 20 can output the working voltage to the plurality of fet control loops, the number of pins used for the bootstrap capacitor common circuit driven by the entire multi-channel high-side fet is reduced while the damage of the entire circuit is reduced.
Electronic device embodiment:
the electronic device of the embodiment is provided with one or more power utilization modules, and is provided with the bootstrap capacitor sharing circuit driven by the multipath high-side field effect transistors, and the bootstrap capacitor sharing circuit supplies power to the power utilization modules.
Finally, it should be emphasized that the invention is not limited to the above-described embodiments, such as for example variations in the structure of the charge pump, or variations in the internal structure of the adjustment module, etc., which are also intended to be included in the scope of the claims.
Claims (10)
1. A multi-channel high-side fet driven bootstrap capacitor sharing circuit comprising:
more than two field effect transistor control loops, each field effect transistor control loop comprises a field effect transistor and a driving circuit, the driving circuit outputs driving voltage to the field effect transistor, and the driving circuit comprises at least one inverter;
the method is characterized in that:
the bootstrap capacitor sharing circuit also comprises a charge pump circuit, wherein the charge pump circuit outputs working voltage to the driving circuits of the field effect transistor control loops;
the driving circuit of each FET control loop comprises a regulating module, wherein the regulating module receives the working voltage and maintains the pressure difference between the working voltage end and the floating voltage end of the inverter of the driving circuit.
2. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in claim 1, characterized by:
the charge pump circuit charges a bootstrap capacitor, and a positive plate of the bootstrap capacitor outputs the working voltage to the regulating module.
3. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in claim 2, characterized by:
the charge pump circuit increases the voltage of the positive plate of the bootstrap capacitor to the sum of the input voltage and the reference drive voltage.
4. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in claim 2, characterized by:
the positive plate of the bootstrap capacitor is connected to one pin.
5. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in any one of claims 1-4, characterized by:
the regulating module comprises an energy storage capacitor and a voltage stabilizing diode, wherein two ends of the energy storage capacitor are respectively connected to the working voltage end of the inverter and the floating voltage end, and the voltage stabilizing diode is used for maintaining the pressure difference between the working voltage end of the inverter and the floating voltage end.
6. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in claim 5, characterized by:
the regulating module further comprises an NMOS tube, a source electrode of the NMOS tube is connected to the first end of the energy storage capacitor, and two ends of the zener diode are respectively connected to a grid electrode of the NMOS tube and the second end of the energy storage capacitor.
7. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in claim 6, characterized by:
and the drain electrode of the NMOS tube receives the working voltage output by the regulating module.
8. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in any one of claims 1-4, characterized by:
each field effect transistor control loop is also provided with a driving module, and the driving module outputs voltage to the inverter.
9. The multi-channel high-side fet driven bootstrap capacitor sharing circuit as defined in claim 8, characterized by:
each field effect transistor control loop is also provided with a level transfer module, and the level transfer module receives the voltage output by the driving module and outputs the voltage to the inverter.
10. An electronic device, comprising:
an electricity utilization module;
the method is characterized in that:
further comprising a multi-channel high-side fet driven bootstrap capacitor common circuit as defined in any one of claims 1 to 9, said bootstrap capacitor common circuit powering said power module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210800528.1A CN117411312A (en) | 2022-07-08 | 2022-07-08 | Bootstrap capacitor shared circuit driven by multipath high-side field effect transistors and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210800528.1A CN117411312A (en) | 2022-07-08 | 2022-07-08 | Bootstrap capacitor shared circuit driven by multipath high-side field effect transistors and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117411312A true CN117411312A (en) | 2024-01-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210800528.1A Pending CN117411312A (en) | 2022-07-08 | 2022-07-08 | Bootstrap capacitor shared circuit driven by multipath high-side field effect transistors and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117411312A (en) |
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2022
- 2022-07-08 CN CN202210800528.1A patent/CN117411312A/en active Pending
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