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CN117406934B - Flash memory data access method, electric quantity calculation method, device and storage medium - Google Patents

Flash memory data access method, electric quantity calculation method, device and storage medium Download PDF

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Publication number
CN117406934B
CN117406934B CN202311709747.XA CN202311709747A CN117406934B CN 117406934 B CN117406934 B CN 117406934B CN 202311709747 A CN202311709747 A CN 202311709747A CN 117406934 B CN117406934 B CN 117406934B
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Prior art keywords
instruction
flash memory
flash
data
access
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CN117406934A (en
Inventor
马东捷
曾熙斌
刘娇
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Shenzhen Siyuan Semiconductor Co ltd
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Shenzhen Siyuan Semiconductor Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

The embodiment of the invention provides a flash memory data access method, an electric quantity calculation device and a storage medium. The flash memory data access method comprises the following steps: acquiring an access signal of external equipment to a register set; determining a corresponding operation instruction according to the access signal, wherein the operation instruction is arranged in the register group; analyzing the operation instruction to obtain an analyzed instruction signal; and sending a corresponding instruction request to the flash memory controller according to the analyzed instruction signal so that the flash memory controller executes access to the flash memory data according to the instruction request. The external device can access the FLASH memory controller through the FLASH memory data access device to send a corresponding instruction request to the FLASH memory controller, and the FLASH memory controller can access the FLASH according to the received instruction request. The external equipment has simple working flow for accessing FLASH and high execution speed. The FLASH controller does not need to additionally analyze the received instruction request, so that the complexity of the FLASH controller can be reduced, and the flexibility and reliability of external equipment to FLASH are improved.

Description

Flash memory data access method, electric quantity calculation method, device and storage medium
Technical Field
The present invention relates to the field of data access technologies, and in particular, to a flash memory data access method, an electric quantity calculation device, and a storage medium.
Background
The FLASH memory (FLASH) can be used as a program memory of the singlechip, and the singlechip can execute operations such as power-on, reset, logic operation and the like by reading programs stored in the FLASH.
In the related art, the singlechip accesses the FLASH controller to realize the data access of the FLASH, and because the control time sequence of the FLASH is relatively complex, a series of actions such as erasing, caching, burning and the like are often needed to complete the erasing or writing of the FLASH once. Therefore, the FLASH controller is more redundant and complicated in design. Correspondingly, the complexity of the work flow of the singlechip software program is higher, so that the access efficiency of the singlechip to FLASH is low, and the flexibility and the reliability are poor.
Disclosure of Invention
The embodiment of the invention provides a flash memory data access method, an electric quantity calculation device and a storage medium.
The flash memory data access method provided by the embodiment of the invention comprises the following steps: acquiring an access signal of external equipment to a register set; determining a corresponding operation instruction according to the access signal, wherein the operation instruction is stored in the register group; analyzing the operation instruction to obtain an analyzed instruction signal; and sending a corresponding instruction request to the flash memory controller according to the analyzed instruction signal so that the flash memory controller executes access to the flash memory data according to the instruction request.
Compared with the method that the external device accesses the FLASH through accessing the FLASH controller, the external device can access the FLASH through accessing the register group, so that the workflow of accessing the FLASH is simpler, and the execution speed is faster. The FLASH controller is split into the instruction analysis module and the instruction execution module, so that the complexity of the design of the FLASH controller can be reduced, and the access efficiency, flexibility and reliability of external equipment to the FLASH are improved.
In some embodiments, the obtaining the access signal of the external device to the register set includes: the access signal is acquired based on an integrated circuit bus protocol.
The FLASH memory data access method of the embodiment of the invention can be applied to the field of integrated circuits, the external equipment can be a controller in the field of integrated circuits, and the external equipment can access FLASH to execute corresponding work based on an integrated circuit bus protocol. The external equipment can realize the communication with the register set only by one data line and one clock line, and the connecting circuit is simple, thereby being beneficial to optimizing the space and the cost of the connecting circuit.
In some embodiments, the register set includes an address register and an instruction register, the operation instruction being disposed within the instruction register. The flash memory data access method comprises the following steps: acquiring an access signal of external equipment to a register set; determining an operation address of the external device written into the address register according to the access signal; determining an operation instruction of the external device for accessing the instruction register according to the access signal; analyzing the operation instruction to obtain an analyzed instruction signal; and sending a corresponding instruction request to the flash memory controller according to the analyzed instruction signal so that the flash memory controller executes access to the flash memory data according to the operation address and the instruction request.
The external device may write a FLASH address or a RAM address to be accessed to the address register, so that the FLASH register performs data access to the corresponding FLASH address or RAM address.
In some embodiments, the register set further includes a data register, and after sending a corresponding instruction request to the flash memory controller according to the parsed instruction signal, the flash memory data access method includes: and under the condition that the instruction request is a write-in request, determining operation data written into the data register by the external equipment according to the access signal so as to enable the flash memory controller to write the operation data into the operation address.
The external device may write the data to be written to the FLASH or RAM into the data register, so that the FLASH register writes the corresponding data to the corresponding FLASH address or RAM address.
In some embodiments, parsing the operation instruction to obtain a parsed instruction signal includes: combining a plurality of the operation instructions to obtain a combined operation instruction; and analyzing one of the combined operation instructions to obtain one analyzed instruction signal.
The plurality of operation instructions can be combined, and functions which can be realized by the operation instructions after combination are similar to functions which can be realized by the operation instructions before combination.
In some embodiments, parsing the operation instruction to obtain a parsed instruction signal includes: disassembling one operation instruction to obtain a plurality of disassembled operation instructions; and analyzing a plurality of the disassembled operation instructions to obtain a plurality of analyzed instruction signals.
One operation instruction can be disassembled, and functions which can be realized by a plurality of disassembled operation instructions are similar to functions which can be realized by operation instructions before disassembly.
In some embodiments, the instruction request comprises a burn instruction request. The step of sending a corresponding instruction request to the flash memory controller according to the parsed instruction signal, so that the flash memory controller executes access to the flash memory data according to the instruction request, including: under the condition that the burning command request is sent to the flash memory controller, erasing data of a flash memory preparation area; after the data in the flash memory preparation area is completely erased, the data in the corresponding cache area is written into the flash memory preparation area, so that the external equipment burns the data in the flash memory preparation area.
In some embodiments, the instruction request comprises a flash instruction request. The step of sending a corresponding instruction request to the flash memory controller according to the parsed instruction signal, so that the flash memory controller executes access to the flash memory data according to the instruction request, including: and under the condition that the rapid burning instruction request is sent to the flash memory controller, writing corresponding data into a corresponding cache area so as to enable the external equipment to burn the data in the corresponding cache area.
Under the condition that the quick burning instruction request is sent to the flash memory controller, corresponding data are written into the corresponding cache area, so that the external equipment burns the data in the corresponding cache area.
In some embodiments, the sending a corresponding instruction request to the flash memory controller according to the parsed instruction signal, so that the flash memory controller performs access to flash memory data according to the instruction request, includes: in the case of an initialization state, the flash memory controller is capable of executing access to the flash memory data according to the instruction request, wherein the flash memory controller is in the initialization state after completing the access to the flash memory data.
After the flash memory controller executes all the processes of completing one instruction request, the instruction execution module returns to the idle state. The instruction execution module waits to receive a new parsed instruction signal in order to issue a new instruction request in the idle state.
The embodiment of the invention provides a flash memory data access device which comprises a register group, an instruction analysis module and an instruction execution module. The register set is internally provided with an operation instruction, and the register set is used for determining the corresponding operation instruction according to an access signal of external equipment to the register set. The instruction analysis module is used for analyzing the operation instruction to obtain an analyzed instruction signal. The instruction execution module is used for sending a corresponding instruction request to the flash memory controller according to the analyzed instruction signal so that the flash memory controller executes access to the flash memory data according to the instruction request.
The embodiment of the invention provides an electric quantity calculation method, which comprises the following steps: the flash memory data is obtained by adopting the flash memory data access method of any one of the embodiments; acquiring an electric quantity calculation program according to the flash memory data; and calculating the electric quantity according to the electric quantity calculation program and an electric parameter, wherein the electric parameter comprises at least one of current and voltage.
The embodiment of the invention provides an electricity meter, which comprises an electric parameter acquisition module and a calculation module. The electrical parameter acquisition module is used for acquiring electrical parameters, wherein the electrical parameters comprise at least one of current and voltage. The calculation module is used for calculating the electric quantity according to an electric quantity calculation program and the electric parameter, and the electric quantity calculation program is determined based on the flash memory data access method of any one of the embodiments.
Embodiments of the present invention provide a computer-readable storage medium. The computer readable storage medium is used for storing a computer program, and when executed, the computer readable storage medium implements the flash memory data access method or the electric quantity calculation method of any one of the above embodiments.
The embodiment of the invention provides a flash memory data access method, an electric quantity calculation device and a storage medium. The flash memory data access method comprises the following steps: acquiring an access signal of external equipment to a register set; determining a corresponding operation instruction according to the access signal, wherein the operation instruction is arranged in the register group; analyzing the operation instruction to obtain an analyzed instruction signal; and sending a corresponding instruction request to the flash memory controller according to the analyzed instruction signal so that the flash memory controller executes access to the flash memory data according to the instruction request. The external device can access the FLASH memory data access device to send a corresponding instruction request to the FLASH memory controller, and the FLASH memory controller can access the FLASH memory data (FLASH) according to the received instruction request.
Compared with the method that the external equipment accesses the FLASH through accessing the complex instruction FLASH controller, the external equipment accesses the FLASH through accessing the register group, the workflow of the external equipment accessing the FLASH is simpler, and the execution speed is faster. The FLASH controller can execute access to the FLASH data according to the received instruction request, and the received instruction request is not required to be additionally analyzed, so that the complexity of the FLASH controller can be reduced, the complexity of the workflow of the software program of the external device is reduced, and the access efficiency, the flexibility and the reliability of the external device to the FLASH are improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a flow chart of a flash memory data access method according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a flash data access device according to an embodiment of the present invention;
FIG. 3 is a table diagram of a register set encoding a corresponding instruction set according to the present invention;
FIG. 4 is a schematic diagram of a register set according to an embodiment of the present invention;
FIG. 5 is a flow chart of a flash memory data access method according to a second embodiment of the present invention;
FIG. 6 is a flow chart of a method for accessing flash memory data according to a third embodiment of the present invention;
FIG. 7 is a flow chart of a method for accessing flash memory data according to a fourth embodiment of the present invention;
FIG. 8 is a schematic workflow diagram of an instruction execution module according to an embodiment of the present invention;
FIG. 9 is a schematic view of an electricity meter according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
The FLASH memory (FLASH) can be used as a program memory of the singlechip, and the singlechip can execute operations such as power-on, reset, logic operation and the like by reading programs stored in the FLASH.
In the related art, the singlechip accesses the FLASH controller to realize the data access of the FLASH, and because the control time sequence of the FLASH is relatively complex, a series of actions such as erasing, caching, burning and the like are often needed to complete the erasing or writing of the FLASH once. Therefore, the FLASH controller is more redundant and complicated in design. Correspondingly, the complexity of the work flow of the singlechip software program is higher, so that the access efficiency of the singlechip to FLASH is low, and the flexibility and the reliability are poor.
Referring to fig. 1 and 2, an embodiment of the present invention provides a flash memory data access method and a flash memory data access device. In some embodiments, the flash data access method may be implemented by a flash data access device, that is, the flash data access device is used to implement the flash data access method.
Of course, in other embodiments, the flash data access method may be implemented by other devices or apparatuses, and is not limited to implementation by the flash data access device. The flash memory data access device may not be dedicated to implementing the flash memory data access method according to the embodiment of the present invention, but may implement other functions and methods.
In some embodiments, a flash data access method includes: step S10, obtaining an access signal of the external device 200 to the register set 10;
step S20, corresponding operation instructions are determined according to the access signals, wherein the operation instructions are stored in the register group 10;
S30, analyzing the operation instruction to obtain an analyzed instruction signal;
Step S40, a corresponding command request is sent to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request.
The flash data access device includes a register set 10, and an instruction request for accessing flash data by the external device 200 may be integrated into a corresponding operation instruction, which is provided inside the register set 10.
The external device 200 may access a FLASH data access device to issue a corresponding instruction request to the FLASH controller 300, and the FLASH controller 300 may access FLASH data (FLASH) according to the received instruction request.
Further, the register set 10 may determine an operation instruction that the external device 200 needs to access according to the access signal of the external device 200, analyze the operation instruction that needs to access to obtain an analyzed instruction signal, and send a corresponding instruction request to the flash memory controller 300 according to the analyzed instruction signal, so that the flash memory controller 300 performs access to the flash memory data according to the instruction request.
Compared with the external device 200 accessing the FLASH controller 300 through complex instructions to access the FLASH, the external device 200 accessing the FLASH through accessing the register set 10 has simpler workflow, reduces the complexity of the workflow of the software program of the external device, and has faster execution speed. The FLASH memory controller 300 can execute access to the FLASH memory data according to the received instruction request, and does not need to additionally analyze the received instruction request, so that the complexity of the FLASH memory controller 300 can be reduced, the complexity of the software program workflow of the external device 200 is reduced, and the access efficiency, flexibility and reliability of the external device 200 to the FLASH are improved.
In some embodiments, the flash data access device includes a register set 10, an instruction parsing module 20, and an instruction execution module 30. An operation instruction is set in the register set 10, and the register set 10 is used for determining a corresponding operation instruction according to an access signal of the external device 200 to the register set 10. The instruction parsing module 20 is configured to parse an operation instruction to obtain a parsed instruction signal. The instruction execution module 30 is configured to send a corresponding instruction request to the flash memory controller 300 according to the parsed instruction signal, so that the flash memory controller 300 performs access to the flash memory data according to the instruction request.
The external device 200 may enable access to the flash data by accessing the register set 10. The register set 10 may determine an operation instruction that the external device 200 needs to access according to an access signal of the external device 200, and send the operation instruction that needs to be accessed to the instruction parsing module 20. The instruction parsing module 20 may parse the acquired operation instruction into different parsed instruction signals. The instruction execution module 30 may generate a corresponding instruction request according to the received parsed instruction signal, and send the corresponding instruction request to the FLASH controller 300, and the FLASH controller 300 may generate a control signal of the FLASH to access the FLASH.
The FLASH controller 300 is structurally split into the instruction parsing module 20 and the instruction executing module 30, and the corresponding workflows of the instruction parsing module 20 and the instruction executing module 30 are also split from the FLASH controller 300, so that the complexity of the FLASH controller 300 can be reduced, the complexity of the workflow of the software program of the external device 200 is reduced, and the access efficiency, flexibility and reliability of the external device 200 to the FLASH are improved.
Specifically, in step S10, the external device 200 may be a single-chip microcomputer or other electronic devices. The external device 200 may access the register set 10 based on an integrated circuit bus protocol (Inter-INTEGRATED CIRCUI, I2C), or the external device 200 may access the register set 10 based on a serial peripheral interface protocol (SERIAL PERIPHERAL INTERFACE, SPI) or other protocol communication.
In step S20, the instruction request of the external device 200 to access the flash data may be integrated into a corresponding operation instruction, and one operation instruction may be encoded corresponding to one section of the register set 10. When the external device 200 accesses the register set 10, the register set 10 may determine, according to the access signal, a code inside the register set 10 that the external device 200 needs to access, that is, may determine an operation instruction that the external device 200 needs to access.
The operation instruction may be regarded as a macro instruction set for an instruction request of the external device 200 to access the flash data. In assembly language programs, a macro is a piece of source program that represents a function. The macro instruction set in the register set 10 according to the embodiment of the present invention may be a code in the register set 10, where the code may represent an action of accessing flash data by the external device 200.
Referring to fig. 3, the external device 200 may transmit a code to the register set 10 to acquire a corresponding operation instruction. For example, the external device 20 transmits the code 0x05 to acquire an operation instruction indicating reading the FLASH, and the external device 20 transmits the code 0x06 to acquire an operation instruction indicating writing the FLASH.
In step S30, the instruction parsing module 20 may parse the acquired operation instruction into different parsed instruction signals, such as a read FLASH instruction, an erase FLASH instruction, a read-write cache (RAM) instruction of the external device 200, and the like, and send the resolved instruction signals to the instruction execution module 30.
The operation instruction obtained by the instruction parsing module 20 may be that the external device 200 reads an inner code of the register set 10, and the instruction parsing module 20 may determine an action of accessing flash data by the external device 200 represented by the inner code of the register set 10 by parsing the operation instruction.
Referring to fig. 3, the command parsing module 20 parses the operation command encoded with 0x05 to obtain a parsed command signal FlashRD, flashRD indicating a read FLASH command. The command parsing module 20 parses the operation command encoded with 0x06 to obtain a parsed command signal FlashWR, flashWR indicating a FLASH write command.
In step S40, the instruction execution module 30 may generate a corresponding instruction request according to the received parsed instruction signal, and send the instruction request to the flash memory controller 300, so that the flash memory controller 300 performs access to the flash memory data. The FLASH controller 300 is configured to generate control signals of the FLASH, including a start timing signal, an address selection signal, and a read/write enable signal, so that the external device 200 can access the FLASH.
Referring to fig. 3, when the instruction execution module 30 receives the parsed instruction signal FlashRD, the instruction execution module 30 sends an instruction request for reading the FLASH to the FLASH controller 300, so that the FLASH starts a corresponding address selection signal and enables a read-write signal, and the external device 200 can read the FLASH of the corresponding address. The external device 200 can access the register set 10 to realize the work flow of accessing FLASH, and has simple and fast execution speed.
In some embodiments, step S10 of obtaining the access signal of the external device 200 to the register set 10 includes: acquisition of access signals based on integrated circuit bus protocol
Preferably, the external device 200 may access the register set 10 based on the integrated circuit bus protocol (Inter-INTEGRATED CIRCUI, I2C). The I2C protocol is simple, flexible and widely supported and is commonly used to connect sensors, memory, display screens and other peripherals to microcontrollers, microprocessors or other integrated circuits.
The FLASH memory data access method and the FLASH memory data access device according to the embodiments of the present invention may be applied to the field of integrated circuits, the external device 200 may be a controller in the field of integrated circuits, and the external device 200 may perform corresponding operations by accessing FLASH based on an integrated circuit bus protocol. An integrated circuit bus is a simple bi-directional two-wire bus that is well suited for efficient interconnect control between a microcontroller and a peripheral, or between multiple microcontrollers. The external device 200 can communicate with the register set 10 by only one data line and one clock line, and the connection line is simple, which is beneficial to optimizing the space and cost of the connection line.
Referring to fig. 4 and 5, in some embodiments, the register set 10 includes an address register 12 and an instruction register 11, and an operation instruction is provided in the instruction register 11. The flash memory data access method comprises the following steps:
step S10, obtaining an access signal of the external device 200 to the register set 10;
step S21, determining the operation address of the external device 200 written into the address register 12 according to the access signal;
Step S22, determining an operation instruction of the external device 200 for accessing the instruction register 11 according to the access signal;
S30, analyzing the operation instruction to obtain an analyzed instruction signal;
Step S41, a corresponding command request is sent to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the operation address and the command request.
The operation instruction may be regarded as a macro instruction set for an instruction request of the external device 200 to access the flash data. In assembly language programs, a macro is a piece of source program that represents a function. The macro instruction set in the register set 10 of the present embodiment may be a code in the register set 10, and the code may indicate an action of accessing the flash data by the external device 200 and an address of accessing the flash data.
The external device 200 may write a FLASH address or a RAM address to which access needs to be performed to the address register 12, so that the FLASH register performs data access to the corresponding FLASH address or RAM address.
Specifically, when the external device 200 needs to read a certain RAM address or FLASH address data, the access signal sent by the external device 200 writes the corresponding RAM address or FLASH address into the address register 12. The access signal sent by the external device 200 accesses the corresponding operation instruction for reading the RAM or the operation instruction for reading the FLASH.
The instruction parsing module 20 parses an operation instruction indicating that the RAM or FLASH is read, and the instruction executing module 30 may send an instruction request indicating that the RAM or FLASH is read to the FLASH controller 300, where the FLASH controller 300 can read the data of the corresponding RAM address or FLASH address.
Referring to fig. 4, further, in some embodiments, the register set 10 further includes a data register 13. After sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, the flash memory data access method includes:
In the case where the instruction request is a write request, the operation data written into the data register 13 by the external device 200 is determined according to the access signal, so that the flash controller 300 writes the operation data to the operation address.
The external device 200 may write data to be written to the FLASH or RAM into the data register 13, so that the FLASH register writes corresponding data to the corresponding FLASH address or RAM address.
Specifically, when the external device 200 needs to write RAM data or FLASH data, the external device 200 writes a corresponding RAM address or FLASH address to the address register 12, and the instruction register 11 issues an operation instruction indicating writing of RAM data. The instruction parsing module 20 parses an operation instruction indicating writing of RAM data or writing of FLASH data, and the instruction execution module 30 may send an instruction request indicating writing of RAM data or writing of FLASH data to the FLASH controller 300.
When it is determined that the FLASH controller 300 performs a request for writing RAM data or FLASH data instructions, the external device 200 may write the corresponding RAM data or the corresponding FLASH data to the data register 13, and the FLASH controller 300 may write the corresponding RAM data to the corresponding RAM address or write the corresponding FLASH data to the corresponding FLASH address.
Referring to fig. 6, in some embodiments, step S30 of parsing the operation instruction to obtain a parsed instruction signal includes:
step S31, combining a plurality of operation instructions to obtain a combined operation instruction;
Step S32, analyzing a combined operation instruction to obtain an analyzed instruction signal.
The plurality of operation instructions can be combined, and functions which can be realized by the operation instructions after combination are similar to functions which can be realized by the operation instructions before combination.
Specifically, referring to fig. 3, an operation instruction ramRD representing write-once RAM and an operation instruction ramWR representing read-once RAM may be combined to obtain a new operation instruction. The instruction execution module 30 may send an instruction request to the flash controller 300 indicating that the RAM is written once and then read once, and the flash controller 300 performs the action of writing the RAM once and then reading the RAM once.
Referring to fig. 7, in some embodiments, parsing the operation instruction to obtain a parsed instruction signal includes:
s33, disassembling an operation instruction to obtain a plurality of disassembled operation instructions;
step S34, analyzing the plurality of disassembled operation instructions to obtain a plurality of analyzed instruction signals.
One operation instruction can be disassembled, and functions which can be realized by a plurality of disassembled operation instructions are similar to functions which can be realized by operation instructions before disassembly.
Specifically, referring to fig. 3, an operation instruction flash_pprog representing Flash page writing may be disassembled into an operation instruction representing Flash ready to write and an operation instruction for executing page writing.
In some embodiments, sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request, including:
In the case of the initialization state, the flash controller 300 is able to perform access to the flash data according to an instruction request, wherein the flash controller 300 is in the initialization state after completing the access to the flash data.
Specifically, referring to fig. 8, after the flash controller 300 performs all the processes of completing one instruction request, the instruction execution module 30 returns to the idle state. In the case of the instruction execution module 30 being in an idle state, the instruction execution module 30 waits to receive a new parsed instruction signal in order to issue a new instruction request.
Flash controller 300 is only able to execute one instruction request at a time. After the execution of the last instruction request by the flash controller 300 is completed, i.e., in the case where the system is in an initialized state, the flash controller 300 is able to execute the next instruction request. Correspondingly, when the instruction execution module 30 is executing the instruction request by the flash memory controller 300, the instruction execution module 30 does not issue a new instruction request to the flash memory controller 300.
In some implementations, the instruction request includes a write RAM request. Sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request, including: in the case where a write RAM request is sent to the flash controller 300, the flash controller 300 enters a write RAM state. The external device 200 may initiate a write-many RAM instruction to write multi-byte data to the data cache area of RAM by accessing the address register 12 and the data register 13 through the I2C.
In some implementations, the instruction request includes a flash instruction request. Sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request, including:
In the case that the fast recording command request is sent to the flash controller 300, the corresponding data is written into the corresponding buffer area, so that the external device 200 records the data in the corresponding buffer area.
Specifically, referring to fig. 8, in the case where the instruction execution module 30 sends a flash instruction request to the flash controller 300, the flash controller 300 enters a write RAM state. The external device 200 can access the address register 12 and the data register 13 through the I2C, and the external device 200 can write the current data register 13 into the RAM corresponding address area through the fast burning command, and then directly perform the FLASH burning process, so that the communication duration of the external device 200 is reduced.
In some implementations, the instruction request includes a burn instruction request. Sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request, including:
in the case where the burning command request is sent to the flash controller 300, the data of the flash preparation area is erased;
After completely erasing the data of the flash memory preparation area, the data inside the corresponding buffer area is written into the flash memory preparation area, so that the external device 200 burns the data of the flash memory preparation area.
Specifically, referring to fig. 8, in the case where a request for a burning instruction is sent to the FLASH controller 300, the FLASH controller 300 clears the data preparation area of FLASH, then performs an erase operation of FLASH, and waits for the completion of the erase operation. The FLASH memory controller 300 writes the data in the RAM buffer corresponding area into the data preparation area of the FLASH memory, and after the writing is completed, the FLASH memory controller executes the writing time sequence of the FLASH memory, and after the writing is completed, the instruction execution module 30 returns to the idle state after the instruction is completed.
It should be noted that, when executing the FLASH sequence of FLASH, the FLASH controller 300 needs to identify that the request of the writing command is FLASH page writing, FLASH block writing or FLASH full writing.
In some implementations, the instruction request includes an erase instruction request. Sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request, including:
in the case where an erase command request is sent to the flash controller 300, the data of the flash preparation area and the flash data are erased.
Specifically, referring to fig. 8, in the case where an erase command request is sent to the FLASH controller 300, the FLASH controller 300 clears the data preparation area of FLASH, then performs the erase operation of FLASH, waits for the erase to be completed, and then returns the command execution module 30 to the idle state.
It should be noted that, when executing the erase command request, the FLASH controller 300 needs to identify that the burn command request is FLASH page erase, FLASH block erase or FLASH full erase.
In some implementations, the instruction request includes a read RAM instruction request. Sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request, including:
Specifically, referring to fig. 8, in the case where a read RAM instruction request is sent to the flash controller 300, the flash controller 300 enters a read RAM state, reads data of a corresponding RAM address according to an operation address written in the address register 12 by the external device 200, and writes the read RAM data in the data register 13. The external device 200 can acquire RAM data to be read by accessing the data register 13.
In some embodiments, the instruction request comprises a read FLASH instruction request. Sending a corresponding command request to the flash memory controller 300 according to the parsed command signal, so that the flash memory controller 300 performs access to the flash memory data according to the command request, including:
Specifically, referring to fig. 8, in the case where a read FLASH command request is sent to the FLASH controller 300, the FLASH controller 300 enters a read FLASH state, reads data of a corresponding FLASH address according to an operation address written in the address register 12 by the external device 200, and writes the read FLASH data in the data register 13. The external device 200 can acquire FLASH data to be read by accessing the data register 13.
The embodiment of the invention provides an electric quantity calculation method, which comprises the following steps: the flash memory data is obtained by adopting the flash memory data access method of any one of the embodiments; acquiring an electric quantity calculation program according to the flash memory data; the electrical quantity is calculated according to an electrical quantity calculation program and an electrical parameter, wherein the electrical parameter comprises at least one of a current and a voltage.
Referring to fig. 9, an embodiment of the present invention also provides an electricity meter 400, the electricity meter 400 including an electrical parameter acquisition module 410 and a calculation module 420. The electrical parameter acquisition module 410 is configured to acquire an electrical parameter, where the electrical parameter includes at least one of a current and a voltage. The calculation module 420 is configured to calculate the electric power according to an electric power calculation program and an electric parameter, where the electric power calculation program is determined based on the flash memory data access method according to any one of the above embodiments.
In some embodiments, the power calculation method may be implemented by the power meter 400, that is, the power meter 400 is used to implement the power calculation method.
Of course, in other embodiments, the power calculation method may be implemented by other devices or apparatuses, and is not limited to implementation by the power meter 400. The electricity meter 400 may not be dedicated to the implementation of the electricity calculation method according to the embodiment of the present invention, but may implement other functions and methods.
Specifically, the external device 200 may be a controller in the integrated circuit field, or may be a single chip microcomputer.
Further, the flash memory can be used as a program memory of the singlechip, the singlechip can acquire a corresponding electric quantity calculation program by reading the flash memory data, and the singlechip can calculate the electric quantity according to the acquired electric quantity calculation program and the electric parameters.
Embodiments of the flash memory data access method may refer to the above embodiments, and the benefits of the electricity amount calculation method and the electricity amount meter 400 include all the benefits of the flash memory data access method, which are not described herein in detail.
Embodiments of the present invention provide a computer-readable storage medium. The computer readable storage medium is used for storing a computer program, and when the computer readable storage medium is executed, the computer readable storage medium realizes the flash memory data access method or the electric quantity calculation method of any one of the above embodiments.
Embodiments of the flash memory data access method and the electric quantity calculation method may refer to the above embodiments, and the beneficial effects of the computer readable storage medium include all the beneficial effects of the flash memory data access method and the electric quantity calculation method, which are not described herein in detail.
The embodiment of the invention provides a flash memory data access method, an electric quantity calculation device and a storage medium. The flash memory data access method comprises the following steps: acquiring an access signal of the external device 200 to the register set 10; determining a corresponding operation instruction according to the access signal, wherein the operation instruction is arranged in the register group 10; analyzing the operation instruction to obtain an analyzed instruction signal; and sending a corresponding instruction request to the flash memory controller 300 according to the analyzed instruction signal, so that the flash memory controller 300 executes access to the flash memory data according to the instruction request. The external device 200 may access a FLASH data access device to issue a corresponding instruction request to the FLASH controller 300, and the FLASH controller 300 may access FLASH data (FLASH) according to the received instruction request.
Compared with the external device 200 accessing the FLASH controller 300 through complex instructions, the external device 200 accessing the FLASH through sending the coded access register set 10 has simpler workflow, reduces the complexity of the workflow of the software program of the external device 200 and has faster execution speed. The FLASH controller 300 can execute access to the FLASH data according to the received instruction request, and the FLASH controller 200 can separate the instruction parsing module 20 and the instruction executing module 30 without additionally parsing the received instruction request, so that the complexity of the FLASH controller 300 can be reduced, and the access efficiency, flexibility and reliability of the external device 200 to the FLASH are improved.
In the description of the present specification, reference is made to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., meaning that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the term "coupled" is to be broadly interpreted and includes, for example, either permanently coupled, detachably coupled, or integrally coupled; can include direct connection, indirect connection through intermediate media, and communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (9)

1. A method for accessing flash memory data, comprising:
the method comprises the steps of obtaining an access signal of external equipment to a register set, wherein the register set comprises an address register, an instruction register and a data register, and an operation instruction is arranged in the instruction register;
Determining an operation address of the external device written into the address register according to the access signal;
determining an operation instruction of the external device for accessing the instruction register according to the access signal;
analyzing the operation instruction to obtain an analyzed instruction signal;
sending a corresponding instruction request to a flash memory controller according to the analyzed instruction signal, so that the flash memory controller executes access to flash memory data according to the operation address and the instruction request;
and under the condition that the instruction request is a write-in request, determining operation data written into the data register by the external equipment according to the access signal so as to enable the flash memory controller to write the operation data into the operation address.
2. The method for accessing flash memory data according to claim 1, wherein the step of obtaining the access signal of the external device to the register set comprises:
the access signal is acquired based on an integrated circuit bus protocol.
3. The method of claim 1, wherein parsing the operation instruction to obtain a parsed instruction signal comprises:
Combining a plurality of the operation instructions to obtain a combined operation instruction;
And analyzing one of the combined operation instructions to obtain one analyzed instruction signal.
4. The method of claim 1, wherein parsing the operation instruction to obtain a parsed instruction signal comprises:
disassembling one operation instruction to obtain a plurality of disassembled operation instructions;
And analyzing a plurality of the disassembled operation instructions to obtain a plurality of analyzed instruction signals.
5. The method of claim 1, wherein the command request includes a burn command request, and the sending the corresponding command request to the flash memory controller according to the parsed command signal, so that the flash memory controller performs access to the flash memory data according to the command request, includes:
Under the condition that the burning command request is sent to the flash memory controller, erasing data of a flash memory preparation area;
After the data in the flash memory preparation area is completely erased, the data in the corresponding cache area is written into the flash memory preparation area, so that the external equipment burns the data in the flash memory preparation area.
6. The method of claim 1, wherein the command request includes a flash command request, and the sending the corresponding command request to the flash controller according to the parsed command signal, so that the flash controller performs access to the flash data according to the command request, includes:
And under the condition that the rapid burning instruction request is sent to the flash memory controller, writing the corresponding data into the corresponding cache area so as to enable the external equipment to burn the data in the corresponding cache area.
7. The method of claim 1, wherein the sending a corresponding command request to the flash memory controller according to the parsed command signal, so that the flash memory controller performs access to the flash memory data according to the command request, comprises:
In the case of an initialization state, the flash memory controller is capable of executing access to the flash memory data according to the instruction request, wherein the flash memory controller is in the initialization state after completing the access to the flash memory data.
8. A flash data access device, the flash data access device comprising:
The register set comprises an address register and an instruction register, wherein an operation address is arranged in the address register, an operation instruction is arranged in the instruction register, the address register is used for determining an operation address of writing the external device into the address register according to an access signal of the external device to the register set, and the instruction register is used for determining an operation instruction of accessing the instruction register by the external device according to the access signal;
The instruction analysis module is used for analyzing the operation instruction to obtain an analyzed instruction signal;
The instruction execution module is used for sending a corresponding instruction request to the flash memory controller according to the analyzed instruction signal so that the flash memory controller can execute access to flash memory data according to the instruction request;
The register set further comprises a data register, wherein operation data are arranged in the data register, and when the instruction request is a write-in request, the data register determines the operation data written into the data register by the external device according to the access signal so as to enable the flash memory controller to write the operation data into the operation address.
9. A computer readable storage medium for storing a computer program, which when executed implements the flash memory data access method of any one of claims 1-7.
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CN116820491A (en) * 2022-03-21 2023-09-29 华为技术有限公司 Flash memory burning device and equipment

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1139149A (en) * 1997-07-23 1999-02-12 Matsushita Electric Ind Co Ltd Information processor and rewrite method for rewritable nonvolatile memory
CN101498994A (en) * 2009-02-16 2009-08-05 华中科技大学 Solid state disk controller
CN104598402A (en) * 2014-12-30 2015-05-06 北京兆易创新科技股份有限公司 Flash memory controller and control method of flash memory controller
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