CN117370099A

CN117370099A - Micro-processing chip and code downloading method

Info

Publication number: CN117370099A
Application number: CN202311385588.2A
Authority: CN
Inventors: 陈思恒; 张晓旭; 倪有粮; 刘智力
Original assignee: Hangzhou Shuotian Technology Co ltd
Current assignee: Hangzhou Shuotian Technology Co ltd
Priority date: 2023-10-23
Filing date: 2023-10-23
Publication date: 2024-01-09

Abstract

The present application relates to the field of chip testing technologies, and in particular, to a micro-processing chip and a code downloading method. The micro-processing chip is provided with a first-in first-out FIFO module, a state machine, a bus module and a storage module; the FIFO module is used for receiving a test excitation signal based on an external clock and performing time domain conversion on the test excitation signal; the state machine is used for encoding the test excitation signal after the time domain conversion into a bus signal; the bus module is used for transmitting the bus signal to the storage module so as to realize downloading storage and/or programming of code data. The micro-processing chip and the code downloading method are beneficial to improving the downloading speed of code data and improving the testing efficiency of the chip.

Description

Micro-processing chip and code downloading method

Technical Field

The present application relates to the field of chip testing technologies, and in particular, to a micro-processing chip and a code downloading method.

Background

With the widespread use of System on chip (SoC) in recent years, solving the problem of testability of SoC chips has become a hotspot for attention and research. The chip is mainly tested twice in the production process: wafer Test (CP) and Final Test (FT). The FT test is to test the packaged chip, and generally requires more stringent requirements to detect the chip with failure as much as possible. In the related art, the test codes are generally downloaded into the chip and tested by a joint test working group (Joint Test Action Group, JTAG), but the method has the problems of low downloading speed, and influence on the test efficiency and the test cost of the chip.

Disclosure of Invention

In view of this, the present application provides a micro-processing chip and a code downloading method, which are helpful for improving the downloading speed of code data and improving the testing efficiency of the chip.

In a first aspect, embodiments of the present invention provide a micro-processing chip provided with a first-in first-out (First Input First Output, FIFO) module, a state machine, a bus module, and a memory module; wherein,

the FIFO module is used for receiving a test excitation signal based on an external clock and performing time domain conversion on the test excitation signal;

the state machine is used for encoding the test excitation signal after the time domain conversion into a bus signal;

the bus module is used for transmitting the bus signal to the storage module so as to realize downloading storage and/or programming of code data.

In some embodiments, the test stimulus signal comprises: one or more of a reset signal, code length information, incoming start address, code data, data valid signal, end of transmission flag, wherein:

the reset signal is used for resetting the external clock and the FIFO module;

the code length information is used for counting the transmitted code data and/or is used for checking the data after the code data transmission is finished;

The incoming start address is used for indicating a storage start address of the code data;

the code data takes a designated address as a storage starting address and is stored in an address increment mode;

the data valid signal is used for indicating that the code data which is currently transmitted into the data processing device is valid data;

the transmission end mark is used for indicating the transmission end of the code data and indicating the CRC check of the code data and transmitting the check result to the outside.

In some embodiments, the FIFO module is an asynchronous FIFO to enable temporary storage and clock domain conversion of the code data;

the FIFO module comprises: a multi-bit code signal pin; when the test stimulus signal includes the code data and the incoming launch address, the code data and the incoming launch address time-division multiplex the multi-bit code signal pin.

In some embodiments, the micro-processing chip is further provided with a verification module;

the verification module comprises a sending end and a receiving end, wherein the sending end is used for receiving data transmitted by an IO port of the micro-processing chip, and the receiving end is connected with a read data port of the FIFO module;

the checking module is specifically configured to perform CRC check calculation on the code data acquired by the receiving end and the CRC initial value, obtain a CRC check result, and store the CRC check result in the data register temporarily; when the receiving end acquires the next effective code data, performing CRC check calculation on the currently acquired code data and a CRC check result stored in the data register to obtain a new CRC check result; when the code data transmission is finished, comparing the CRC check result obtained by final calculation with a CRC reference value obtained from the outside, and if the comparison is consistent, keeping the alarm signal at a low level; if the comparison is inconsistent, the alarm signal is pulled high.

In some embodiments, the state machine comprises:

an idle state, wherein the state machine is in the idle state when the bus module is reset and idle, and the FIFO module is switched to a bus request state from the idle state when receiving effective data;

the bus request state is used for initiating a bus receiving request to the bus module, switching to the starting state after the bus module responds to the bus receiving request, and unconditionally jumping to the address and command transmission state from the starting state;

the address and command transmission state is used for sending the address and command contained in the test excitation signal to the bus module and jumping to the data transmission state when the bus module is idle;

the data transmission state is used for transmitting code data contained in the test excitation signal to the bus module, and when the bus module is idle and the transmission of the code data is not finished, the address and command transmission state is skipped;

and the check state is used for entering a state of CRC check on the code data when the code data transmission is finished, and unconditionally jumping to the idle state after the check on the code data is finished.

In a second aspect, an embodiment of the present invention provides a method for downloading code of a microprocessor chip, where the method includes:

Receiving a test excitation signal based on an external clock, and performing time domain conversion on the test excitation signal;

encoding the time-domain converted test excitation signal into a bus signal;

the bus signals are stored to enable download storage and/or programming of code data.

the reset signal is used for resetting the external clock and the FIFO module, has the beneficial effects that the external clock and the drive excitation signal and related logic are reset, and the reset signal is used for resetting the related logic when downloading is started each time, so that the occurrence of an uncertain state is prevented;

the code data takes the designated address as a storage initial address and is stored in an address increment mode, so that the programming and downloading of the storage equipment into a preset distribution area can be realized, and the utilization and programming flexibility of the storage equipment are improved;

the transmission end mark is used for indicating the transmission end of the code data and indicating the CRC check of the code data and transmitting the check result to the outside;

advantageous effects of the combination of code length information and code data: the code downloading realizes the verification of the data after the transmitting end and the chip cross clock domain, and the CRC hardware realizes the algorithm to verify the initial address and the data information, so as to prevent the effective signal from abnormal after passing through the chip IO and the chip cross clock domain.

In some embodiments, the method further comprises:

when effective code data is obtained, performing CRC check calculation on the code data and a CRC initial value to obtain a CRC check result and temporarily storing the CRC check result in a data register;

when the receiving end acquires the next effective code data, performing CRC check calculation on the currently acquired code data and a CRC check result stored in the data register to obtain a new CRC check result;

when the code data transmission is finished, comparing the CRC check result obtained by final calculation with a CRC reference value obtained from the outside, and if the comparison is consistent, keeping the alarm signal at a low level; if the comparison is inconsistent, the alarm signal is pulled high.

In some embodiments, the encoding the time-domain converted test stimulus signal into the bus signal includes a state transition of a state machine, including:

In some embodiments, the test stimulus signal containing the code data can be encoded into a bus signal and transmitted to the memory module for storage, in such a way that the code data in the memory module is not modified, and the code data is downloaded and stored in the memory module.

In some embodiments, the test stimulus signal containing the code data may be encoded as a bus signal and transmitted into the memory module to instead store a portion of the code data in the memory module, in such a way that there may be modifications to the code data in the memory module, programming of the code data in the memory module may be accomplished.

In the embodiment of the invention, the FIFO module is used for carrying out time domain conversion on the externally input test excitation signal, thereby being beneficial to the transmission of the test excitation signal among the modules of the micro-processing chip. In addition, the embodiment of the invention converts the test excitation signal into the bus signal, and the code data can be transmitted to other modules or memories of the micro-processing chip in a bus mode through the bus architecture inside the micro-processing chip, so that the downloading storage or programming function of the code data is realized. Compared with a single-wire downloading mode, the embodiment of the invention adopts a bus mode to download the code data, thereby being beneficial to improving the code downloading speed and improving the testing efficiency of the chip.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a micro-processing chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another micro-processing chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a micro-processing chip according to another embodiment of the present invention;

FIG. 4 is a flowchart of a method for downloading code of a micro-processing chip according to an embodiment of the present invention;

FIG. 5 is a flowchart of another method for downloading code from a microprocessor chip according to an embodiment of the present invention;

FIG. 6 is a flowchart of a method for performing CRC check on code data according to an embodiment of the present invention;

fig. 7 is a state transition schematic diagram of a state machine according to an embodiment of the present invention.

Detailed Description

For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Referring to fig. 1, a schematic structural diagram of a micro-processing chip according to an embodiment of the present invention is provided. The micro-processing chip shown in fig. 1 may be a control module, a digital signal processing (Digital Signal Processing, DSP) chip, a microprocessor (Micro Processor Unit, MPU), a micro CPU, or the like, which can process digital signals, analog signals, or a micro central control chip, a system on chip, or the like, which can perform functions such as signal control, instruction processing, and operation, and the chip implementation form of the micro-processing chip is not particularly limited in the embodiment of the present invention.

In order to realize downloading of codes and chip testing in a micro-processing chip, the embodiment of the invention is provided with a downloading hardware module in the micro-processing chip. As shown in fig. 1, the download hardware module includes a FIFO module, a state machine, a bus module, and a memory module. The FIFO module can be connected with a test signal generating module outside the chip to receive the test excitation signal generated by the test signal generating module. Alternatively, the test signal generation module and the microprocessor chip may employ different clocks. And after receiving the test excitation signal based on the external clock, the FIFO module performs time domain conversion on the test excitation signal. I.e. the FIFO module converts the test stimulus signal based on the external clock into a signal based on the clock of the micro-processing chip. The FIFO module transmits the test excitation signal after time domain conversion to the state machine. The state machine is used for encoding the test excitation signal after the time domain conversion into a bus signal and sending the bus signal to the bus module. The bus module is used for transmitting bus signals to the memory module so as to realize the downloading storage and/or programming of the code data. In some embodiments, the FIFO module may be an asynchronous FIFO for implementing temporary storage and clock domain conversion of code data.

Referring to fig. 2, a schematic structural diagram of another micro-processing chip according to an embodiment of the present invention is provided. The micro-processing chip shown in fig. 2 further comprises a verification module based on the micro-processing chip structure shown in fig. 1. The verification module is used for carrying out CRC (cyclic redundancy check) on the code data contained in the test excitation signal, and generating an alarm signal when the verification fails. In the embodiment of the invention, the code data can be prevented from being abnormal after passing through the chip IO port and the cross-clock domain through CRC (cyclic redundancy check) of the code data.

As shown in fig. 2, the verification module may include a transmitting end and a receiving end, where the transmitting end is used to receive data transmitted by the IO port of the micro-processing chip, and the receiving end is connected to the read data port of the FIFO module. The checking module is specifically configured to perform CRC check calculation on the code data acquired by the receiving end and the CRC initial value, obtain a CRC check result, and store the CRC check result in the data register temporarily. When the receiving end acquires the next effective code data, the checking module performs CRC check calculation on the currently acquired code data and the CRC check result stored in the data register to obtain a new CRC check result. When the code data transmission is finished, comparing the CRC check result obtained by final calculation with a CRC reference value obtained from the outside, and if the comparison is consistent, keeping the alarm signal at a low level; if the comparison is inconsistent, the alarm signal is pulled high.

Referring to fig. 3, a schematic structural diagram of a further micro-processing chip according to an embodiment of the present invention is provided. In the architecture shown in fig. 3, the bus modules shown in fig. 1 and 2 may be implemented as an AHB host interface and the memory modules may be implemented as SRAMs. The AHB host interface is connected with the SRAM through the AMBA AHB. In the micro-processing chip shown in fig. 3, the FIFO module converts the time domain of the externally input test excitation signal, so the state machine, the AHB host interface, the AMBA AHB, the SRAM and the verification module are all local clock domains of the micro-processing chip. The input part of the FIFO module is the external clock domain.

The externally transmitted test stimulus signals will be described below in connection with the micro-processing chip shown in fig. 1-3.

In some embodiments, the test stimulus signal may include: one or more of a reset signal, code length information, an incoming start address, code data, a data valid signal, an end of transmission flag. Wherein:

and a reset signal for resetting the external clock and the FIFO module. The external clock and associated logic driving the stimulus signal may be reset by a reset signal. The reset signal may be used to reset the associated logic at each download initiation to prevent the occurrence of an indeterminate state.

The code length information is used for counting the transmitted code data and/or is used for data verification after the code data transmission is finished. And carrying out data verification on the code data after the clock domain crossing of the chip sending end and the chip inside based on the code length information. Optionally, the data check may be a CRC check, that is, checking the start address and the data information by using a CRC hardware implementation algorithm, so as to prevent the code data from being abnormal after passing through the chip IO and the clock domain crossing.

And the incoming start address is used for indicating a storage start address of the code data, so that the code data can be conveniently downloaded to a preset distribution area of the storage module.

The code data is stored with the designated address as a storage start address and in an address increment manner. The storage mode of the code data is beneficial to downloading and storing the code data to a preset distribution area of the storage module, and improves the utilization and programming flexibility of the storage device. And the storage mode of the code data supports continuous writing of data to addresses increasing according to word and continuous writing of data to different addresses.

And the data valid signal is used for indicating that the currently incoming code data is valid data.

And a transmission end mark for indicating the end of transmission of the code data and for indicating the CRC check of the code data and transmitting the check result to the outside. The signal conditions that the test stimulus signal may contain will be described below in connection with various embodiments.

In some embodiments, the test stimulus signal received externally by the FIFO module may include code data and a data valid signal. The code data may be test code or the like that needs to be downloaded. The data valid signal is used to indicate that the currently incoming code data is valid data. Optionally, the currently incoming code data is transferred to the memory module in the form of bus data after time domain conversion of the FIFO module and bus format conversion of the state machine. The code data is stored in an address increment mode by taking a designated address as a storage starting address when the storage module stores the code data. In the embodiment of the invention, the code data takes the designated address as the storage initial address and is stored in an address increasing mode, which supports continuous writing of data to the address increasing according to word and continuous writing of data to different addresses, thereby realizing the ordered storage of the code data in the storage module. In some embodiments, the specified address may be a fixed address that is preset; in other embodiments, the specified address may be an externally incoming address. For example, the externally input test stimulus signal includes an incoming start address, and the incoming start address inputted from the outside is used to indicate the specified address. In some embodiments, the FIFO module comprises: a multi-bit code signal pin; when the test stimulus signal includes the code data and the incoming launch address, the code data and the incoming launch address time-division multiplex the multi-bit code signal pins.

In some embodiments, the test stimulus signal received externally by the FIFO module comprises a reset signal, code data, a data valid signal, and an end of transmission flag. Before code data transmission starts, the FIFO module acquires a reset signal from the outside of the chip, and an external clock and the FIFO module can be reset through the reset signal. The FIFO module then obtains the code data and the data valid signal. When the FIFO module receives the transmission end flag, it determines that the code data transmission is ended.

In some embodiments, a transmission start flag may also be included in the test stimulus signal. The FIFO module receives the transmission start flag indicating the start of the code data transmission after receiving the reset signal. Alternatively, the transmission start flag and the transmission end flag may be time-multiplexed with the same signal pin of the FIFO module. The signal pin may be set to a first voltage signal for use as a transmission start flag before the start of the code data transmission. When the code data transmission is completed, the signal pin may be set to a second voltage signal, which is used as a transmission end flag. Alternatively, the first voltage signal may be a high level signal, and the second voltage signal may be a low level signal.

In some embodiments, the test stimulus signal received externally by the FIFO module may include code data, a data valid signal, and an end of transmission flag. In this embodiment the transmission of the code data is started directly, without setting a reset signal before the code data transmission.

In some embodiments, the test stimulus signal may include only a reset signal when the micro-processing chip is in a particular time period, such as when the micro-processing chip is in a reset state.

In the above embodiments, the CRC check on the code data is not considered. In other embodiments, a CRC check mechanism may be designed. For example, the test stimulus signal received from the outside by the FIFO module includes a reset signal, code data, a data valid signal, and an end-of-transmission flag. Before code data transmission starts, the FIFO module acquires a reset signal from the outside of the chip, and an external clock and the FIFO module can be reset through the reset signal. The FIFO module then obtains the code data and the data valid signal. When the FIFO module receives the transmission end flag, it determines that the code data transmission is ended and initiates a CRC check on the code data. Specifically, the code data may be CRC checked by a check module.

In some embodiments, a custom test stimulus signal is provided. The custom test stimulus signal may include a reset signal, a multi-bit code signal, a data valid signal, and a download initiation end flag signal. The functions of the reset signal and the data valid signal are described above and will not be described in detail here. The multi-bit code signal and the download initiation end flag signal will be further described below.

In some embodiments, a multi-bit code signal may be used to represent the incoming boot address described above at the beginning of a code data download, and thereafter used to represent the code data. In a specific implementation, the FIFO module may have a multi-bit code signal pin, and the incoming start address and the code data may be time-multiplexed with the multi-bit code signal pin to respectively obtain the incoming start address and the code data inputted from the outside. In other embodiments, the code length information, the incoming boot address, and the code data may be time-multiplexed with the multi-bit code signal pins, thereby respectively obtaining externally input code length information, incoming boot address, and code data. In the embodiment of the invention, the signal pins of the FIFO module are multiplexed by various signal time sharing, so that the number of IO ports of the micro-processing chip can be reduced.

In some embodiments, the download start end flag signal is a first voltage signal when downloading the code data is started, and indicates that the code data starts to be transmitted, that is, the transmission start flag. When the code data transmission is finished, the download starting end mark signal is a second voltage signal to indicate the code data transmission is finished, namely, the download starting end mark signal corresponds to the transmission end mark. In some embodiments, the first voltage signal may be a high level signal and the second voltage signal may be a low level signal. Alternatively, the first voltage signal and the second voltage signal may occupy the same signal pin of the FIFO module. In some embodiments, the transmission end identifier may be used to instruct the checking module to perform CRC checking on the code data and transmit the checking result to the outside, in addition to indicating the transmission end of the code data.

In connection with the micro-processing chip shown in fig. 1 to 3, the embodiment of the invention provides a code downloading method of the micro-processing chip. As shown in fig. 4, the processing steps of the method include:

and 401, the FIFO module receives the test excitation signal based on the external clock, performs time domain conversion on the test excitation signal, and transmits the test excitation signal after the time domain conversion to the state machine.

The state machine encodes the time-domain converted test stimulus signal into a bus signal 402.

403, the bus module transmits bus signals to the memory module to enable download storage and/or programming of the code data.

In the embodiment of the invention, the FIFO module is used for carrying out time domain conversion on the externally input test excitation signal, thereby being beneficial to the transmission of the test excitation signal among the modules of the micro-processing chip. And the code data is downloaded in a bus form, so that the downloading speed of the code data is improved, and the testing efficiency of the chip is improved.

Referring to fig. 5, a flowchart of another method for downloading code of a micro-processing chip according to an embodiment of the present invention is provided. In the embodiment of the present invention, the test excitation signal includes a reset signal, code length information, an incoming start address, code data, a data valid signal, and a download start end flag signal. As shown in fig. 5, the process of downloading code data by the micro processing chip includes:

501, the FIFO module receives an externally input reset signal, and performs clock and logic reset on an external clock and the FIFO module through the reset signal. In some embodiments, the FIFO module may transmit a reset signal to the verification module and clock and logically reset the verification module.

And 502, the FIFO module receives code length information input from the outside, and transmits the code length information to the verification module after time domain conversion. The code length information can be used for counting the code data transmitted subsequently and/or checking the code data after the code data transmission is finished.

503, the fifo module receives the input start address input from the outside, and sends the input start address to the state machine after time domain conversion, and the state machine converts the input start address into a bus format and sends the converted input start address to the bus module. The incoming start address is used to represent a storage start address of the code data that is subsequently incoming. As shown in fig. 3, the state machine may send an incoming boot address to the AHB host interface, which may store the subsequently transmitted code data in the SRAM according to the incoming boot address.

And 504, the FIFO module receives the externally input download start end mark signal, code data and data effective signal, and transmits the download start end mark signal, the code data and the data effective signal to the state machine after time domain conversion, and the state machine converts the download start end mark signal, the code data and the data effective signal into a bus format and transmits the bus format to the bus module.

The download start end flag signal may be a high level signal to indicate the start of code data transmission as a transmission start flag, and the download start end flag signal remains high level during the code data transmission. The data valid signal is used to indicate that the currently incoming code data is valid data. After the bus module (e.g., the AHB host interface in fig. 3) receives the code data, the incoming boot address may be used as a storage start address and stored in an address increment manner in the memory module (e.g., the SRAM in fig. 3).

505, when the download start end flag signal is at a low level, the download start end flag signal is used as a transmission end flag to indicate that the code data transmission is ended, and the state machine instructs the verification module to verify the code data.

506, after the code data is successfully checked by the checking module, a check success signal is sent to the state machine, and the state machine determines that the current downloading of the code data is finished. Optionally, if the verification module fails to verify the code data, the verification module may send out an alarm signal.

In step 504, a download start end flag signal for indicating that the code data starts to be transmitted may be sent after the reset signal and before the code length information; of course, the code length information may be transmitted after the code data is transmitted. The transmission timing of each signal can be adjusted according to the actual situation.

By the method, orderly and reliable downloading of the code data can be realized, an uncertain state in the process of downloading the code data is prevented, and the code data is prevented from being abnormal after passing through the chip IO port and the clock domain crossing.

Referring to fig. 6, a flowchart of a method for performing CRC check on code data is provided in an embodiment of the present invention. The processing steps of the method as shown in fig. 6 may include:

601, the fifo module receives the first code data input from the outside, performs time domain conversion on the first code data, and sends the first code data to the verification module. It will be appreciated that the FIFO time-domain converted first code data is also sent to the state machine for storage in the memory module.

And 602, performing CRC calculation by the checking module by using the CRC initial value and the first code data to obtain a first CRC checking result.

603, the fifo module receives the second code data input from the outside, performs time domain conversion on the second code data, and sends the second code data to the verification module. It will be appreciated that the FIFO time-domain converted second code data is also sent to the state machine for storage in the memory module.

And 604, performing CRC calculation on the first CRC check result and the second code data by the check module to obtain a second CRC check result.

605, the checking module repeats the above steps 603 and 604 until the last data of the code data to be downloaded is received, and obtains the final calculated CRC check result.

The verification module receives 606 the externally entered CRC reference value.

607, the checking module compares the finally calculated CRC result with the CRC reference value, if the comparison is consistent, the alarm signal keeps low level; if the comparison is inconsistent, the alarm signal is pulled high.

In some embodiments, the check module may utilize the code length information to count the code data or participate in the calculation of the CRC check result when calculating the CRC check result for the code data.

In the embodiment of the invention, the code data sent to the verification module is subjected to input and clock domain crossing conversion of the IO port of the FIFO module. The CRC of the code data through the checking module can prevent the code data from being abnormal after passing through the chip IO port and crossing clock domains.

Referring to fig. 7, a state transition diagram of a state machine according to an embodiment of the present invention is provided. As shown in fig. 7, the state machine includes: IDLE state (IDLE state), bus request state (BUSREQ state), START state (START state), address and command transfer state (ADDR state), data transfer state (WD state), and check state (CRC state). Wherein the transition conditions between the states are:

and in an IDLE state, when the FIFO module receives the reset signal and the AHB bus is in an IDLE state, the state machine is in the IDLE state. When the FIFO receives valid data, it switches from the idle state to the BUSREQ state. The FIFO receives valid data, for example, may be any one or more of code length information, an incoming start address, a download start end flag signal, and a data valid signal.

And the BUSREQ state, after the FIFO receives the effective data and switches to the BUSREQ state, the state machine initiates a bus receiving request to the AHB host interface, and the AHB host interface jumps to the START state after responding to the bus receiving request and jumps from the START state to the ADDR state unconditionally.

And an ADDR state, in which the state machine transmits addresses and commands contained in the test stimulus signals to the AHB host interface, and jumps to the WD state when the AHB bus is idle. The addresses and commands transmitted by the state machine to the AHB host interface may include an incoming start address, a download start end flag signal, a data valid signal, and the like. When the state machine transmits the incoming start address to the AHB host interface, the AHB host interface uses the incoming start address as a storage start address for subsequently incoming code data.

And in the WD state, the AHB host interface downloads code data to the storage module through the AHB bus. When the AHB bus is idle and the transfer of code data is not complete, the state machine jumps back to the ADDR state until code data is received again.

And the CRC state is that when the downloading starting ending mark signal indicates that the code data transmission is ended, the state machine jumps to the CRC state and performs CRC on the code data through the check module, and when the check module finishes checking the code data, the state machine jumps to the IDLE state unconditionally.

In the embodiment of the invention, the downloading process of the code data can be in line with the time sequence of the AHB host interface by controlling the state transition conditions of the state machine, thereby being beneficial to downloading the code data into the storage module through the AHB bus.

It should be understood that the division of the various modules of the micro-processing chip shown in fig. 1-3 is merely a division illustration and that the various modules may be physically combined or separated in a particular implementation. On the basis of not considering the division of each module in the micro-processing chip, the embodiment of the invention also provides a code downloading method of the micro-processing chip, which comprises the following steps:

encoding the time-domain converted test excitation signal into a bus signal;

the reset signal is used for resetting the external clock and the FIFO module;

In some embodiments, the method further comprises: when effective code data is obtained, performing CRC check calculation on the code data and a CRC initial value to obtain a CRC check result and temporarily storing the CRC check result in a data register;

In some embodiments, the storing of the bus signal to enable download storage and/or programming of the code data includes: the test excitation signal containing the code data can be encoded into a bus signal and transmitted to the storage module for storage, so that the code data is downloaded and stored in the storage module; and/or

The test stimulus signal containing the code data is encoded into a bus signal and transmitted into the memory module to replace a portion of the code data in the memory module for programming the code data in the memory module.

The parts of the implementation process and the beneficial effects of the method according to the embodiments of the present invention that are not described in detail may be referred to in the relevant descriptions of fig. 1 to fig. 7, and are not described here again.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein can be implemented as a combination of electronic hardware, computer software, and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described micro-processing chip may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein. The foregoing is merely specific embodiments of the present application, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present application, which should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The micro-processing chip is characterized by comprising a FIFO module, a state machine, a bus module and a storage module; wherein,

2. The chip of claim 1, wherein the test stimulus signal comprises: one or more of a reset signal, code length information, incoming start address, code data, data valid signal, end of transmission flag, wherein:

The reset signal is used for resetting the external clock and the FIFO module;

3. The chip of claim 2, wherein the FIFO module is an asynchronous FIFO for implementing temporary storage and clock domain conversion of the code data;

4. The chip of claim 1, wherein the micro-processing chip is further provided with a verification module;

5. The chip of claim 1, wherein the state machine comprises:

6. A code downloading method of a micro-processing chip, the method comprising:

encoding the time-domain converted test excitation signal into a bus signal;

7. The method of claim 6, wherein the test stimulus signal comprises: one or more of a reset signal, code length information, incoming start address, code data, data valid signal, end of transmission flag, wherein:

The reset signal is used for resetting the external clock and the FIFO module;

8. The method of claim 6, wherein the method further comprises:

9. The method of claim 8, wherein encoding the time-domain converted test stimulus signal into a bus signal comprises state transitions of a state machine, comprising:

10. The method of claim 6, wherein storing the bus signal to enable download storage and/or programming of the code data comprises: the test excitation signal containing the code data can be encoded into a bus signal and transmitted to the storage module for storage, so that the code data is downloaded and stored in the storage module;

and/or