CN117334733A - N-substrate groove type GaN insulated gate bipolar transistor for controlling hole injection efficiency - Google Patents
N-substrate groove type GaN insulated gate bipolar transistor for controlling hole injection efficiency Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000002347 injection Methods 0.000 title claims abstract description 23
- 239000007924 injection Substances 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims abstract description 25
- 230000002146 bilateral effect Effects 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 5
- 230000007246 mechanism Effects 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000000605 extraction Methods 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 description 55
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 55
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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Abstract
The invention relates to an N-substrate groove type GaN insulated gate bipolar transistor for controlling hole injection efficiency, belonging to the field of power semiconductor devices. The transistor is of a bilateral symmetry structure, and the left half structure comprises a P+ collector region, a P-collector region, an N-buffer region, an N-drift region, a P-body region, an N+ emitter substrate, and an insulating medium layer Al 2 O 3 The metal-to-metal contact area of grid electrode, metal-to-metal Ni contact area of collector electrode, metal-to-metal Ni/Ti contact area of emitter electrode and metal-to-metal Ti/Al/Ni/Au contact area of emitter electrode. The high doped P+ region is a collector injection region, and is used as an unbalanced hole injection mechanism when the device is turned on in the forward direction, the low doped P-region is a low electron barrier region and is used as an unbalanced electron extraction mechanism of the drift region, so that the current tailing phenomenon when the device is turned off can be effectively improved, and the device has lower turn-off timeAnd the turn-off loss of the device in the switching process is reduced.
Description
Technical Field
The invention belongs to the field of power semiconductor devices, and relates to an N-substrate groove type GaN insulated gate bipolar transistor for controlling hole injection efficiency.
Background
With the development of semiconductor technology, the performance of conventional Si and GaAs semiconductor devices has approached the theoretical limit imposed by the materials themselves. The third generation semiconductor, represented by gallium nitride (GaN), has the outstanding advantages of wide band gap, high saturation drift velocity, high critical breakdown electric field and the like, and becomes an ideal substitute material for manufacturing high-power, high-frequency, high-temperature and radiation-resistant electronic devices. Compared with Si and GaAs, the GaN has a forbidden band width of 3.4EV, is very suitable for being used as a high-voltage power device, is suitable for working in a high-temperature and high-radiation environment, has a Baliga figure of merit of 1450, and is far ahead of other semiconductor materials, so that the GaN is more suitable for being used as a power electronic device.
The IGBT (Insulated Gate Bipolar Transistor) is a bipolar semiconductor power device combining a MOSFET and a BJT, and both carriers participate in conduction, has the advantages of low on-voltage, low driving power consumption, high working frequency and the like, is widely applied to the fields of communication technology, new energy equipment and various consumer electronics, and is a core device of an electronic power system.
As demand has grown in recent years, power electronics with higher forward blocking capability, smaller cell size, and lower power consumption have been in need of innovation. The existing IGBT adopts Si or SiC material as the P-type substrate, and the current P-GaN process is limited, so that the research on the GaN IGBT device taking N-GaN as the substrate has great application value for developing a low-power-consumption and high-speed GaN power switch device, and is an ideal device in the field of high-speed and low-power consumption in the future.
Disclosure of Invention
Accordingly, the present invention is directed to an N-substrate trench GaN insulated gate bipolar transistor with controlled hole injection efficiency, which reduces charge storage in the drift region by controlling hole injection efficiency in the collector region to achieve low turn-off loss and faster switching speed, and the P-GaN doping concentration cannot be too high due to process limitations.
In order to achieve the above purpose, the present invention provides the following technical solutions:
an N-substrate trench type GaN insulated gate bipolar transistor (CEH GaN IGBT) for controlling hole injection efficiency is based on an N-type GaN substrate material, and a collector region of the novel device is of a P+/P-multi-region alternating structure with different acceptor impurity doping concentrations. Specifically, in the CEH GaN IGBT, one part of the N substrate groove type GaN IGBT collector region is heavily doped and the other part is lightly doped. The high doped P+ region is a collector injection region, and is used as an unbalanced hole injection mechanism when the device is turned on in the forward direction, the low doped P-region is a low electron barrier region and is used as an unbalanced electron extraction mechanism of the drift region, so that the current tailing phenomenon when the device is turned off can be effectively improved, the turn-off time is lower, and the turn-off loss of the device in the switching process is reduced.
The transistor is of a bilateral symmetry structure, and the left half structure comprises a P+ collector region 1, a P-collector region 2, an N-buffer region 3, an N-drift region 4, a P-body region 5, an N+ emitter substrate 6 and an insulating medium layer Al 2 O 3 7. A gate metal Al contact region 8, a collector metal Ni contact region 9, an emitter metal Ni/Ti contact region 10 and an emitter metal Ti/Al/Ni/Au contact region 11;
the P+ collector region 1 is positioned between the collector metal Ni contact region 9 and the N-buffer region 3, and the right side of the P+ collector region is in contact with the P-collector region;
the P-collector region 2 is positioned between the collector metal Ni contact region 9 and the N-buffer region 3, and the left side of the P-collector region is in contact with the P+ collector region 1;
the N-buffer area 3 is positioned on the upper surface of the N-drift area 4, and the upper surface of the N-buffer area is respectively contacted with the P+ collector area 1 and the P-collector area 2;
the N-drift region 4 is positioned between the N-buffer region 3 and the P-body region 5, and the right part of the N-drift region is connected with the insulating medium layer Al 2 O 3 7, contact;
the P-body region 5 is positioned on the lower surface of the N-drift region 4, and the right side of the P-body region is connected with the insulating medium layer Al 2 O 3 7, contact;
the N+ emitter substrate 6 is positioned on the lower surface of the P-body region 5 and is provided with an insulating medium layer Al 2 O 3 7 lower surface of which is contacted with the emitter metal Ti/Al/Ti/AuThe upper surface of zone 11 is in contact;
the insulating medium layer Al 2 O 3 The left side of the electrode 7 is contacted with the right lower surface of the N-drift region 4, the right surface of the P-body region 5 and the upper surface of the N+ emitter substrate 6;
the gate metal Al contact area 8 is positioned on the insulating medium layer Al 2 O 3 7 upper surface;
the collector metal Ni contact region 9 is positioned on the upper surfaces of the P+ collector region 1 and the P-collector region 2;
the emitter metal Ni/Ti contact region 10 is inlaid in the N+ emitter substrate 6, the upper surface of the emitter metal Ni/Ti contact region is in contact with the P-body region 5, and the lower surface of the emitter metal Ni/Ti contact region is in contact with the emitter metal Ti/Al/Ni/Au contact region 11.
Preferably, the p+ collector region 1, the P-collector region 2 and the P-body region 5 are doped with P-type impurities, and the doping concentration may be changed as required.
Preferably, the N-buffer region 3, the N-drift region 4 and the n+ emitter substrate 6 are doped with N-type impurities, and the doping concentration may be changed as required.
Preferably, the thickness h1 of the p+ collector region 1 is equal to the thickness h1 of the P-collector region 2.
Preferably, the sum of the width w5 of the p+ collector region 1 and the width w4 of the P-collector region 2 is equal to the width w1 of the N-buffer region 3.
The invention has the beneficial effects that: the invention provides a novel structure for promoting the application of a GaN semiconductor material in the field of IGBT devices, and because of the technological limit of the existing P-type GaN, the invention designs a novel structure of a trench gate IGBT with an N-type GaN substrate and a P/N/P/N structure, thereby more fully playing the advantages of a wide forbidden band semiconductor GaN material. Meanwhile, in the new structure, a part of the collector region is heavily doped, a part of the collector region is lightly doped, charge injection is reduced when the device is turned on, and storage of the charge in the drift region is reduced, so that the collector region has lower turn-off speed and turn-off power consumption as a switching device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the specification.
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of an N-substrate trench GaN insulated gate bipolar transistor (CEH GaN IGBT) with control of hole injection efficiency according to embodiment 1;
FIG. 2 is a schematic illustration of the dimensions of the CEH GaN IGBT of FIG. 1;
fig. 3 is a schematic structural diagram of a GaN IGBT tube of the same size as in example 1 provided in example 2;
fig. 4 is a schematic view of the dimensions of a GaN IGBT tube of the same dimensions as those of example 1 provided in example 2;
fig. 5 shows 100A/cm for the CEH GaN IGBT of example 1 and the GaN IGBT of example 2 of the same size when t=300k, vge (gate voltage) =8v 2 Schematic diagram of conduction voltage drop under current density;
FIG. 6 shows the gate voltage V in the forward conduction mode g Output characteristics curves of the CEH GaN IGBT of embodiment 1 when the output characteristics are respectively 1V,2V,3V,4V,5V,6V,7V,8V,9V and 10V;
FIG. 7 shows the gate voltage V in the forward conduction mode g Output characteristic curves of the GaN IGBT of example 2 for 1v,2v,3v,4v,5v,6v,7v,8v,9v,10v, respectively;
fig. 8 is a schematic diagram of forward withstand voltage curves of the CEH GaN IGBT of example 1 and the GaN IGBT of example 2 of the same size;
FIG. 9 is a resistive load test circuit diagram for testing the turn-off characteristics of a device;
fig. 10 is a turn-off graph of the CEH GaN IGBT of example 1 and the GaN IGBT of example 2 of the same size when t=300K;
reference numerals: 1-P+ collector region, 2-P-collector region, 3-N-buffer region, 4-N-drift region, 5-P-body region, 6-N+ emitter substrate, 7-insulating dielectric layer Al 2 O 3 8-gate metal Al contact region, 9-collector metal Ni contactA region, a 10-emitter metal Ni/Ti contact region, a 11-emitter metal Ti/Al/Ni/Au contact region.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to limit the invention; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc., that indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but not for indicating or suggesting that the referred device or element must have a specific azimuth, be constructed and operated in a specific azimuth, so that the terms describing the positional relationship in the drawings are merely for exemplary illustration and should not be construed as limiting the present invention, and that the specific meaning of the above terms may be understood by those of ordinary skill in the art according to the specific circumstances.
Example 1:
as shown in fig. 1 to 2, this embodiment provides an N-substrate trench type GaN insulated gate for controlling hole injection efficiencyThe structure of the bipolar transistor (CEH GaN IGBT) is bilaterally symmetrical, and the left half structure comprises a P+ collector region 1, a P-collector region 2, an N-buffer region 3, an N-drift region 4, a P-body region 5, an N+ emitter substrate 6 and an insulating medium layer Al 2 O 3 7. A gate metal Al contact region 8, a collector metal Ni contact region 9, an emitter metal Ni/Ti contact region 10, and an emitter metal Ti/Al/Ni/Au contact region 11.
The P+ collector region 1 is positioned between the collector metal Ni contact region 9 and the N-buffer region 3, the right side of the P+ collector region is in contact with the P-collector region, the width w5 of the P+ collector region 1 is 6um, the thickness h1 is 0.5um, the doping type is uniform doping, and the doped P-type impurity concentration is 1 multiplied by 10 18 cm -3 。
The P-collector region 2 is positioned between the collector metal Ni contact region 9 and the N-buffer region 3, the left side of the P-collector region is in contact with the P+ collector region 1, the width w4 of the P-collector region 2 is 2um, the thickness h1 is 0.5um, the doping type is uniform doping, and the doped P-type impurity concentration is 1 multiplied by 10 16 cm -3 。
The N-buffer region 3 is positioned on the upper surface of the N-drift region 4, the upper surface of the N-buffer region is respectively contacted with the P+ collector region 1 and the P-collector region 2, the width w1 of the N-buffer region 3 is 8um, the thickness h2 is 0.5um, the doping type is uniform doping, and the doped N-type impurity concentration is 1 multiplied by 10 17 cm -3 。
The N-drift region 4 is located between the N-buffer region 3 and the P-body region 5, and its right part is connected with the insulating medium layer Al 2 O 3 7 contacts, thickness h3 is 7.5um, doping type is uniform doping, doping N type impurity concentration is 5×10 15 cm -3 。
The P-body region 5 is positioned on the lower surface of the N-drift region 4, and the right side of the P-body region is connected with the insulating medium layer Al 2 O 3 7 contacts, thickness h4 is 1um, doping type is uniform doping, doping N type impurity concentration is 1×10 17 cm -3 。
An N+ emitter substrate 6 is positioned on the lower surface of the P-body region 5 and an insulating medium layer Al 2 O 3 7, the lower surface is contacted with the upper surface of an emitter metal Ti/Al/Ti/Au contact region 11, the thickness h5 is 2um, the doping type is uniformly doped, and the doped N-type impurity concentration is 2 multiplied by 10 18 cm -3 。
Insulating dielectric layer Al 2 O 3 The left side of the electrode 7 is contacted with the right lower surface of the N-drift region 4, the right surface of the P-body region 5 and the upper surface of the N+ emitter substrate 6;
the gate metal Al contact region 8 is positioned on the insulating medium layer Al 2 O 3 7 upper surface;
collector metal Ni contact region 9 is positioned on the upper surfaces of P+ collector region 1 and P-collector region 2;
the emitter metal Ni/Ti contact region 10 is inlaid in the N+ emitter substrate 6, the upper surface of the emitter metal Ni/Ti contact region is in contact with the P-body region 5, and the lower surface of the emitter metal Ni/Ti contact region is in contact with the emitter metal Ti/Al/Ni/Au contact region 11.
In the implementation process, the N-substrate trench type GaN insulated gate bipolar transistor (CEH GaN IGBT) structure for controlling hole injection efficiency provided in embodiment 1 of the present invention is only an optimal size selection regarding the setting of the width and thickness, and as long as the positional relationship between the structures of each part in the transistor is maintained, the sizes of the structures of each part can be correspondingly modified according to actual requirements, and the same effect can be achieved.
Example 2:
as shown in fig. 3 to 4, this embodiment provides a GaN IGBT of the same size as that of embodiment 1, except that p+ collector region 1 of this embodiment entirely covers p+ collector region 1 and P-collector region 2 of embodiment 1. Specifically, the device structure of this embodiment is bilaterally symmetrical, and the left half structure includes a p+ collector region 1, an N-buffer region 3, an N-drift region 4, a P-body region 5, an n+ emitter substrate 6, and an insulating dielectric layer Al 2 O 3 7. A gate metal Al contact region 8, a collector metal Ni contact region 9, an emitter metal Ni/Ti contact region 10, and an emitter metal Ti/Al/Ni/Au contact region 11.
The P+ collector region 1 is positioned between the collector metal Ni contact region 9 and the N-buffer region 3, the width w1 of the P+ collector region 1 is 8um, the thickness h1 is 0.5um, the doping type is uniform doping, and the doped P-type impurity concentration is 1 multiplied by 10 18 cm -3 。
The N-buffer region 3 is positioned on the upper surface of the N-drift region 4, the upper surfaces of the N-buffer region 3 are respectively contacted with the P+ collector region 1, the width w1 of the N-buffer region 3 is 8um, the thickness h2 is 0.5um, the doping type is uniform doping,doped N-type impurity concentration of 1×10 17 cm -3 。
The N-drift region 4 is located between the N-buffer region 3 and the P-body region 5, and is connected with the insulating medium layer Al on the right side 2 O 3 7 contacts, thickness h3 is 7.5um, doping type is uniform doping, doping N type impurity concentration is 5×10 15 cm -3 。
The P-body region 5 is positioned on the lower surface of the N-drift region 4, and the right side of the P-body region is connected with the insulating medium layer Al 2 O 3 7 contacts, thickness h4 is 1um, doping type is uniform doping, doping N type impurity concentration is 1×10 17 cm -3 。
An N+ emitter substrate 6 is positioned on the lower surface of the P-body region 5 and an insulating medium layer Al 2 O 3 7, the lower surface is contacted with the upper surface of an emitter metal Ti/Al/Ti/Au contact region 11, the thickness h5 is 2um, the doping type is uniformly doped, and the doped N-type impurity concentration is 2 multiplied by 10 18 cm -3 。
Insulating dielectric layer Al 2 O 3 7 are in contact with the lower right surface of the N-drift region 4, with the right surface of the P-body region 5, and with the upper surface of the N + emitter substrate 6.
The gate metal Al contact region 8 is positioned on the insulating medium layer Al 2 O 3 7 upper surface.
Collector metal Ni contact 9 is located on the upper surface of p+ collector 1.
The emitter metal Ni/Ti contact region 10 is inlaid in the N+ emitter substrate 6, the upper surface of the emitter metal Ni/Ti contact region is in contact with the P-body region 5, and the lower surface of the emitter metal Ni/Ti contact region is in contact with the emitter metal Ti/Al/Ni/Au contact region 11.
Fig. 5 shows 100A/cm of the CEH GaN IGBT (example 1) and the GaN IGBT (example 2) of example 1 and the GaN IGBT of example 2 of the same size when t=300k, vge (gate voltage) =8v 2 As can be seen from fig. 5, the on-voltage drop of the CEH GaN IGBT is 3.36V, and the on-voltage drop of the GaN IGBT is 3.31V, which is mainly due to the fact that the presence of the P-collector region reduces the average doping concentration of the collector region, and further causes the hole injection of the CEH GaN IGBT collector region to be reduced, so that the hole concentration in the N-drift region is reduced, and the conductivity modulation effect of the N-drift region is reduced.
FIG. 6 shows the gate voltage V in the forward conduction mode g The output characteristics of the CEH GaN IGBT of example 1 for 1V,2V,3V,4V,5V,6V,7V,8V,9V,10V, respectively, show that the CEH GaN IGBT has good gate control capability.
FIG. 7 shows the gate voltage V in the forward conduction mode g The output characteristics of example 2 for 1v,2v,3v,4v,5v,6v,7v,8v,9v,10v, respectively, show that example 2 has a higher output saturation current due to higher hole injection rate in the collector region.
Fig. 8 is a schematic diagram of forward voltage withstanding curves of the CEH GaN IGBT of embodiment 1 and the GaN IGBT of embodiment 2 of the same size, and in the forward blocking mode, the structural parameters of the two devices are completely identical, and breakdown voltages of the CEH GaN IGBT and the GaN IGBT are not greatly different, namely 1421V and 1440V, respectively.
FIG. 9 is a resistive load test circuit diagram for testing the turn-off characteristics of a device, wherein the bus voltage V 2 Set to 800V, V 1 For a voltage input signal varying from 15V/-5V, the gate resistance R G =5Ω, the reverse freewheeling diode FWD is set by simulation as an ideal diode, the load resistor R L ＝80Ω。
Fig. 10 is a graph of turn-off of the CEH GaN IGBT of example 1 and the GaN IGBT of example 2 when t=300K, showing waveforms of collector current of the devices as the transient simulation time changes, and it can be seen that when both IGBT devices are turned off, there is a tailing current phenomenon, but the GaN IGBT is more obvious, indicating that the turn-off time is longer. The CEH GaN IGBT is characterized in that a lightly doped P-region is introduced into a collector region, hole injection of the collector region is reduced, and in forward conduction, a conductivity modulation effect exists, so that the device stores fewer carriers in a drift region, and in turn-off, the number of carriers required to be extracted is reduced, so that the turn-off speed is higher. The turn-off time of the CEH GaN IGBT is 41.3ns, and the turn-off loss is 0.593mJ/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the The turn-off time of the GaN IGBT is 71.5ns, and the turn-off loss is 0.829mJ/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the Compared with the GaN IGBT of the embodiment 2, the turn-off time of the CEH GaN IGBT designed in the embodiment 1 of the invention is reduced by 42.2%, and the turn-off loss is reduced by 28.5%.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.
Claims (5)
1. An N-substrate groove type GaN insulated gate bipolar transistor for controlling hole injection efficiency is characterized in that the transistor is of a bilateral symmetry structure, and the left half structure comprises a P+ collector region (1), a P-collector region (2), an N-buffer region (3), an N-drift region (4), a P-body region (5), an N+ emitter substrate (6) and an insulating medium layer Al 2 O 3 (7) A gate metal Al contact region (8), a collector metal Ni contact region (9), an emitter metal Ni/Ti contact region (10) and an emitter metal Ti/Al/Ni/Au contact region (11);
the P+ collector region (1) is positioned between the collector metal Ni contact region (9) and the N-buffer region (3), and the right side of the P+ collector region is in contact with the P-collector region;
the P-collector region (2) is positioned between the collector metal Ni contact region (9) and the N-buffer region (3), and the left side of the P-collector region is in contact with the P+ collector region (1);
the N-buffer area (3) is positioned on the upper surface of the N-drift area (4), and the upper surface of the N-buffer area is respectively contacted with the P+ collector area (1) and the P-collector area (2);
the N-drift region (4) is positioned between the N-buffer region (3) and the P-body region (5), the right part of the N-drift region is connected with the insulating medium layer Al 2 O 3 (7) Contacting;
the P-body region (5) is positioned on the lower surface of the N-drift region (4), and the right side of the P-body region is connected with the insulating medium layer Al 2 O 3 (7) Contacting;
the N+ emitter substrate (6) is positioned on the lower surface of the P-body region (5) and the insulating medium layer Al 2 O 3 (7) The lower surface of the lower surface is contacted with the upper surface of an emitter metal Ti/Al/Ti/Au contact area (11);
the insulating medium layer Al 2 O 3 (7) The left side is contacted with the right lower surface of the N-drift region (4)Is contacted with the right surface of the P-body region (5) and is contacted with the upper surface of the N+ emitter substrate (6);
the grid metal Al contact area (8) is positioned on the insulating medium layer Al 2 O 3 (7) An upper surface;
the collector metal Ni contact region (9) is positioned on the upper surfaces of the P+ collector region (1) and the P-collector region (2);
the emitter metal Ni/Ti contact region (10) is inlaid in the N+ emitter substrate (6), the upper surface of the emitter metal Ni/Ti contact region is in contact with the P-body region (5), and the lower surface of the emitter metal Ni/Ti contact region is in contact with the emitter metal Ti/Al/Ni/Au contact region (11).
2. The N-substrate trench GaN insulated gate bipolar transistor controlling hole injection efficiency according to claim 1, wherein the p+ collector region (1), P-collector region (2) and P-body region (5) are doped with P-type impurities.
3. The N-substrate trench GaN insulated gate bipolar transistor for controlling hole injection efficiency according to claim 1, wherein said N-buffer region (3), N-drift region (4) and n+ emitter substrate (6) are doped with N-type impurities.
4. The N-substrate trench GaN insulated gate bipolar transistor controlling hole injection efficiency according to claim 1 or 2, characterized in that the thickness h1 of the p+ collector region (1) and the P-collector region (2) is equal.
5. The N-substrate trench GaN insulated gate bipolar transistor controlling hole injection efficiency according to claim 1 or 2, wherein the sum of the width w5 of the p+ collector region (1) and the width w4 of the P-collector region (2) is equal to the width w1 of the N-buffer region (3).
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100301335A1 (en) * | 2009-06-02 | 2010-12-02 | Sei-Hyung Ryu | High Voltage Insulated Gate Bipolar Transistors with Minority Carrier Diverter |
| CN107768433A (en) * | 2017-09-22 | 2018-03-06 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
| CN113540224A (en) * | 2021-07-19 | 2021-10-22 | 重庆邮电大学 | N-substrate groove type GaN insulated gate bipolar transistor |
| CN113611738A (en) * | 2021-08-10 | 2021-11-05 | 重庆邮电大学 | Groove type GaN insulated gate bipolar transistor with heterojunction injection |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100301335A1 (en) * | 2009-06-02 | 2010-12-02 | Sei-Hyung Ryu | High Voltage Insulated Gate Bipolar Transistors with Minority Carrier Diverter |
| CN107768433A (en) * | 2017-09-22 | 2018-03-06 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
| CN113540224A (en) * | 2021-07-19 | 2021-10-22 | 重庆邮电大学 | N-substrate groove type GaN insulated gate bipolar transistor |
| CN113611738A (en) * | 2021-08-10 | 2021-11-05 | 重庆邮电大学 | Groove type GaN insulated gate bipolar transistor with heterojunction injection |
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