CN117320540A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure and a method of manufacturing the same are provided. An exemplary method includes depositing a first conductive material layer on a substrate, patterning the first conductive material to form a first conductor plate over the substrate, forming a first high-K dielectric layer on the first conductor plate, forming a second high-K dielectric layer on the first high-K dielectric layer, forming a third high-K dielectric layer on the second high-K dielectric layer, and forming a second conductor plate over the third high-K dielectric layer and vertically overlapping the first conductor plate, wherein a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and different from a composition of the second high-K dielectric layer.

Description

Semiconductor structures and manufacturing methods

Technical field

Embodiments of the present application relate to semiconductor structures and methods of fabricating the same.

Background technique

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced successive generations of integrated circuits, each smaller and more complex than the last. However, these advances have increased the complexity of handling and manufacturing ICs, and to achieve these advances, similar developments in IC handling and manufacturing are required. As ICs evolve, functional density (i.e., the number of interconnected devices per chip area) typically increases while geometric size (i.e., the smallest component that can be created using a manufacturing process) decreases.

As IC device geometries decrease, there is a need to move large surface area passive components into back-end-of-line (BEOL) structures. Metal-insulator-metal (MIM) capacitors are one example of such passive devices. A typical MIM capacitor consists of multiple conductor plates that are insulated from each other by multiple insulator layers. Although existing MIM capacitors and their manufacturing processes are generally adequate for their intended purposes, they are not entirely satisfactory in every respect.

Contents of the invention

According to one aspect of an embodiment of the present application, a method of manufacturing a semiconductor structure is provided, including: depositing a first conductive material layer over a substrate; patterning the first conductive material layer to form a first conductor plate over the substrate ; forming a first high-K dielectric layer over the first conductor plate; forming a second high-K dielectric layer on the first high-K dielectric layer; forming a third high-K dielectric layer on the second high-K dielectric layer layer; and forming a second conductor plate above and vertically overlapping the first conductor plate, wherein the composition of the first high-K dielectric layer is the same as the composition of the third high-K dielectric layer, And the composition is different from the second high-K dielectric layer.

According to another aspect of an embodiment of the present application, a method of manufacturing a semiconductor structure is provided, including: forming a first conductor plate on a first insulating layer over a substrate; forming a top surface along the first conductor plate and a second insulating layer extending from the sidewall surface; a multi-layer dielectric structure is conformally formed above the first conductor plate, wherein the multi-layer dielectric structure is in direct contact with both the first insulating layer and the second insulating layer, and wherein multiple A layer dielectric structure is formed from a high-K dielectric layer; and a second conductor plate is formed over the multi-layer dielectric structure and vertically overlapping the first conductor plate.

According to yet another aspect of embodiments of the present application, a semiconductor structure is provided that includes a metal-insulator-metal (MIM) capacitor on a first insulating layer over a substrate. The MIM capacitor includes: a first conductor plate located on a first insulating layer, and a second insulating layer extending along and on the side walls and top surface of the first conductor plate. a conformal dielectric structure over the substrate and a first conductor plate, wherein the conformal dielectric structure is formed from a plurality of high-K dielectric layers, and a second conductor plate over the conformal dielectric structure and connected to the first conductor plate The plates overlap vertically, with the conformal dielectric structure in direct contact with both the second insulating layer and the first insulating layer.

Description of drawings

Aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are for illustration purposes only. Indeed, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

1 is a flow diagram of a method of fabricating a semiconductor structure in accordance with various aspects of the present disclosure.

Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16 are various diagrams according to the present disclosure. Partial cross-sectional view of a workpiece during various manufacturing stages of the method of FIG. 1 .

17 and 18 are partial cross-sectional views of alternative workpieces during various manufacturing stages of the method of FIG. 1 in accordance with various aspects of the present disclosure.

19 is a flow diagram of a method for fabricating another semiconductor structure in accordance with various aspects of the present disclosure.

20, 21, and 22 are partial cross-sectional views of a workpiece during various manufacturing stages of the method of FIG. 19 in accordance with various aspects of the present disclosure.

23 and 24 are partial cross-sectional views of alternative workpieces during various manufacturing stages of the method of FIG. 19 in accordance with various aspects of the present disclosure.

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are examples only and not intended to be limiting. For example, in the following description, forming the first component over or on the second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which the first component and the second component may be formed in direct contact. Additional components so that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not by itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, for convenience of description, spaced relational terms such as “below”, “below”, “lower”, “above”, “upper”, etc. may be used herein to describe what is shown in the figures. The relationship of one element or component to another element or component. The spacing relation terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein interpreted accordingly.

Furthermore, when "about," "approximately," etc. are used to describe a number or range of numbers, the term is intended to encompass numbers that are within a reasonable range taking into account the variations inherent in the manufacturing process as understood by those of ordinary skill in the art. . For example, the number or range of a number encompasses a reasonable range of the number described, including, for example, within +/- 10% of the number described, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number. For example, a layer of material having a thickness of "about 5 nm" may comprise a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer is +/- 15% known to one of ordinary skill in the art. Furthermore, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself limit the relationship between the various embodiments and/or configurations discussed.

Metal-Insulator-Metal (MIM, Metal-Insulator-Metal) capacitors have been widely used in functional circuits, such as mixed-signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM) and logic operation circuits. In system-on-chip (SOC) applications, different capacitors for different functional circuits must be integrated on the same chip to achieve different purposes. For example, in mixed-signal circuits, capacitors are used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillators and phase-shifting networks for coupling and/or bypass purposes. For microprocessors, capacitors are used for decoupling. As the name suggests, MIM capacitors consist of a sandwich structure of interleaved metal and insulator layers. An example MIM capacitor includes a plurality of conductor plates, each conductor plate being insulated from adjacent conductor plates by a layer of insulator. Today, MIM capacitors are also implemented in high-performance computing (HPC). Those MIM capacitors implemented in HPC may require high capacitance. Although existing MIM capacitors may be satisfactory in providing high capacitance, their performance suffers from time-dependent dielectric breakdown (TDDB) failure due to the insulator layer disposed between two adjacent conductor plates. Lifespan may be short.

The present disclosure provides metal-insulator-metal (MIM) capacitors with improved TDDB performance and methods of forming the same. MIM capacitors include a multilayer insulator structure disposed between two adjacent conductor plates. In an exemplary embodiment, a method of forming a MIM capacitor includes depositing a first conductive layer on a substrate, performing an etching process to pattern the first conductive layer to form a first conductor plate, performing a nitriding process on the first conductor plate, A first hafnium-zirconium oxide (HZO) layer is formed on the first conductor plate, a titanium oxide layer or an aluminum oxide layer is formed on the first hafnium-zirconium oxide (HZO) layer, and then a titanium oxide layer or aluminum oxide layer is formed on the first conductor plate. A second hafnium zirconium oxide layer is formed on the second layer. By interposing a titanium oxide or aluminum oxide layer between the first and second hafnium zirconium oxide layers, defects in the first and second hafnium zirconium oxide layers may be less easily linked. In this way, conductive paths along the grain boundaries of the first and second hafnium zirconium oxide layers may be reduced or eliminated. Therefore, the TDDB performance of the MIM capacitor is advantageously improved.

Various aspects of the present disclosure will now be described in greater detail with reference to the accompanying drawings. In this regard, FIG. 1 is a flowchart illustrating a method 100 for fabricating a semiconductor structure in accordance with an embodiment of the present disclosure. Method 100 is described below in conjunction with FIGS. 2-18 , which are partial cross-sectional views of workpiece 200 at various stages of manufacturing according to embodiments of method 100 . 19 is a flowchart illustrating a method 300 for fabricating a semiconductor structure in accordance with an embodiment of the present disclosure. The method 300 is described below in conjunction with Figures 1-18 and 20-24, which are partial cross-sectional views of the workpiece 200' at different manufacturing stages according to embodiments of the method 300. Since the workpiece 200/200' will be fabricated into a semiconductor structure at the end of the manufacturing process, the workpiece may also be referred to as a semiconductor structure 200/200' depending on context. Methods 100 and 300 are examples only and are not intended to limit the disclosure to what is expressly shown therein. Additional steps may be provided before, during, and after method 100/300, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For reasons of simplicity, not all steps are described in detail here. Furthermore, throughout this application, like reference numerals refer to like parts unless otherwise specified.

Referring to FIGS. 1 and 2 , method 100 includes block 102 of providing workpiece 200 . Workpiece 200 includes substrate 202, which may be made of silicon or other semiconductor material such as germanium. Substrate 202 may also include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 202 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, substrate 202 may include an epitaxial layer, such as an epitaxial layer covering the bulk semiconductor. Various microelectronic components may be formed in or on substrate 202, such as transistor components including source/drain components, gate structures, gate spacers, source/drain contacts, gate pole contacts, isolation structures including shallow trench isolation (STI), or any other suitable component. Depending on the context, the source/drain components may individually or collectively refer to source or drain. Transistors formed on substrate 202 may be planar devices or multi-gate devices. Multi-gate devices include, for example, fin field effect transistors (FinFETs) or multi-bridge channel (MBC) transistors. FinFETs have a raised channel that is wrapped on multiple sides by a gate (for example, the gate wraps the top and sidewalls of a "fin" of semiconductor material that extends from the substrate). MBC transistors have a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. Since its gate structure surrounds the channel region, the MBC transistor may also be called a gate-all-around transistor (SGT) or a gate-all-around (GAA) transistor.

Workpiece 200 also includes a multi-layer interconnect (MLI) structure 210 that provides interconnections (eg, wiring) between the various microelectronic components of workpiece 200 . MLI structure 210 may also be referred to as interconnect structure 210 . MLI structure 210 may include multiple metal layers or metallization layers. In some cases, MLI structure 210 may include eight (8) to fourteen (14) metal layers. Each metal layer includes a plurality of conductive features embedded in an inter-metal dielectric (IMD) layer. Conductive components may include contacts, vias, or metal lines. The IMD layer may be silicon oxide or a silicon oxide-containing material, where silicon is present in various suitable forms. For example, the IMD layer includes silicon oxide or a low-k dielectric material with a k value (dielectric constant) less than that of silicon oxide (approximately 3.9). In some embodiments, the low-k dielectric material includes tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide such as borophosphosilicate glass (BPSG), fused Silica glass (FSG), phosphosilicate glass, silicon oxycarbonitride (SiOCN), spin-on silicon-based polymer dielectric), combinations thereof, or other suitable materials.

In one embodiment, a carbide layer 220 is deposited on the MLI structure 210 . Deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof. Any suitable type of carbide material may be used in carbide layer 220, such as silicon carbide (SiC).

In an embodiment, oxide layer 230 is deposited on carbide layer 220 . Any suitable deposition process for oxide layer 230 may be used, including CVD, flowable CVD (FCVD), spin coating, PVD, ALD, or combinations thereof. In one embodiment, oxide layer 230 includes undoped silicon oxide.

Workpiece 200 also includes a first etch stop layer (ESL) 240 deposited on oxide layer 230 . The first ESL 240 may include silicon nitride carbon (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), or silicon nitride (SiN), or a combination thereof, and may be chemically Formed by vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or a combination thereof.

Workpiece 200 also includes dielectric layer 250 deposited on first ESL 240 . The composition of dielectric layer 250 may be similar to the composition of oxide layer 230 . In some embodiments, dielectric layer 250 includes undoped quartz glass (USG) or silicon oxide. Dielectric layer 250 may be deposited using CVD, flowable CVD (FCVD), spin coating, PVD, ALD, or a combination thereof.

Workpiece 200 also includes a plurality of lower contact features (eg, lower contact features 253 , 254 , and 255 ) formed in dielectric layer 250 . Formation of the lower contact features may include patterning of dielectric layer 250 to form trenches, and depositing barrier layers (not separately labeled) and metal fill layers (not separately labeled) in the trenches. In some embodiments, the barrier layer may include titanium nitride or tantalum nitride and may be conformally deposited using PVD, CVD, metal-organic CVD (MOCVD), or a suitable method. In one embodiment, the barrier layer may include tantalum nitride. The metal fill layer may include copper (Cu) and may be deposited using electroplating or electroless plating. After depositing the barrier and metal fill layers, a planarization process, such as a chemical mechanical planarization (CMP) process, may be performed to remove excess barrier and metal fill layers to form lower contact features 253, 254, and 255. Although lower contact members 253, 254, and 255 are disposed below upper contact members (eg, upper contact members 292, 294), lower contact members 253, 254, and 255 are sometimes referred to as top metal (TM) contacts.

Workpiece 200 also includes a second etch stop layer 256 formed directly on dielectric layer 250 . In embodiments, the second etch stop layer 256 is deposited on the dielectric layer 250 by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. The second etch stop layer 256 may include silicon carbonitride (SiCN), silicon nitride (SiN), other suitable materials, or combinations thereof. In this embodiment, the second etch stop layer 256 is in direct contact with the top surfaces of the lower contact features 253, 254, and 255.

Workpiece 200 also includes an oxide layer 258 formed directly on second etch stop layer 256 . In embodiments, oxide layer 258 may include undoped quartz glass (USG), silicon oxide, or other suitable materials.

Referring to FIGS. 1 and 3 , method 100 includes block 104 in which first conductive layer 262 is formed directly on oxide layer 258 . First conductive layer 262 may be deposited on oxide layer 258 using PVD, CVD, or MOCVD, and may cover the entire top surface of workpiece 200 . In some embodiments, the first conductive layer 262 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), cobalt (Co), nickel (Ni ), tungsten (W), aluminum (Al) or other suitable materials. In one embodiment, first conductive layer 262 includes titanium nitride (TiN).

Referring to FIGS. 1 and 4 , method 100 includes block 106 in which first conductive layer 262 is patterned to form first conductor plate 262 ′ directly on lower contact feature 254 . Patterning may include depositing a hard mask layer on the first conductive layer 262, forming a photoresist layer on the hard mask, patterning the photoresist layer using photolithography, and using the patterned photoresist layer as an etch mask. The patterned hard mask is then used as an etch mask to etch the first conductive layer 262 . The hard mask layer and photoresist layer can be selectively removed. In this embodiment, the oxide layer 263 is formed by etching the first conductive layer 262 and/or removing the hard mask layer and the photoresist layer. That is, the top surface and the sidewall surface of the first conductor plate exposed to the etchant are oxidized, thereby forming the oxide layer 263 . As shown in Figure 4, oxide layer 263 extends along the top and sidewall surfaces of first conductor plate 262'. In embodiments where first conductive layer 262 includes titanium nitride (TiN), oxide layer 263 includes titanium oxide (TiO ₂ ).

Referring to FIGS. 1 and 5 , the method 100 includes block 108 in which a nitriding process 265 is performed on the workpiece 200 to convert the oxide layer 263 to a nitrided oxide layer 263 ′, thereby enhancing the first conductor plate 262 ' and the first insulator structure 264 (shown in FIG. 6 ) to be formed, and improves the reliability of the final structure of the workpiece 200 . In an embodiment, the nitrogen source in nitridation process 265 includes a nitrogen plasma. The nitriding process 265 may be performed at a flow rate of about 8,000 sccm to about 10,000 sccm, at a temperature between about 350°C and about 450°C, and at a plasma power of about 200W to about 300W for about 20 seconds to 60 seconds to form an impressive A satisfactory nitrided layer (eg, nitrided oxide layer 263') without damaging front-end devices (eg, transistors formed on substrate 202). After performing the nitriding process 265, the oxide layer 263 is nitrided and becomes the nitrided oxide layer 263'. In an embodiment, the oxide layer 263 includes titanium oxide (TiO ₂ ), and the nitride oxide layer 263 ′ includes titanium oxynitride (TiON). After performing the nitriding process 265, the nitrogen content in the first conductor plate 262' may also be changed. In an embodiment, the nitrogen content of the upper portion of the first conductor plate 262' is higher than the nitrogen content of the lower portion of the first conductor plate 262'. That is, the upper portion of the first conductor plate 262' includes nitrogen-rich titanium nitride (TiN), while the lower portion of the first conductor plate 262' may be nitrogen poor.

Referring to FIGS. 1 and 6 , method 100 includes block 110 in which first insulator structure 264 is formed on workpiece 200 . After patterning first conductive layer 262 to form first conductor plate 262' and after performing nitridation process 265, first insulator structure 264 is formed. The first insulator structure 264 is conformally formed to have a substantially uniform thickness on the top surface of the workpiece 200 (e.g., substantially the same thickness on the top surface and sidewall surfaces of the nitride oxide layer 263').

In this embodiment, in order to improve the time-dependent dielectric breakdown (TDDB) performance and thereby improve the reliability of the semiconductor device (eg, metal-insulator-metal capacitor), the first insulator structure 264 is a multi-layer structure and includes a direct A conformal first high-K dielectric layer 264a formed on the oxide layer 258 and the nitrided oxide layer 263', a conformal second high-K dielectric layer 264a formed directly on the first high-K dielectric layer 264a layer 264b, and a conformal third high-K dielectric layer 264c formed directly on the second high-K dielectric layer 264b. In an embodiment, the first high-K dielectric layer 264a, the second high-K dielectric layer 264b and the Third high-K dielectric layer 264c. The temperature of thermal ALD can be lower than the temperature of nitriding process 265. The conformal first high-K dielectric layer 264a is in direct contact with the nitrided oxide layer 263' and the oxide layer 258 and is spaced from the first conductor plate 262' by the nitrided oxide layer 263'.

The first insulator structure 264 has an overall thickness T, and in embodiments, the composition of the first high-K dielectric layer 264a is the same as the composition of the third high-K dielectric layer 264c. Compared to the embodiment in which the insulator structure is a single-layer structure and is formed from a first high-K dielectric layer having a thickness T, the first high-K dielectric layer 264a is formed to have a thickness T1 less than the thickness T and to have a thickness less than the thickness T. The thickness T3 of the third high-K dielectric layer 264c will advantageously reduce or prevent the crystallization of the first high-K dielectric layer 264a and the third high-K dielectric layer 264c, thereby reducing the Conductive paths are formed in the layer and improve TDDB performance. In an embodiment, the first high-K dielectric layer 264a and the third high-K dielectric layer 264c include hafnium zirconium oxide (HZO). In order to provide satisfactory forward bias related TDDB and satisfactory reverse bias related TDDB, the ratio of thickness T1 to thickness T3 may be between about 0.9 and about 1.1. In an embodiment, thickness T1 is substantially equal to thickness T3. In some embodiments, each of thickness T1 and thickness T3 is greater than and less than/>

The first insulator structure 264 also includes a second high-K dielectric layer 264b sandwiched between the first high-K dielectric layer 264a and the third high-K dielectric layer 264c. In an embodiment, the dielectric constant of the second high-K dielectric layer 264b is less than the dielectric constant of the first high-K dielectric layer 264a and the third high-K dielectric layer 264c. By forming the second high-K dielectric layer 264b between the first high-K dielectric layer 264a and the third high-K dielectric layer 264c, defects in the first high-K dielectric layer 264a and the third low-K dielectric layer Defects in 264 may connect less easily to form conductive paths along the grain boundaries of the first high-K dielectric layer and the third high-K dielectric layer, thus improving TDDB performance. The second high-K dielectric layer 264b has a lattice constant that is different from the lattice constants of the first high-K dielectric layer 264a and the third high-K dielectric layer 264c. In embodiments in which the first high-K dielectric layer 264a and the third high-K dielectric layer 264c include HZO, in order to significantly improve TDDB performance and save manufacturing costs, the second high-K dielectric layer 264b includes aluminum oxide (Al ₂ O ₃ ). In another embodiment, second high-K dielectric layer 264b includes titanium oxide (TiO ₂ ). The thickness T2 of the second high-K dielectric layer 264b is less than the thickness T1. In embodiments, the ratio of thickness T1 to thickness T2 may be greater than 10. The thickness T2 of the second high-K dielectric layer 264b is greater than and less than

Referring to FIGS. 1 and 7 , method 100 includes block 112 in which second conductor plate 266 is formed on first insulator structure 264 . In this embodiment, the second conductor plate 266 is formed directly on the lower contact member 253 and vertically overlaps the first conductor plate 262'. The second conductor plate 266 may be similar in composition and formation to the first conductor plate 262'. For example, a second conductive layer may be deposited on workpiece 200 and then patterned to form second conductor plate 266 . In an embodiment, second conductor plate 266 includes titanium nitride (TiN). In some embodiments, the top surface and sidewall surfaces of second conductor plate 266 may be oxidized, and workpiece 200 may therefore include titanium oxide formed on second conductor plate 266 . The oxide layer may then be nitrided through a nitriding process similar to nitriding process 265 to form a nitrided oxide layer 267 (eg, TiON). Furthermore, the nitrogen content of the upper portion of the second conductor plate 266 is higher than the nitrogen content of the lower portion of the second conductor plate 266 .

Referring to FIGS. 1 and 8 , method 100 includes block 114 in which second insulator structure 268 is formed over workpiece 200 . In embodiments, second insulator structure 268 is conformally formed to have a generally uniform thickness on the top surface of workpiece 200 (eg, have generally the same thickness on the top surface and sidewall surfaces of the nitride oxide layer). In embodiments, the second insulator structure 268 is formed and composed similarly to the first insulator structure 264 . For example, the second insulator structure 268 includes a first high-K dielectric layer 268a, a second high-K dielectric layer 268, and a third high-K dielectric layer 268c. In an embodiment, the first high-K dielectric layer 268a has the same formation, composition, and thickness as the first high-K dielectric layer 264a, and the second high-K dielectric layer 268b has the same formation, composition, and thickness as the second high-K dielectric layer 264a. The electrical layer 264b is the same, the formation, composition and thickness of the third high-K dielectric layer 268c are the same as the third high-K dielectric layer 264c, and repeated descriptions are omitted for simplicity reasons. Therefore, the TDDB performance of the second insulator structure 268 disposed between the second conductor plate 266 and the third conductor plate 270a can be improved.

Referring to Figures 1 and 9, method 100 includes block 116 in which third conductor plate 270a and dummy conductive features 270b are formed on second insulator structure 268. More specifically, the third conductor plate 270a is formed directly above the lower contact part 254 and vertically overlaps the first conductor plate 262' and the second conductor plate 266, and the dummy conductor part 270b is formed directly above the lower contact part 253 and is connected with the first conductor plate 262' and the second conductor plate 266. Two conductor plates 266 overlap vertically. The formation and composition of the third conductor plate 270a and the dummy conductive member 270b may be similar to that of the first conductor plate 262', and repeated descriptions are omitted for simplicity. In an embodiment, third conductor plate 270a and dummy conductive component 270b include titanium nitride (TiN). A nitriding process similar to nitriding process 265 may be performed. Similarly, the workpiece 200 also includes a nitrided oxide layer 270c formed on the sidewalls and top surface of the third conductor plate 270a, and a nitrided oxide layer 270d formed on the sidewalls or top surface of the dummy conductive feature 270b. In an embodiment, nitrided oxide layer 270c and nitrided oxide layer 270d include titanium oxynitride (TiON). The upper portion of the third conductor plate 270a has a higher nitrogen content than the lower portion of the third conductor plate 270a, and the upper portion of the dummy conductive member 270b has a higher nitrogen content than the lower portion of the dummy conductive member 270b. Nitrogen content.

After the third conductor plate 270a is formed, the structure of the MIM capacitor 272 is finalized. In the embodiment shown in FIG. 9 , workpiece 200 includes MIM capacitor 272 and dummy conductive feature 270 b formed directly above lower contact feature 253 . In this embodiment, the MIM capacitor 272 includes three vertically stacked conductor plates (ie, the first conductor plate 262', the second conductor plate 266, and the third conductor plate 270a), a plurality of insulator structures (ie, the first insulator structure 264 and second insulator structure 268) and a plurality of nitrided oxide layers (eg, layers 263', 267, 270c). It should be understood that the MIM capacitor 272 may include other suitable numbers of conductor plates (e.g., two, four, or more), with each two adjacent conductor plates being composed of a corresponding multi-layer insulator structure (e.g., a multi-layer insulator structure). An insulator structure 264) is isolated from the nitrided oxide layer (eg, nitrided oxide layer 263'). In an embodiment, the first and third high-K dielectric layers (eg, 264a and 264c, 268a and 268c) include HZO, and the second high-K dielectric layer (eg, 264b, 268b) includes aluminum oxide (Al ₂ O ₃ ). In another embodiment, the first and third high-K dielectric layers (eg, 264a and 264c, 268a and 268c) include HZO, and the second high-K dielectric layer (eg, 264b, 268b) includes titanium oxide (TiO ₂ ).

Referring to FIGS. 1 and 10 , method 100 includes block 118 in which first passivation structure 274 is formed on MIM capacitor 272 . As shown in FIG. 10 , MIM capacitor 272 is sandwiched between first passivation structure 274 and oxide layer 258 . In some embodiments, first passivation structure 274 may include a dielectric layer or two or more dielectric layers formed from any suitable material, such as silicon oxide or silicon nitride. In an embodiment, first passivation structure 274 includes silicon oxide formed by plasma enhanced chemical vapor deposition (PECVD). The thickness of the first passivation structure 274 may be about and/> between.

Referring to Figures 1, 11, 12, 13, and 14, method 100 includes block 120 in which conductive vias 288 and 290 are formed. First refer to Figure 11. After the first passivation structure 274 is formed, as shown in FIG. 11 , a patterned mask 278 is formed on the first passivation structure 274 . Patterned mask 278 includes two openings 278a and 278b that expose portions of first passivation structure 274 thereunder. For example, opening 278a exposes a portion of first passivation structure 274 formed directly above lower contact feature 253, and opening 278b exposes a portion of first passivation structure 274 formed directly above upper contact feature 254.

When patterned mask 278 is used as an etch mask, an etching process may be performed to form openings 280 and 282 as shown in FIG. 12 . The etching process stops at the top surface of second etch stop layer 256 . In an embodiment, the etching process etches through the first passivation structure 274, the nitride oxide layer 270d, the dummy conductive feature 270b, the second insulator structure 268, the nitride oxide layer 267, the second conductor plate 266, and the first insulator. Structure 264 to form opening 280. The etching process also etches through the first passivation structure 274, the nitride oxide layer 270c, the third conductor plate 270a, the second insulator structure 268, the first insulator structure 264, the nitride oxide layer 263', and the first conductor plate 262' to form opening 282. In embodiments, the etching process may include a dry etching process.

Referring to FIG. 13 , after the openings 280 and 282 are formed, another etching process is performed to vertically extend the openings 280 and 282 to penetrate the second etch stop layer 256 and expose the lower contact features 253 and 254 . Vertically extending openings 280 and 282 may be referred to as openings 284 and 286, respectively. In some embodiments, a dry etching process may be used to selectively etch second etch stop layer 256 to form openings 284 and 286 . After openings 284 and 286 are formed, patterned mask 278 may be selectively removed.

After openings 284 and 286 are formed, as shown in FIG. 14 , conductive vias 288 and 290 are formed in openings 284 or 286 respectively. In this embodiment, to form conductive vias 288 and 290, first conformally deposited over first passivation structure 274 and in openings 284 and 286 using a suitable deposition technique, such as ALD, PVD, or CVD. barrier layer 289a, and then a metal fill layer 289b is deposited over barrier layer 289a using ALD, PVD, CVD, electroless plating, or electroplating. Barrier layer 289a may include titanium nitride (TiN), tantalum nitride (TaN), or other metal nitrides. The metal filling layer 289b may be formed of copper (Cu), aluminum (Al), aluminum-copper (Al-Cu), or other suitable materials. A planarization process (eg, CMP) may then be performed after forming the metal fill layer 289b to finalize the shapes of the conductive vias 288 and 290.

Referring to Figures 1, 14, and 15, the method 100 includes block 122 for performing further processing. Such further processing may include, for example, forming metal lines (eg, metal lines 292, 294 shown in Figure 14) over first passivation structure 274. Metal lines 292 and 294 are electrically connected to and in direct contact with conductive vias 288 and 290, respectively. In some embodiments, metal lines 292, 294 may be referred to as upper contact features and may be part of a redistribution layer (RDL) to reroute bonding connections between upper and lower layers. This further process may also include forming a second passivation structure 296 on the workpiece 200 (shown in Figure 15). The second passivation structure 296 may be a multi-layer structure. This further process may also include forming openings extending through second passivation structure 296 to expose metal lines 292, 294, and forming pads in the openings to electrically connect to metal lines 292, 294. A bonding pad may include multiple layers, and forming multiple layers involves multiple processes. In some embodiments, after first forming openings to expose metal lines 292, 294, an under-bump metal (UBM) layer may be deposited into the openings, and then a bump layer (e.g., made of copper) may be deposited on the UBM layer ). A solder layer can then be formed on the bump layer to serve as a connection point to external circuitry.

FIG. 16 depicts a partial cross-sectional view of MIM capacitor 272. More specifically, as shown in FIG. 16 , a portion of the MIM capacitor 272 includes a first conductor plate 262 ′, a nitrided oxide layer 263 ′ extending along the sidewalls and top surface of the first conductor plate 262 ′, and a nitrided oxide layer 263 ′ extending along the sidewalls and top surface of the first conductor plate 262 ′. A first high-K dielectric layer 264a on the oxide layer 263' and in direct contact with the nitrided oxide layer 263', a second high-K dielectric layer 264b on the first high-K dielectric layer 264a, and a second high-K dielectric layer 264b on the nitrided oxide layer 263'. a third high-K dielectric layer 264c on the high-K dielectric layer 264b, and a second conductor plate 266 on the third high-K dielectric layer 264c and overlapping the first conductor plate 262'. In an embodiment, the first and third high-K dielectric layers 264a and 264c include HZO, and the second high-K dielectric layer 264b includes aluminum oxide (Al ₂ O ₃ ) or titanium oxide (TiO ₂ ).

In the above-described embodiments described with reference to FIGS. 1-16 , an aluminum oxide (Al ₂ O ₃ ) or titanium oxide (TiO ₂ )-based layer is formed between the first and third high-K dielectric layers 264 a and 264 c. With the second high-K dielectric layer 264b, the TDDB performance of the MIM capacitor 272 is improved. In an alternative embodiment, to increase the forward bias breakdown voltage, the first insulator structure may also include a fourth high-K dielectric layer 264d. For example, in the embodiment shown in Figure 17, the first insulator structure 264' includes a first high-K dielectric layer 264a' and a fourth high-K dielectric layer 264d formed on the first high-K dielectric layer 264a'. . The first high-K dielectric layer 264a' has a thickness T and is a single layer formed of a high-K dielectric material (eg, HZO) (as shown in Figure 17). In the embodiment shown in FIG. 18 , first insulator structure 264 ″ includes first insulator structure 264 and fourth high-K dielectric layer 264 d formed on third high-K dielectric layer 264 c of first insulator structure 264 . The fourth high-K dielectric layer 264d may be deposited by plasma-enhanced ALD (PEALD) at a temperature between 150°C and 250°C. Forming the fourth high-K dielectric layer 264d increases the gap between two adjacent conductor plates ( For example, the total thickness of the insulator structure between conductor plates 262' and 266) (eg, thickness increases from T to T'), thereby increasing the forward bias breakdown voltage of MIM capacitor 272. In an embodiment, no. The second high-K dielectric layer 264b includes aluminum oxide (Al ₂ O ₃ ), and the fourth high-K dielectric layer 264d includes titanium oxide (TiO ₂ ). In an embodiment, the second high-K dielectric layer 264b includes titanium oxide (TiO 2 ). TiO ₂ ), and the fourth high-K dielectric layer 264d also includes titanium oxide. Since titanium oxide has high dielectric permittivity, the introduction of the fourth high-K dielectric layer 264d advantageously increases the overall insulator structure. thickness and forward bias breakdown voltage of MIM capacitor 272 without reducing the capacitance of MIM capacitor 272. In embodiments, in order to increase the forward bias of MIM capacitor 272 without significantly reducing the capacitance of MIM capacitor 272 Breakdown voltage, the thickness T4 of the fourth high-K dielectric layer 264d may be approximately and/> between.

Although the embodiments shown in FIGS. 16-18 are directed to the insulator structure between the first conductor plate 262' and the second conductor plate 266, it should be understood that these embodiments are also applicable to the second conductor plate 266' and the second conductor plate 266'. An insulator structure between three conductor plates 270a or any other insulator structure between two adjacent conductor plates. The composition of the second insulator structure may be the same as or different from the composition of the first insulator structure. In some embodiments, second insulator structure 268 may also include a titanium oxide layer formed on third high-K dielectric layer 268c. In alternative embodiments, the first insulator structure 264 may include a titanium oxide layer 264d, the second insulator structure 268 may not contain a titanium oxide layer, and the second insulator structure 268 may have a thickness (eg, thickness T′) that is less than that of the first insulator structure 264d. Thickness (such as thickness T).

In the above-described embodiments described with reference to FIGS. 1-18 , the nitriding process (eg, nitriding process 265 ) is performed after forming the first conductor plate, the second conductor plate, and/or the third conductor plate. Figure 19 depicts an alternative method 300 of forming a MIM capacitor. Method 300 is similar to method 100. One of the differences between method 100 and method 300 includes replacing the nitriding process (eg, the nitriding process in block 108) with an ALD process. More specifically, as shown in FIG. 20 , after forming the first conductor plate 262 ′ and forming the oxide layer 263 (eg, TiO ₂ ) in block 106 , the method 300 proceeds to block 108 ′. , before forming the first insulator structure 264, another oxide layer 401 is deposited on the workpiece 200'. In one embodiment, oxide layer 401 includes titanium oxide (TiO ₂ ) and is formed by ALD. That is, the composition of the oxide layer 401 is the same as the composition of the oxide layer 263 . Oxide layer 401 has higher uniformity, better morphology, and fewer defects than oxide layer 263 . After the oxide layer 401 is formed, the operations in blocks 110-122 may be performed to complete the fabrication of the workpiece 200'. Workpiece 200' in Figure 20 is similar to workpiece 200 in Figure 15, one of the differences between workpiece 200' and workpiece 200 includes that workpiece 200' does not have a nitrided oxide layer (eg, TiON), conversely, workpiece 200 ′ includes an oxide layer 263 extending along the sidewalls and top surface of the first conductor plate 262 ′, and a conformal oxide layer 401 (eg, TiO ₂ ) formed on the oxide layer 263 and the oxide layer 258 . Similarly, workpiece 200' may also include oxide layers 403, 404, and 405 formed with the formation of conductor plates 266 and 270a and dummy conductive features 270b, respectively, and conformal oxide layer 402 formed by ALD (eg, TiO ₂ ). Conformal oxide layer 402 is similar to conformal oxide layer 401 .

Figure 22 depicts a partial cross-sectional view of MIM capacitor 272 in workpiece 200'. More specifically, as shown in FIG. 22 , the workpiece 200 ′ includes a first conductor plate 262 ′, an oxide layer 263 extending along the sidewalls and top surface of the first conductor plate 262 ′, on and with the oxide layer 263 . The oxide layer 263 is in direct contact with the oxide layer 401, the first high-K dielectric layer 264a on and in direct contact with the oxide layer 401, the second high-K dielectric layer 264a on the first high-K dielectric layer 264a. Dielectric layer 264b, a third high-K dielectric layer 264c on the second high-K dielectric layer 264b, and a second conductor plate on the third high-K dielectric layer 264c and overlapping the first conductor plate 262' 266. In one embodiment, the first and third high-K dielectric layers 264a and 264c include HZO, and the second high-K dielectric layer 264b includes aluminum oxide (Al ₂ O ₃ ) or titanium oxide (TiO ₂ ).

Methods of increasing the forward bias breakdown voltage (e.g., forming a titanium oxide layer on the first and/or second insulator structures 264/264'/268) may also be applied to the workpiece 200' to increase the positive voltage of the workpiece 200'. bias breakdown voltage. For example, in the embodiment shown in FIG. 23, a first insulator structure 264' including a first high-K dielectric layer 264a' and a fourth high-K dielectric layer 264d is formed on the oxide layer 401. In the embodiment shown in FIG. 24, a first insulator structure 264" including a first insulator structure 264 and a fourth high-K dielectric layer 264d is formed on the oxide layer 401. In an embodiment, the oxide layer 401 and The fourth high-K dielectric layer 264d both includes titanium oxide (TiO ₂ ), and the second high-K dielectric layer 264 b includes aluminum oxide (Al ₂ O ₃ ) or titanium oxide (TiO ₂ ). As above with reference to Figure 16-Fig. 18, it may be advantageous to increase the forward bias breakdown voltage of the workpiece 200'. Although the embodiment shown in Figures 22-24 is for the space between the first conductor plate 262' and the second conductor plate 266 first insulator structure, but it should be understood that these embodiments are also applicable to the insulator structure between the second conductor plate 266 and the third conductor plate 270a or any other insulator structure between two adjacent conductor plates.

Although not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits to semiconductor structures and their formation. For example, the present disclosure provides a multilayer insulator structure disposed between two adjacent conductor plates of a metal-insulator-metal capacitor. In the described embodiments, by providing a multi-layer insulator structure, the TDDB performance of the metal-insulator-metal capacitor can be improved. In some embodiments, the forward bias breakdown voltage of the metal-insulator-metal capacitor may also be increased. Therefore, the overall performance and reliability of the metal-insulator-metal capacitor can be advantageously improved.

This disclosure provides many different embodiments. Semiconductor structures and methods of fabricating the same are disclosed herein. In an exemplary aspect, the present disclosure relates to a method. The method includes: depositing a first conductive material layer over a substrate; patterning the first conductive material layer to form a first conductor plate over the substrate; forming a first high-K dielectric layer over the first conductor plate; forming a second high-K dielectric layer on a high-K dielectric layer; forming a third high-K dielectric layer on the second high-K dielectric layer; and forming a conductor on the third high-K dielectric layer and in contact with the first conductor. The plates vertically overlap a second conductor plate, wherein the first high-K dielectric layer has the same composition as the third high-K dielectric layer and is different from the composition of the second high-K dielectric layer.

In some embodiments, the first high-K dielectric layer and the third high-K dielectric layer may include hafnium zirconium oxide (HZO). In some embodiments, the second high-K dielectric layer may include aluminum oxide (Al ₂ O ₃ ) or titanium oxide (TiO ₂ ). In some embodiments, patterning the first conductive material layer includes performing an etching process on the first conductive material layer, wherein performing the etching process further oxidizes the sidewalls and top surface of the first conductor plate to form an oxide layer. In some embodiments, the method may further include, prior to forming the first high-K dielectric layer, performing a nitriding process on the oxide layer to form a nitrided oxide layer on the first conductor plate. In some embodiments, after performing the nitriding process, the nitrogen content in the upper portion of the first conductor plate is greater than the nitrogen content in the lower portion of the first conductor plate. In some embodiments, the method may further include forming a fourth high-K dielectric layer on the third high-K dielectric layer, wherein the composition of the fourth high-K dielectric layer is the same as the composition of the first high-K dielectric layer. different. In some embodiments, the composition of the fourth high-K dielectric layer is the same as the composition of the second high-K dielectric layer. In some embodiments, the thickness of the third high-K dielectric layer is substantially equal to the thickness of the first high-K dielectric layer.

In another exemplary aspect, the present disclosure relates to a method. The method includes: forming a first conductor plate on a first insulating layer over a substrate; forming a second insulating layer extending along a top surface and a sidewall surface of the first conductor plate; conformally forming the first conductor plate over the first conductor plate. forming a multi-layer dielectric structure, wherein the multi-layer dielectric structure is in direct contact with both the first insulating layer and the second insulating layer, and wherein the multi-layer dielectric structure is formed from a high-K dielectric layer; and forming a multi-layer dielectric structure located on the multi-layer dielectric layer A second conductor plate above the structure and vertically overlapping the first conductor plate.

In some embodiments, conformally forming the multi-layer dielectric structure includes conformally depositing a first high-K dielectric layer over the first conductor plate, wherein the first high-K dielectric layer is in contact with the first insulating layer and The second insulating layer is both in direct contact; a second high-K dielectric layer is conformally deposited on the first high-K dielectric layer; and a third high-K dielectric layer is conformally deposited on the second high-K dielectric layer. , wherein the composition of the second high-K dielectric layer is different from the composition of the first high-K dielectric layer and the composition of the third high-K dielectric layer. In some embodiments, conformally forming the multi-layer dielectric structure further includes: conformally depositing a fourth high-K dielectric layer on the third high-K dielectric layer, wherein the composition of the fourth high-K dielectric layer The composition of the first high-K dielectric layer and the composition of the third high-K dielectric layer are different. In some embodiments, the composition of the fourth high-K dielectric layer is the same as the composition of the second high-K dielectric layer. In some embodiments, forming the first conductor plate includes: depositing a layer of conductive material on the first insulating layer; and performing an etching process to pattern the layer of conductive material to form the first conductor plate, wherein the performance of the etching process further oxidizes The side walls and top surface of the first conductor plate form a second insulating layer. In some embodiments, the method may further include performing a nitridation plasma treatment on the second insulating layer after performing the etching process. In some embodiments, the method may further include conformally depositing a dielectric layer over the first insulating layer after performing the etching process, wherein the dielectric layer has the same composition as the second insulating layer.

In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a metal-insulator-metal (MIM) capacitor on a first insulating layer over a substrate, the MIM capacitor including a first conductor plate on the first insulating layer and a second insulating layer along Extending over and over the sidewalls and top surface of the first conductor plate, a conformal dielectric structure is located over the substrate and the first conductor plate, wherein the conformal dielectric structure is formed by A plurality of high-K dielectric layers are formed, and a second conductor plate is located above the conformal dielectric structure and vertically overlaps the first conductor plate, wherein the conformal dielectric structure is directly connected to both the second insulating layer and the first insulating layer. touch.

In some embodiments, the conformal dielectric structure may include: a first hafnium zirconium oxide layer over a second insulating layer; an aluminum oxide layer over the first hafnium zirconium oxide layer; and a second hafnium zirconium oxide layer over on the aluminum oxide layer, wherein the thickness of the first hafnium zirconium oxide layer is substantially equal to the thickness of the second hafnium zirconium oxide layer. In some embodiments, the first conductor plate includes titanium nitride (TiN) and the second insulating layer includes titanium oxynitride (TiON). In some embodiments, the nitrogen content in the upper portion of the first conductor plate is greater than the nitrogen content in the lower portion of the first conductor plate.

The above summarizes features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the invention, and that they can make various changes, substitutions and alterations in the invention without departing from the spirit and scope of the invention. .

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:

depositing a first layer of conductive material over a substrate;

patterning the first conductive material layer to form a first conductor plate over the substrate;

forming a first high-K dielectric layer over the first conductor plate;

forming a second high-K dielectric layer over the first high-K dielectric layer;

forming a third high-K dielectric layer over the second high-K dielectric layer; and

forming a second conductor plate positioned above the third high-K dielectric layer and vertically overlapped with the first conductor plate,

Wherein the composition of the first high-K dielectric layer is the same as the composition of the third high-K dielectric layer and is different from the composition of the second high-K dielectric layer.

2. The method of claim 1, wherein the first high-K dielectric layer and the third high-K dielectric layer comprise hafnium zirconium oxide.

3. The method of claim 2, wherein the second high-K dielectric layer comprises aluminum oxide or titanium oxide.

4. The method of claim 1, wherein patterning the first conductive material layer comprises performing an etching process on the first conductive material layer, wherein performing the etching process further oxidizes sidewalls and a top surface of the first conductor plate to form an oxide layer.

5. The method of claim 4, further comprising:

a nitridation process is performed on the oxide layer prior to forming the first high-K dielectric layer, thereby forming a nitrided oxide layer on the first conductor plate.

6. The method of claim 5, wherein after performing the nitriding treatment, a nitrogen content in an upper portion of the first conductor plate is greater than a nitrogen content in a lower portion of the first conductor plate.

7. A method of fabricating a semiconductor structure, comprising:

Forming a first conductor plate on the first insulating layer above the substrate;

forming a second insulating layer extending along a top surface and a sidewall surface of the first conductor plate;

conformally forming a multi-layer dielectric structure over the first conductor plate, wherein the multi-layer dielectric structure is in direct contact with both the first insulating layer and the second insulating layer, and wherein the multi-layer dielectric structure is formed of a high-K dielectric layer; and

a second conductor plate is formed overlying the multi-layer dielectric structure and vertically overlapping the first conductor plate.

8. A semiconductor structure, comprising:

a metal-insulator-metal capacitor on a first insulating layer over a substrate, the metal-insulator-metal capacitor comprising:

a first conductor plate on the first insulating layer,

a second insulating layer extending along and over the sidewalls and top surface of the first conductor plate,

a conformal dielectric structure over the substrate and the first conductor plate, wherein the conformal dielectric structure is formed of a plurality of high-K dielectric layers, an

A second conductor plate over the conformal dielectric structure and vertically overlapping the first conductor plate,

Wherein the conformal dielectric structure is in direct contact with both the second insulating layer and the first insulating layer.

9. The semiconductor structure of claim 8, wherein the conformal dielectric structure comprises:

a first hafnium zirconium oxide layer over the second insulating layer;

an aluminum oxide layer on the first hafnium zirconium oxide layer; and

a second hafnium zirconium oxide layer on the aluminum oxide layer,

wherein the thickness of the first hafnium zirconium oxide layer is equal to the thickness of the second hafnium zirconium oxide layer.

10. The semiconductor structure of claim 8, wherein the first conductor plate comprises titanium nitride and the second insulating layer comprises titanium oxynitride.