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CN117317017A - Silicon carbide MOSFET device and preparation method thereof - Google Patents

Silicon carbide MOSFET device and preparation method thereof Download PDF

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Publication number
CN117317017A
CN117317017A CN202311405655.2A CN202311405655A CN117317017A CN 117317017 A CN117317017 A CN 117317017A CN 202311405655 A CN202311405655 A CN 202311405655A CN 117317017 A CN117317017 A CN 117317017A
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China
Prior art keywords
silicon carbide
region
source
layer
drift layer
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CN202311405655.2A
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Inventor
王正
杨程
万胜堂
王坤
陈鸿骏
赵耀
王毅
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Yangzhou Yangjie Electronic Co Ltd
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Yangzhou Yangjie Electronic Co Ltd
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Priority to CN202311405655.2A priority Critical patent/CN117317017A/en
Publication of CN117317017A publication Critical patent/CN117317017A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode

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Abstract

A silicon carbide MOSFET device and a method for making the same. Relates to the technical field of semiconductors. Comprises a silicon carbide substrate and a silicon carbide drift layer which are sequentially arranged from bottom to top; the top surface of the silicon carbide drift layer is provided with a plurality of PW regions which extend downwards at intervals; the top surface of the PW region is provided with a NP region and a PP region I which extend downwards; a groove at the source stage is arranged between adjacent PW regions, and a PP region II extending downwards is arranged at the bottom of the groove at the source stage; the end part and the middle part of the top surface of the silicon carbide drift layer are respectively provided with a gate oxide layer, a Poly layer and an isolation layer which are sequentially arranged from bottom to top; the isolation layer extends downwards from the side part to be connected with the NP region; according to the invention, the trench body diode is formed in the silicon carbide MOSFET, so that the body diode is conducted from the N-type drift layer, the conducting capacity of the body diode is improved, and the lattice defect spreading caused by the recombination phenomenon of electrons and holes is effectively avoided, thereby reducing the device performance degradation caused by the bipolar degradation phenomenon.

Description

Silicon carbide MOSFET device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon carbide MOSFET device and a preparation method thereof.
Background
Silicon carbide is used as a third-generation semiconductor material, the critical breakdown field strength of the silicon carbide is 10 times that of a Si material, the forbidden bandwidth and the thermal conductivity of the silicon carbide are 3 times that of the Si material, and the concentration of an intrinsic carrier is only one tenth that of the Si material. Wherein, the wide forbidden band characteristic can realize lower leakage current and high-temperature working capacity; the thickness of the drift region of the blocking voltage can be reduced by 10 times by the strength of the high-critical breakdown electric field, so that the on resistance of the high-voltage class device is greatly reduced; while high thermal conductivity may allow for higher power dissipation in the device and reduce the requirements for cooling equipment. These significant advantages make silicon carbide an ideal material for making high power, high frequency, high temperature resistant, radiation resistant devices.
The silicon carbide MOSFET device is a switch type device applied to the high-power field and mainly applied to the voltage range of 650V to 1700V. Compared with silicon-based IGBT, the silicon carbide MOSFET has parasitic body diode, and can realize protection without additional parallel diode, but the parasitic body diode has obvious disadvantages while bringing advantages. Since silicon carbide MOSFETs have lattice defects such as Basal Plane Dislocations (BPDs), the parasitic body diode of the silicon carbide MOSFET transfers holes in the P region to the N-type silicon carbide drift layer during turn-on, and when electrons and holes recombine at crystal defects of the drift layer, the crystal defects may be further enlarged by the energy of the electrons and holes, so that bipolar degradation occurs, and a large defect region occurs. Larger defect areas may reduce device performance, such as increasing on-resistance and increasing leakage current.
Disclosure of Invention
The invention designs a silicon carbide MOSFET device, which improves the through-current capability of a device body diode and reduces the bipolar degradation risk of the device, and a preparation method thereof.
The technical scheme of the invention is as follows: a silicon carbide MOSFET device comprises a silicon carbide substrate and a silicon carbide drift layer which are sequentially arranged from bottom to top;
the top surface of the silicon carbide drift layer is provided with a plurality of PW regions which extend downwards at intervals;
the top surface of the PW region is provided with a NP region and a PP region I which extend downwards;
a groove at the source stage is arranged between adjacent PW regions, and a PP region II extending downwards is arranged at the bottom of the groove at the source stage;
the end part and the middle part of the top surface of the silicon carbide drift layer are respectively provided with a gate oxide layer, a Poly layer and an isolation layer which are sequentially arranged from bottom to top; the isolation layer extends downwards from the side part to be connected with the NP region;
the top surface of the silicon carbide drift layer is provided with source-level ohmic contact metal connected with the PP area I and the NP area;
source Schottky contact metal deposited on the top surface of the source ohmic contact metal and passing through the groove at the source is arranged between the adjacent isolation layers;
and a front source electrode metal is arranged above the isolation layer.
Specifically, the conductivity types of the silicon carbide substrate and the silicon carbide drift layer are both N-type.
Specifically, the doping impurity and the concentration of the first PP region and the second PP region are the same.
Specifically, the doping impurities of the first PP region and the second PP region are Al ions, and the doping concentration is 5E18/cm 3 。
Specifically, the depth of the groove at the source stage is larger than the junction depth of the PW region.
A preparation method of a silicon carbide MOSFET device comprises the following steps:
s100, epitaxially growing a silicon carbide drift layer on a silicon carbide substrate;
s200, preliminarily forming a PW region on the silicon carbide drift layer through ion implantation;
s300, forming an NP region on the silicon carbide drift layer preliminarily through ion implantation;
s400, forming a groove at the source level on the silicon carbide drift layer through an etching process;
s500, respectively preliminarily forming PP regions on the silicon carbide drift layer and the trenches at the source level by ion implantation;
s600, forming PW region, NP region and PP region by activating diffusion;
s700, forming a gate oxide layer on the silicon carbide drift layer through dry oxygen growth;
s800, forming a Poly layer on the gate oxide layer by depositing polysilicon, and leading out the Poly layer as a gate electrode;
s900, depositing silicon dioxide connected with the NP region on the Poly layer to form an isolation layer;
s1000, depositing source-level ohmic contact metal on the NP region and the PP region;
s1100, source-level Schottky contact metal which is deposited on the top surface of source-level ohmic contact metal and passes through a groove at the source level is arranged between isolation layers;
and S1200, depositing front source metal on the uppermost part of the device and leading out as a source electrode.
Specifically, the PP region includes a first PP region disposed on the NP region side and a second PP region (6 b) disposed in the trench at the source.
Specifically, the depth of the trench at the source in step S400 is greater than the depth of the PW region by 0.2-0.3um.
Specifically, the implanted ions in steps S200 and S500 are Al ions, respectively.
Specifically, the implanted ions in step S300 are N ions.
According to the invention, the trench body diode is formed in the silicon carbide MOSFET, so that the body diode is conducted from the N-type drift layer, the conducting capacity of the body diode is improved, and the lattice defect spreading caused by the recombination phenomenon of electrons and holes is effectively avoided, thereby reducing the device performance degradation caused by the bipolar degradation phenomenon. Because the structure is easy to cause the increase of leakage current between the source electrode and the drain electrode of the silicon carbide MOSFET device, the high-doped P region is formed by injecting under the trench body diode, so that the high-doped P region, the PW region and the N-type drift layer form an electric field shielding region, the increase of leakage current is avoided, and the pressure resistance of the device is ensured.
Drawings
FIG. 1 is a schematic diagram of the structure of step S100 of the present invention;
FIG. 2 is a schematic diagram of the structure of step S200 of the present invention;
FIG. 3 is a schematic diagram of the structure of step S300 of the present invention;
FIG. 4 is a schematic structural diagram of step S400 of the present invention;
FIG. 5 is a schematic structural diagram of step S500 of the present invention;
FIG. 6 is a schematic structural diagram of step S700 of the present invention;
FIG. 7 is a schematic structural diagram of step S800 of the present invention;
FIG. 8 is a schematic structural diagram of step S900 of the present invention;
FIG. 9 is a schematic structural diagram of step S1000 of the present invention;
FIG. 10 is a schematic diagram of the structure of step S1100 of the present invention;
FIG. 11 is a schematic structural diagram of step S1200 of the present invention;
in the figure, 1 is a silicon carbide substrate, 2 is a silicon carbide drift layer, 3 is a PW region, 4 is an NP region, 5 is a trench at a source, 6a is a PP region one, 6b is a PP region two, 7 is a gate oxide layer, 8 is a Poly layer, 9 is an isolation layer, 10 is a source ohmic contact metal, 11 is a source Schottky contact metal, and 12 is a front source metal.
Detailed Description
The present invention will be described in detail with reference to specific practical examples. Examples of which are shown in the accompanying drawings and the description thereof are for the purpose of illustrating the invention only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1-11; a silicon carbide MOSFET device comprising a silicon carbide substrate 1 and a silicon carbide drift layer 2 arranged in this order from bottom to top;
the top surface of the silicon carbide drift layer 2 is provided with a plurality of PW regions 3 which extend downwards at intervals;
the top surface of the PW region 3 is provided with a NP region 4 and a PP region 6a which extend downwards;
a source-level groove 5 is arranged between adjacent PW regions 3, and a downward extending PP region II 6b is arranged at the bottom of the source-level groove 5;
the end part and the middle part of the top surface of the silicon carbide drift layer 2 are respectively provided with a gate oxide layer 7, a Poly layer 8 and an isolation layer 9 which are sequentially arranged from bottom to top; the isolation layer 9 extends downwards from the side part to be connected with the NP region 4;
the top surface of the silicon carbide drift layer 2 is provided with source-level ohmic contact metal 10 connected with the PP region I6 a and the NP region 4;
source Schottky contact metal 11 deposited on the top surface of the source ohmic contact metal 10 and passing through the trench 5 at the source is arranged between the adjacent isolation layers 9;
a front source metal 12 is arranged above the isolation layer 9 and is led out as a source electrode.
Further defined, the conductivity type of the silicon carbide substrate 1 and the silicon carbide drift layer 2 are both N-type.
Further defined, the first PP region 6a and the second PP region 6b are doped with the same impurity and concentration.
Further limiting, doping impurities of the first PP region 6a and the second PP region 6b into Al ions, wherein the doping concentration is 5E18/cm 3 。
Further defined, the depth of the trench 5 at the source is greater than 0.2-0.3um of the junction depth of the PW region.
A preparation method of a silicon carbide MOSFET device comprises the following steps:
s100, referring to fig. 1, epitaxially growing a silicon carbide drift layer 2 on a silicon carbide substrate 1;
s200, referring to FIG. 2, after a patterned mask oxide layer is formed on the silicon carbide drift layer 2 through dielectric film deposition, photoetching and etching, a PW region 3 is preliminarily formed through ion implantation;
s300, referring to FIG. 3, after a patterned mask oxide layer is formed on the silicon carbide drift layer 2 through dielectric film deposition, photoetching and etching, an NP region 4 is initially formed through ion implantation;
s400, referring to FIG. 4, after a patterned mask oxide layer is formed on the silicon carbide drift layer 2 through dielectric film deposition, photoetching and etching, a trench 5 at a source stage is formed through an etching process;
s500, referring to FIG. 5, after a patterned mask oxide layer is formed by dielectric film deposition, photoetching and etching on the silicon carbide drift layer 2 and the trench 5 at the source stage, a PP region (6 a and 6b in the figure) is preliminarily formed by ion implantation respectively;
s600, performing activation diffusion through high-temperature activation annealing to form a PW region 3, an NP region 4 and a PP region;
s700, referring to fig. 6, forming a gate oxide layer 7 on the silicon carbide drift layer 2 by dry oxygen growth;
s800, referring to fig. 7, a Poly layer 8 is formed by depositing polysilicon on the gate oxide layer 7 and is extracted as a gate electrode;
s900, referring to FIG. 8, depositing silicon dioxide connected with the NP region 4 on the Poly layer 8 to form an isolation layer 9, isolating the grid electrode and the source stage and avoiding two short circuits;
s1000, referring to fig. 9, depositing source ohmic contact metal 10 on the NP region 4 and PP region 6a;
s1100, referring to fig. 10, a source schottky contact metal 11 deposited on the top surface of the source ohmic contact metal 10 and passing through the trench 5 at the source is provided between the adjacent isolation layers 9;
and S1200, depositing a front source metal 12 at the uppermost part of the device and leading out as a source electrode.
Further defined, the PP region includes a first PP region 6a disposed on the NP region 4 side and a second PP region 6b disposed within the trench 5 at the source.
Further defined, the depth of the trench 5 at the source in step S400 is greater than the depth of the PW region 3 by 0.2-0.3um.
Principle of: the trench schottky junction diode is easy to cause leakage current increase between the source and the drain, so in the device turn-off process, in order to avoid the leakage current increase, the depth of the trench 5 at the source is not easy to be larger than the junction depth of the PW region 3, if the depth is too large, the leakage current flowing to the schottky junction diode is not easy to pinch off between the PP region two 6b and the PW region 3, and therefore the depth of the trench is set to be 0.2-0.3um. It is verified that the body diode current capacity of the SiC MOSFET is improved by about 120% compared with the conventional SiC MOSFET.
Further limited, the implantation ions in steps S200 and S500 are Al ions, respectively, with implantation energy ranging from 30 to 500keV and implantation dose ranging from 1E12 to 1E16cm -2 The injection temperature is 400-600 ℃.
Further limiting the implantation ion in the step S300 to N ion with implantation energy ranging from 20 to 300keV and implantation dosage ranging from 3.6E11 to 1E15cm -2 The injection temperature is normal temperature.
Further defined, the high temperature activation annealing temperature in step S600 is 1600 ℃ -1900 ℃.
The innovation points of the scheme are as follows:
1. the through-current capability of the device body diode is improved: compared with PN junction diode, the Schottky junction diode has lower forward voltage drop and stronger through-current capability. In this case, by forming a trench schottky junction diode in the SiC MOSFET, the body diode is converted from a PN junction diode to a schottky junction diode, and the schottky junction contact area is further increased, so that the current passing capability of the body diode is improved. Simulation shows that compared with the parasitic body diode of the conventional SiC MOSFET device, the body diode current capacity of the SiC MOSFET can be improved by about 120 percent
2. Reducing the risk of bipolar degradation of the device: bipolar degradation of SiC MOSFETs is due to defect propagation caused by holes of PW region 3 entering the N-drift layer and recombining with electrons thereof during body diode operation. The body diode is transferred from the PN junction diode of the PW region 3 to the Schottky diode of the N-drift layer, so that holes of the PW region 3 are prevented from entering the N-drift layer, and the bipolar degradation risk of the device is reduced.
For the purposes of this disclosure, the following points are also described:
(1) The drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;
(2) The embodiments disclosed herein and features of the embodiments may be combined with each other to arrive at new embodiments without conflict;
the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A silicon carbide MOSFET device comprising a silicon carbide substrate (1) and a silicon carbide drift layer (2) arranged in that order from below;
the top surface of the silicon carbide drift layer (2) is provided with a plurality of PW regions (3) which extend downwards at intervals;
the top surface of the PW region (3) is provided with a NP region (4) and a PP region I (6 a) which extend downwards;
an active level groove (5) is arranged between adjacent PW regions (3), and a downward extending PP region II (6 b) is arranged at the bottom of the active level groove (5);
the end part and the middle part of the top surface of the silicon carbide drift layer (2) are respectively provided with a gate oxide layer (7), a Poly layer (8) and an isolation layer (9) which are sequentially arranged from bottom to top; the isolating layer (9) extends downwards from the side part and is connected with the NP region (4);
the top surface of the silicon carbide drift layer (2) is provided with source-level ohmic contact metal (10) connected with the PP zone I (6 a) and the NP zone (4);
source Schottky contact metal (11) deposited on the top surface of the source ohmic contact metal (10) and passing through the groove (5) at the source is arranged between the adjacent isolation layers (9);
and a front source electrode metal (12) is arranged above the isolation layer (9).
2. A silicon carbide MOSFET device according to claim 1, characterized in that the silicon carbide substrate (1) and the silicon carbide drift layer (2) are both of N-type conductivity.
3. A silicon carbide MOSFET device according to claim 1, characterized in that the PP region one (6 a) and PP region two (6 b) are doped with the same impurity concentration.
4. A silicon carbide MOSFET device according to claim 3, characterized in that the first (6 a) and second (6 b) PP regions are doped with Al ions at a doping concentration of 5E18/cm 3 。
5. A silicon carbide MOSFET device according to claim 1, characterized in that the depth of the trench (5) at the source is greater than the PW junction depth.
6. A method for fabricating a silicon carbide MOSFET device comprising the steps of:
s100, epitaxially growing a silicon carbide drift layer (2) on a silicon carbide substrate (1);
s200, initially forming a PW region (3) on the silicon carbide drift layer (2) through ion implantation;
s300, forming an NP region (4) on the silicon carbide drift layer (2) preliminarily through ion implantation;
s400, forming a groove (5) at a source stage on the silicon carbide drift layer (2) through an etching process;
s500, respectively forming PP regions on the silicon carbide drift layer (2) and the grooves (5) at the source stage through ion implantation preliminarily;
s600, forming PW region (3), NP region (4) and PP region by activating diffusion;
s700, forming a gate oxide layer (7) on the silicon carbide drift layer (2) through dry oxygen growth;
s800, forming a Poly layer (8) on the gate oxide layer (7) by depositing polysilicon, and leading out the Poly layer as a gate electrode;
s900, depositing silicon dioxide connected with the NP region (4) on the Poly layer (8) to form an isolation layer (9);
s1000, depositing source-level ohmic contact metal (10) on the NP region (4) and the PP region (6 a);
s1100, source-level Schottky contact metal (11) which is deposited on the top surface of source-level ohmic contact metal (10) and passes through a groove (5) at the source level is arranged between isolation layers (9);
and S1200, depositing a front source metal (12) at the uppermost part of the device and leading out as a source electrode.
7. The method of manufacturing a silicon carbide MOSFET device according to claim 6, wherein the PP region comprises a first PP region (6 a) disposed on the NP region (4) side and a second PP region (6 b) disposed in the trench (5) at the source.
8. The method of manufacturing a silicon carbide MOSFET device according to claim 6, wherein the depth of the trench (5) at the source in step S400 is 0.2-0.3um greater than the depth of the PW region (3).
9. The method of manufacturing a silicon carbide MOSFET device according to claim 6, wherein the implanted ions in steps S200 and S500 are Al ions, respectively.
10. The method of manufacturing a silicon carbide MOSFET device according to claim 6, wherein the implanted ions in step S300 are N ions.
CN202311405655.2A 2023-10-27 2023-10-27 Silicon carbide MOSFET device and preparation method thereof Pending CN117317017A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118213276A (en) * 2024-05-20 2024-06-18 扬州扬杰电子科技股份有限公司 Trench gate silicon carbide MOSFET device and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118213276A (en) * 2024-05-20 2024-06-18 扬州扬杰电子科技股份有限公司 Trench gate silicon carbide MOSFET device and preparation method thereof

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