CN117293103B

CN117293103B - Chip packaging structure

Info

Publication number: CN117293103B
Application number: CN202311324598.5A
Authority: CN
Inventors: 邹本辉; 赵烨; 沙大喜; 汤田华; 王挺
Original assignee: Suzhou Rongrui Electronic Technology Co ltd
Current assignee: Suzhou Rongrui Electronic Technology Co ltd
Priority date: 2023-10-13
Filing date: 2023-10-13
Publication date: 2024-09-13
Anticipated expiration: 2043-10-13
Also published as: CN117293103A

Abstract

The application provides a chip packaging structure which comprises a first heat conduction layer, a second heat conduction layer, a sealing layer and a metal lead wire, wherein the first heat conduction layer, the second heat conduction layer and the sealing layer are arranged on the periphery of a wafer layer, and the metal lead wire is electrically connected with the wafer layer. The first heat conduction layer wraps the wafer layer, the thickness of the wafer layer is 0.4-0.6mm, and the thickness of the first heat conduction layer is 0.08-0.12mm; the second heat conduction layer does not completely wrap the first heat conduction layer, the area of the second heat conduction layer covering the first heat conduction layer is more than 90% of the area of the first heat conduction layer, and the thickness of the second heat conduction layer is 0.18-0.22mm; the heat conductivity of the second heat conduction layer is larger than that of the first heat conduction layer; the thickness of the sealing layer is 0.2-0.4mm so as to improve the overall heat dissipation effect of the chip packaging structure.

Description

Chip packaging structure

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a chip packaging structure.

Background

The current high-power chip packaging device can be used in the fields of aerospace, microwave communication, electronic components and the like, and along with the development of the device to multifunctional integration, miniaturization and light weight, the reliability requirement of the current device is hardly met by the traditional chip packaging.

The traditional chip packaging technology is a shell for mounting a semiconductor integrated circuit chip, plays roles of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and the chip packaging is divided into wafer cutting, surface mounting, wire bonding, injection molding and packaging test. In the conventional scheme, as shown in fig. 1, after the metal leads are sealed by using epoxy resin in injection molding, heat dissipation of the chip wafer layer 01 is mainly concentrated on the epoxy resin part 02 and the lead metal part 03, but because the area of the lead metal part 03 is too small and the heat dissipation is mainly concentrated on the epoxy resin part 02, the heat conductivity coefficient of the epoxy resin is only 0.21W/(m·k), so that the heat dissipation is only carried out by the epoxy resin part 02 and the lead metal part 03, and the heat dissipation requirement of a high-power chip packaging device can not be met far.

Disclosure of Invention

In view of the above, the present application provides a chip package structure, which includes a first heat conductive layer, a second heat conductive layer, a sealing layer, and a metal lead electrically connected to the wafer layer. In one aspect, the first heat conductive layer completely encapsulates the wafer layer, such that heat in the wafer layer is transferred out through the first heat conductive layer at a first time. On the other hand, the second heat conduction layer with higher heat conduction coefficient is arranged outside the first heat conduction layer, heat can be further and rapidly transferred out, and the metal lead wire can be insulated due to the arrangement of the sealing layer. Therefore, compared with the prior art, the heat dissipation area of the chip packaging structure is greatly increased, and the heat dissipation effect is obviously enhanced.

The technical scheme provided by the application is as follows:

in one set of embodiments of the present application, there is provided a chip package structure including: the first heat conduction layer, the second heat conduction layer and the sealing layer are arranged on the periphery of the wafer layer, and the metal lead is electrically connected with the wafer layer;

Seen from a section of the chip packaging structure, the first heat conduction layer wraps the wafer layer, and the thickness T1 of the wafer layer is 0.4-0.6mm;

The first heat conduction layer comprises a first upper heat conduction layer and a first lower heat conduction layer; the metal lead is connected with the wafer layer and led out from the contact position of the first upper heat conduction layer and the first lower heat conduction layer, and the thickness T2 of the first heat conduction layer is 0.08-0.12mm;

The second heat conduction layer does not completely wrap the first heat conduction layer, the area of the second heat conduction layer covering the first heat conduction layer is larger than 90% of the area of the first heat conduction layer, and the thickness T3 of the second heat conduction layer is 0.18-0.22mm;

The second heat conduction layer is not completely wrapped on the first heat conduction layer, the sealing layer is filled in the position, the thickness T4 of the sealing layer is 0.2-0.4mm, and the diameter of the metal lead is 0.08-0.12mm;

the thermal conductivity of the second thermal conductive layer is greater than the thermal conductivity of the first thermal conductive layer, and the absolute value of the difference between the thermal expansion coefficient of the first thermal conductive layer and the thermal expansion coefficient of the wafer layer is less than the absolute value of the difference between the thermal expansion coefficient of the second thermal conductive layer and the thermal expansion coefficient of the wafer layer.

In one embodiment, the first upper heat conducting layer comprises a first upper main body part and two first upper wrapping parts which are respectively arranged at two sides of the first upper main body part, the first upper heat conducting layer is integrally formed, and the length of the first upper main body part is equal to that of the wafer layer; the length L1 of the first upper wrapping part is 0.08-0.12mm;

the first lower heat conduction layer comprises a first lower main body part and two first lower wrapping parts which are respectively arranged at two sides of the first lower main body part, the first lower heat conduction layer is integrally formed, and the length of the first lower main body part is equal to that of the wafer layer; the length L1 of the first lower wrapping portion is 0.08-0.12mm.

In one embodiment, the surface of the first heat conducting layer away from the wafer layer further comprises: the two filling layers are respectively a first filling layer and a second filling layer; the first filling layer is arranged above the first upper heat conduction layer, the second filling layer is arranged below the first lower heat conduction layer, the filling layer is respectively contacted with the first heat conduction layer and the second heat conduction layer, the length of the filling layer is L2, L0 is less than L2 < (L0+2) and L1;

The first heat conduction layer comprises four baffle wall structures, the baffle wall structures are respectively arranged on the two first upper wrapping portions and the two first lower wrapping portions, the filling layer is respectively and completely contacted with the first upper main body portion and the first lower main body portion, and the baffle wall structures are used for limiting the material of the filling layer between the first heat conduction layer and the second heat conduction layer.

In one embodiment, the chip package structure further includes: the two first inserting layers are respectively arranged in the first upper heat conducting layer and the first lower heat conducting layer;

The heat conductivity coefficient of the first insertion layer is larger than that of the first heat conduction layer, the thickness of the first insertion layer is T5, T2 is more than or equal to 0.25 and less than or equal to T5 and less than or equal to 0.3 and T2, and the vertical distance from the first insertion layer to the wafer layer is smaller than that from the first insertion layer to the second heat conduction layer.

In one embodiment, the second thermally conductive layer comprises: a second upper heat conductive layer in contact with the first upper heat conductive layer and a second lower heat conductive layer in contact with the first lower heat conductive layer;

The thermal conductivity of the first insertion layer is equal to the thermal conductivity of the second thermal conductive layer;

The chip packaging structure further comprises: the four first through parts are respectively arranged on the first upper heat conduction layers, one ends of the two first through parts are respectively connected with the second upper heat conduction layers in a through way, and the other ends of the two first through parts are respectively connected with the first insertion layers arranged on the first upper heat conduction layers in a through way;

The other two first through parts are respectively arranged on the first lower heat conducting layers, one ends of the other two first through parts are respectively connected with the second lower heat conducting layers in a through mode, and the other ends of the other two first through parts are respectively connected with the first inserting layers arranged on the first lower heat conducting layers in a through mode.

In one embodiment, the chip package structure further includes: the two second inserting layers are respectively arranged in the second upper heat conduction layer and the second lower heat conduction layer;

The heat conductivity coefficient of the second insertion layer is larger than that of the second heat conduction layer, the length of the second insertion layer is L3, the length of the second heat conduction layer is L4, (L0+2L1) < L3 < L4; the thickness of the second insertion layer is T6, T3 is more than or equal to 0.25 and less than or equal to T6 and less than or equal to 0.3, and the vertical distance from the second insertion layer to the first heat conduction layer is smaller than the vertical distance from the second insertion layer to the outer edge of the second heat conduction layer.

In one embodiment, the chip package structure further includes: the four second through parts are respectively arranged on the second upper heat conduction layers, one ends of the two second through parts are respectively connected to the outer surface of the whole chip packaging structure through the second upper heat conduction layers, and the other ends of the two second through parts are respectively connected with the second insertion layers arranged on the second upper heat conduction layers in a through way;

The other two second through parts are respectively arranged on the second lower heat conducting layer, one ends of the other two second through parts are respectively connected to the outer surface of the whole chip packaging structure through the second lower heat conducting layer, and the other ends of the other two second through parts are respectively connected with the second inserting layer arranged on the second lower heat conducting layer in a through mode.

In another set of embodiments of the present application, there is provided a chip package structure including: the first heat conduction layer, the second heat conduction layer and the sealing layer are arranged on the periphery of the wafer layer, and the metal lead is electrically connected with the wafer layer;

the first heat conduction layer comprises a first upper heat conduction layer and a first lower heat conduction layer; the metal lead is connected with the wafer layer and led out from the contact position of the first upper heat conduction layer and the first lower heat conduction layer, the thickness of the first upper heat conduction layer is T21, the thickness of the first lower heat conduction layer is T22, T22 is more than T21, and the thickness T21 of the first heat conduction layer is 0.08-0.12mm;

The second heat conduction layer is not completely wrapped on the first heat conduction layer, the sealing layer is filled in the position, the thickness T4 of the sealing layer is 0.18-0.22mm, and the diameter of the metal lead is 0.08-0.12mm;

In one embodiment, the second thermally conductive layer comprises: the second upper heat conduction layer is contacted with the first upper heat conduction layer, the second lower heat conduction layer is contacted with the first lower heat conduction layer, the thickness of the second upper heat conduction layer is T31, the thickness of the second lower heat conduction layer is T32, T31 is more than T32, and T32 is 0.08-0.12mm;

the chip packaging structure comprises:

The first insertion layer is arranged on the first lower heat conduction layer, the heat conduction coefficient of the first insertion layer is larger than that of the first heat conduction layer, the thickness of the first insertion layer is T5, T22 is more than or equal to 0.25 and less than or equal to 0.3 and T22, and the vertical distance from the first insertion layer to the wafer layer is smaller than that from the first insertion layer to the second heat conduction layer;

Two first through portions provided on both sides of the first insertion layer in a longitudinal direction of the first insertion layer, the two first through portions being provided in the first lower heat conductive layer, respectively, and one ends of the two first through portions being connected to the second lower heat conductive layer, respectively, and the other ends of the two first through portions being connected to the first insertion layer, respectively;

the second insertion layer is arranged on the second upper heat conduction layer, the heat conduction coefficient of the second insertion layer is larger than that of the second heat conduction layer, the thickness of the second insertion layer is T6, T31 is more than or equal to 0.25 and less than or equal to 0.3 and T31, and the vertical distance from the second insertion layer to the first heat conduction layer is smaller than that from the second insertion layer to the outer edge of the second heat conduction layer; and

And the second through parts are arranged on two sides of the second insertion layer in the length direction of the second insertion layer, the two second through parts are respectively arranged in the second upper heat conduction layer, one ends of the two second through parts are respectively in through connection with the second upper heat conduction layer, and the other ends of the two second through parts are respectively in through connection with the second insertion layer.

the first lower heat conduction layer comprises a first lower main body part and two first lower wrapping parts which are respectively arranged at two sides of the first lower main body part, the first lower heat conduction layer is integrally formed, and the length of the first lower main body part is equal to that of the wafer layer; the length L1 of the first lower wrapping part is 0.08-0.12mm;

the area of each of the first lower wrap portions is greater than the area of each of the first upper wrap portions.

The heat conductivity coefficient of the first insertion layer is larger than that of the first heat conduction layer, the thickness of the first insertion layer is T5, T21 is more than or equal to 0.25 and less than or equal to T5 and less than or equal to 0.3 and T21, and the vertical distance from the first insertion layer to the wafer layer is smaller than that from the first insertion layer to the second heat conduction layer.

In one embodiment, the second thermally conductive layer comprises: the second upper heat conduction layer is contacted with the first upper heat conduction layer, the second lower heat conduction layer is contacted with the first lower heat conduction layer, the thickness of the second upper heat conduction layer is T31, the thickness of the second lower heat conduction layer is T32, and T31 is more than T32;

The heat conductivity coefficient of the second insertion layer is larger than that of the second heat conduction layer, the length of the second insertion layer is L3, the length of the second heat conduction layer is L4, (L0+2L1) < L3 < L4; the thickness of the second insertion layer is T6, T32 is more than or equal to 0.25 and less than or equal to T6 and less than or equal to 0.3T 32, and the vertical distance from the second insertion layer to the first heat conduction layer is smaller than the vertical distance from the second insertion layer to the outer edge of the second heat conduction layer.

In one embodiment, the chip package structure further includes:

the chip packaging structure further comprises: the four second through parts are respectively arranged on the second upper heat conduction layers, one ends of the two second through parts are respectively connected to the outer surface of the whole chip packaging structure through the second upper heat conduction layers, and the other ends of the two second through parts are respectively connected with the second insertion layers arranged on the second upper heat conduction layers in a through way;

In one embodiment, the second thermally conductive layer is a ceramic material;

The chip packaging structure further comprises: a metal heat sink and a heat dissipating metal lead connected to the metal heat sink; the metal radiating fin is arranged outside the second heat conducting layer, and the wafer layer is insulated from the metal radiating fin; the heat dissipation metal lead is connected with the metal lead.

The beneficial effects are that: in one embodiment of the application, a chip package structure is provided, which includes a first heat conductive layer, a second heat conductive layer, a sealing layer, and a metal lead electrically connected to the wafer layer. The first heat conduction layer wraps the wafer layer, the thickness T1 of the wafer layer is 0.4-0.6mm, and the thickness T2 of the first heat conduction layer is 0.08-0.12mm; the second heat conduction layer does not completely wrap the first heat conduction layer, the area of the second heat conduction layer covering the first heat conduction layer is more than 90% of the area of the first heat conduction layer, and the thickness T3 of the second heat conduction layer is 0.18-0.22mm; the heat conductivity of the second heat conduction layer is larger than that of the first heat conduction layer; the thickness T4 of the sealing layer is 0.2-0.4mm, and the special structural dimension design, the special heat conductivity gradient design and the special heat expansion coefficient design of each film layer have the comprehensive effect, so that the integral heat dissipation effect of the chip packaging structure can be improved. The concrete steps are as follows: in one aspect, the first thermally conductive layer completely encapsulates the wafer layer such that heat in the wafer layer is transferred out through the first thermally conductive layer at a first time (in time). The first heat conductive layer may be provided as a high heat conductive silica gel and a high heat conductive material. On the other hand, the second heat conduction layer with higher heat conduction coefficient is arranged outside the first heat conduction layer and used for further transmitting heat in the first heat conduction layer to the outside of the wafer layer. The second heat conductive layer may be provided as a metal or ceramic for preventing aging of the first heat conductive layer. In addition, when the second heat conduction layer surrounds the first heat conduction layer, a part of gaps are arranged, the gaps are filled with sealing layers, and the sealing layers can be made of materials such as epoxy resin. The sealing layer can seal the metal lead wire, and insulation between the wafer layer and the second heat conduction layer is achieved. Compared with the prior art, the heat dissipation area of the chip packaging structure is greatly increased, and the heat dissipation effect is obviously enhanced.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a chip package structure provided in the prior art;

FIG. 2 is a first schematic diagram of a chip package structure according to a first set of embodiments of the present application;

FIG. 3 is a second schematic diagram of a chip package structure according to the first embodiment of the present application;

FIG. 4 is a third schematic diagram of a chip package structure according to the first set of embodiments of the present application;

FIG. 5 is a fourth schematic diagram of a chip package structure according to the first set of embodiments of the present application;

FIG. 6 is a fifth schematic diagram of a chip package structure according to the first set of embodiments of the present application;

FIG. 7 is a sixth schematic diagram of a chip package structure according to the first set of embodiments of the present application;

FIG. 8 is a seventh schematic diagram of a chip package structure according to a first set of embodiments of the present application;

FIG. 9 is an eighth schematic diagram of a chip package structure according to a first set of embodiments of the present application;

Fig. 10 is a top view of a chip package structure according to a first set of embodiments of the present application;

FIG. 11 is a first schematic diagram of a chip package structure according to a second set of embodiments of the present application;

FIG. 12 is a second schematic diagram of a chip package structure according to a second set of embodiments of the present application;

FIG. 13 is a third schematic diagram of a chip package structure according to a second set of embodiments of the present application;

FIG. 14 is a fourth schematic diagram of a chip package structure according to a second set of embodiments of the present application;

FIG. 15 is a fifth schematic diagram of a chip package structure according to a second set of embodiments of the present application;

FIG. 16 is a sixth schematic diagram of a chip package structure according to a second set of embodiments of the present application;

FIG. 17 is a seventh schematic diagram of a chip package structure according to a second set of embodiments of the present application;

FIG. 18 is a schematic diagram of a chip package structure according to a second embodiment of the present application;

fig. 19 is a graph showing the relationship between chip surface temperature and time for five chip package structures in the prior art and the present application.

Reference numerals:

Chip wafer layer 01, epoxy resin portion 02, lead metal portion 03, heat spreader 04.

Chip package structure 100:

wafer layer 10, metal lead 11, first heat conduction layer 12, second heat conduction layer 13, sealing layer 14, first filling layer 151, second filling layer 152, metal heat sink 16, heat dissipation metal lead 17;

The first upper heat conductive layer 121, the first upper body portion 121a, the first upper wrap portion 121b, the first lower heat conductive layer 122, the first lower body portion 122a, the first lower wrap portion 121b, the barrier wall structure 12a, the first insert layer 12b, and the first through portion 12c;

The second upper heat conductive layer 131, the second lower heat conductive layer 132, the second insertion layer 13a, and the second through portion 13b.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 2, in a first schematic diagram of a chip package structure 100 according to a first set of embodiments of the present application, the chip package structure 100 includes: wafer layer 10, metal lead 11, first heat conduction layer 12, second heat conduction layer 13 and sealing layer 14. The wafer layer 10 is connected to a metal lead 11. The wafer layer 10 may be a high-power chip, and the shape of the wafer layer 10 is not limited, and may be a strip shape or have a special-shaped structure, for example, the wafer layer 10 may be an arch shape or have a plurality of protruding structures. The thickness of the wafer layer 10 is 0.3mm-0.6mm, and the thickness T1 of a typical high power chip is 0.5mm.

As shown in fig. 2, the first heat conductive layer 12 wraps the wafer layer 10 when viewed in a cross section of the chip package structure 100. The first heat conductive layer 12 may be provided as an insulating material. The first heat conductive layer 12 may include a first upper heat conductive layer 121 and a first lower heat conductive layer 122. The first thermally conductive layer 12 may be integrally formed or may be formed in two steps. The first upper heat conducting layer 121 and the first lower heat conducting layer 122 are respectively disposed on a first surface and a second surface of the wafer layer 10, where the first surface and the second surface are two surfaces facing away from the wafer layer 10. The first thermally conductive layer 12 may be formed by dispensing, coating, liquid infusion, or sheet lamination. The specific shape of the first heat conductive layer 12 is not limited, and needs to be changed according to the change in the shape of the wafer layer 10. The thermal conductivity of the first thermal conductive layer 12 may be set to 6 to 13W/(m·k), and the thickness T2 of the first thermal conductive layer 12 may be set to 0.08mm to 0.12mm, and preferably may be set to 0.1mm. The side length (L1) of the first heat conductive layer 12 may be set to 0.08mm to 0.12mm, and preferably may be set to 0.1mm. The first thermally conductive layer 12 may be a thermally conductive silicone.

The second heat conducting layer 13 does not completely wrap the first heat conducting layer 12, and the area of the second heat conducting layer 13 covering the first heat conducting layer 12 is more than 90% of the area of the first heat conducting layer 12. The second heat conductive layer 13 is a material that is more conducive to heat dissipation. The thermal conductivity of the second thermal conductive layer 13 may be set to 100-300W/(m·k), and the thickness T3 of the second thermal conductive layer 13 may be set to 0.1mm-0.3mm, and preferably may be set to 0.2mm. The second thermally conductive layer 13 may be a metal or a ceramic material. The second heat conductive layer 13 includes a second upper heat conductive layer and a second lower heat conductive layer. The second heat conductive layer 13 may be integrally formed or may be formed in two steps. The second upper heat conducting layer is disposed on a side of the first upper heat conducting layer 121 away from the wafer layer 10, and the second lower heat conducting layer is disposed on a side of the first lower heat conducting layer 122 away from the wafer layer 10. The second heat conductive layer 13 may also be formed by dispensing, coating, liquid pouring or lamination.

The second heat conductive layer 13 is filled with the sealing layer 14 at a position where the first heat conductive layer 12 is not completely wrapped, the thickness T4 of the sealing layer 14 is 0.1-0.3mm, preferably T4 is 0.2mm, the diameter of the metal lead 11 is 0.08-0.12mm, and the diameter of the metal lead 11 is preferably 0.1mm. The sealing layer 14 is in contact with the first heat conductive layer 12, the second heat conductive layer 13, and the metal lead 11, respectively. The sealing layer 14 is used to wrap the metal lead 11 so that the metal lead 11 is in a sealed state. The sealing layer 14 may be provided as an epoxy resin.

The second heat conductive layer 13 has a heat conductivity greater than that of the first heat conductive layer 12. In addition, the thermal expansion coefficients of the layers can satisfy: the absolute value of the difference between the thermal expansion coefficient of the first thermally conductive layer 12 and the thermal expansion coefficient of the wafer layer 10 is smaller than the absolute value of the difference between the thermal expansion coefficient of the second thermally conductive layer 13 and the thermal expansion coefficient of the wafer layer 10. The heat is spontaneously transferred from the high temperature to the low temperature in the object or between the objects as long as the temperature difference exists.

In this embodiment, a heat conducting structure composed of the first heat conducting layer 12 and the second heat conducting layer 13 of high heat conducting material is adopted, so that heat in the wafer layer 10 can be stably and efficiently transferred out, and the heat dissipation efficiency of the chip is remarkably improved. In one aspect, the first heat conducting layer 12 completely wraps the wafer layer 10, so that heat in the wafer layer 10 can be timely transferred out through the first heat conducting layer 12. On the other hand, the second heat conducting layer 13 with higher heat conductivity coefficient is arranged outside the first heat conducting layer 12, so as to further transfer the heat in the first heat conducting layer 12 away from the wafer layer 10. In addition, a part of the gap is provided when the second heat conductive layer 13 surrounds the first heat conductive layer 12, and the gap is filled with the sealing layer 14. The sealing layer 14 may seal the metal lead 11, and achieve insulation between the wafer layer 10 and the outside. Compared with the prior art, the heat dissipation area of the chip packaging structure 100 is greatly increased, and the heat dissipation effect is obviously enhanced. The heat dissipation effect of the chip package structure 100 is significantly enhanced, and the service life of the semiconductor chip 10 can be effectively prolonged.

Referring to fig. 3, in a second schematic diagram of the chip package structure 100 according to the first set of embodiments of the present application, the first upper thermally conductive layer 121 includes a first upper body portion 121a and two first upper wrapping portions 121b disposed on two sides of the first upper body portion 121a, the first upper thermally conductive layer 121 is integrally formed, and the length of the first upper body portion 121a is equal to the length of the wafer layer 10 (the length is L0 as shown in fig. 3). The length L1 of the first upper wrapping portion 121b is 0.08 to 0.12mm, and may be preferably set to 0.1mm.

The first lower heat conducting layer 122 includes a first lower body portion 122a and two first lower wrapping portions 121b respectively disposed on two sides of the first lower body portion 122a, where the first lower heat conducting layer 122 is integrally formed, and the length of the first lower body portion 122a is equal to the length of the wafer layer 10 (the lengths are L0 as shown in fig. 3). The length L1 of the first lower wrapping portion 121b is 0.08 to 0.12mm, and may be preferably set to 0.1mm.

In this embodiment, the specific structures of the first upper heat conducting layer 121 and the first lower heat conducting layer 122 are further defined, the preparation process of the chip packaging structure 100 can be simplified by the heat conducting layers formed integrally respectively, the specific structure size of the heat conducting layers can be closer to the specific structure of the wafer layer 10, and the sealing of the metal leads 11 can be better realized.

Referring to fig. 4, in a third schematic diagram of the chip package structure 100 according to the first set of embodiments of the present application, a surface of the first heat conductive layer 12 away from the wafer layer 10 further includes: two filler layers. The material of the filling layer can be heat-conducting silicone grease. The two filling layers are a first filling layer 151 and a second filling layer 152 respectively; the first filling layer 151 is disposed above the first upper heat conductive layer 121, and the second filling layer 152 is disposed below the first lower heat conductive layer 122. (hereinafter, the filling layer may be understood as the first filling layer 151 and/or the second filling layer 152.) and the filling layer is in contact with the first heat conducting layer 12 and the second heat conducting layer 13, respectively, the filling layer has a length L2, L0 < L2 < (l0+2×l1). The projection of the filler layer onto the wafer layer 10 covers the entire length of the wafer layer 10. The center of the wafer layer 10 in the longitudinal direction is on the same line as the center of the filling layer in the longitudinal direction. The thickness of the filling layer is less than 0.35 x T2.

The first heat conductive layer 12 includes four barrier structures 12a. The stop wall structure 12a includes a convex stop angle, which may be an acute angle or a right angle. The formation of the dam structure 12a may be performed by recessing the first heat conductive layer 12. The thickness of the dam structure 12a may be equal to 1/2 of the thickness of the fill layer. The retaining wall structure 12a is respectively disposed on the two first upper wrapping portions 121b and the two first lower wrapping portions 121b, and the filling layer is respectively in full contact with the first upper body portion 121a and the first lower body portion 122a, and the retaining wall structure 12a is used for limiting the material of the filling layer between the first heat conduction layer 12 and the second heat conduction layer 13.

In this embodiment, the chip package structure 100 further includes a filling layer and a barrier wall structure 12a. When the first heat conducting layer 12 is a heat conducting silica gel, there are voids on the surface of the heat conducting silica gel, that is, the fine structures such as holes, cracks or protrusions on the surface of the silica gel have an influence on the surface morphology and performance. The filling layer (silicone grease) in this embodiment may be disposed to fill the surface voids of the thermally conductive silica gel (the first thermally conductive layer 12). In addition, because of extrusion phenomenon and thixotropic property of the heat-conducting silicone grease, the filling layer (heat-conducting silicone grease) needs to be limited by the baffle wall structure 12a, and is further completely wrapped by the first heat-conducting layer 12 and the second heat-conducting layer 13.

The infill layer and retaining wall structure 12a should be noted during the setup process: the filler layer is disposed with emphasis on the corresponding location of the wafer layer 10. The length L1 of the first heat conductive layer 12 on the left and right sides of the wafer layer 10 may be widened appropriately to ensure a sufficient contact area between the filling layer and the first upper heat conductive layer 121. The filling layer is made of heat-conducting silicone grease, so that the filling layer can be well contacted with metal or ceramic of the second heat-conducting layer 13, deformation is not easy to occur, and the whole thickness of the chip packaging structure 100 is particularly thin.

The process for preparing the filling layer and retaining wall structure 12a includes: the first heat conductive layer 12 is grooved to form a barrier structure 12a. The first heat conductive layer 12 is annealed to form a filling layer (heat conductive silicone grease) at a relatively high temperature, so that the heat conductive silicone gel and the heat conductive silicone grease are in close and stable contact. The temperature at which the filling layer is formed must not be too high and is generally controlled to < 150 deg..

Referring to fig. 5, in a fourth schematic diagram of the chip package structure 100 according to the first set of embodiments of the present application, the chip package structure 100 further includes: two first interposer layers 12b are disposed within the first upper thermally conductive layer 121 and the first lower thermally conductive layer 122, respectively.

The thermal conductivity of the first interposer layer 12b is greater than that of the first thermal conductive layer 12, and the thickness of the first interposer layer 12b is T5, T2 is greater than or equal to 0.25 and less than or equal to 0.3T 2. The first interposer 12b is in a 1/2 position closer to the wafer layer 10. The vertical distance from the first interposer 12b to the wafer layer 10 is smaller than the vertical distance from the first interposer 12b to the second thermally conductive layer 13. If the first heat conductive layer 12 is cut evenly in a direction perpendicular to the thickness direction, the first interposer 12b is located closer to the half of the wafer layer 10 than the first heat conductive layer 12.

In the present embodiment, the first insertion layer 12b having a higher thermal conductivity is inserted into the first thermal conductive layer 12. Specifically, the first insertion layer 12b material with higher heat conductivity such as metal particles and metal sheets is added into the heat-conducting silica gel layer to improve the heat dissipation speed. Specifically, the first interposer 12b can reduce the thermal resistance of the first heat conductive layer 12, thereby increasing the heat dissipation speed of the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

Referring to fig. 6, in a fifth schematic diagram of a chip package structure 100 according to a first set of embodiments of the present application, a second heat conductive layer 13 includes: a second upper heat conductive layer 131 in contact with the first upper heat conductive layer 121 and a second lower heat conductive layer 132 in contact with the first lower heat conductive layer 122. The thermal conductivity of the first interposed layer 12b is equal to the thermal conductivity of the second thermal conductive layer 13. The material of the first insertion layer 12b may be set to coincide with the material of the second heat conduction layer 13.

The chip package structure 100 further includes: four first through-holes 12c, wherein two first through-holes 12c are respectively provided on the first upper heat conductive layer 121, and one ends of the two first through-holes 12c are respectively connected with the second upper heat conductive layer 131 in a penetrating manner, and the other ends of the two first through-holes 12c are respectively connected with the first interposed layer 12b provided on the first upper heat conductive layer 121 in a penetrating manner.

The other two first through-holes 12c are provided in the first lower heat conductive layer 122, and one ends of the other two first through-holes 12c are connected to the second lower heat conductive layer 132, and the other ends of the other two first through-holes 12c are connected to the first interposed layer 12b provided in the first lower heat conductive layer 122.

In this embodiment, the first through portion 12c is added, so that heat collected in the first heat conducting layer 12 can be more conveniently conducted out to the second heat conducting layer 13. The heat in the first heat conducting layer 12 can be quickly conducted out to the second heat conducting layer 13 along the first through portion 12c, and the heat conducting effect is improved.

Referring to fig. 7, in a sixth schematic diagram of the chip package structure 100 according to the first set of embodiments of the present application, the chip package structure 100 further includes: two second interposed layers 13a are disposed within the second upper and lower heat conductive layers 131 and 132, respectively.

The thermal conductivity of the second interposer layer 13a is greater than that of the second thermal conductive layer 13, the length of the second interposer layer 13a is L3, the length of the second thermal conductive layer 13 is L4, (l0+2χl1) < L3 < L4. The projection of the second interposer 13a onto the wafer layer 10 covers the entire length of the wafer layer 10. The center in the longitudinal direction of the wafer layer 10 is on the same line as the center in the longitudinal direction of the second interposer 13 a. The thickness of the second insertion layer 13a is T6,0.25×t3.ltoreq.t6.ltoreq.0.3×t3. The second interposer 13a is in a 1/2 position closer to the first thermally conductive layer 12. The vertical distance from the second interposed layer 13a to the first heat conductive layer 12 is smaller than the vertical distance from the second interposed layer 13a to the outer edge of the second heat conductive layer 13. If the second heat conductive layer 13 is cut evenly in a direction perpendicular to the thickness direction, the second interposed layer 13a is located closer to the half of the first heat conductive layer 12 than the second heat conductive layer 13.

In the present embodiment, the second insertion layer 13a having a higher thermal conductivity is inserted into the second thermal conductive layer 13. Specifically, graphene material with higher heat conductivity coefficient is added into the metal layer to serve as a second insertion layer, so that the heat dissipation speed is improved. Specifically, the second interposer 13a can reduce the thermal resistance of the second heat conductive layer 13, thereby accelerating the heat dissipation speed of the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

Referring to fig. 8, in a seventh schematic diagram of the chip package structure 100 according to the first set of embodiments of the present application, the chip package structure 100 further includes: four second through portions 13b, wherein two second through portions 13b are respectively disposed on the second upper heat conductive layer 131, and one ends of the two second through portions 13b are respectively connected to the outer surface of the entire chip package structure 100 through the second upper heat conductive layer 131, and the other ends of the two second through portions 13b are respectively connected to the second insertion layer 13a disposed on the second upper heat conductive layer 131.

The other two second through portions 13b are respectively disposed on the second lower heat conductive layer 132, and one ends of the other two second through portions 13b are respectively connected to the outer surface of the entire chip package structure 100 through the second lower heat conductive layer 132, and the other ends of the other two second through portions 13b are respectively connected to the second interposer layer 13a disposed on the second lower heat conductive layer 132.

In this embodiment, the second through portion 13b is added, so that the heat collected in the second heat conducting layer 13 can be more conveniently conducted away from the wafer layer 10. The heat in the second heat conducting layer 13 can be quickly conducted out of the wafer layer 10 along the second through portion 13b, so as to improve the heat conducting effect.

Referring to fig. 9, in an eighth schematic view of a chip package structure 100 according to the first set of embodiments of the present application, a second heat conductive layer 13 is made of a ceramic material. The chip package structure 100 illustrated in fig. 9 further includes: a metal heat sink 16, and a heat-dissipating metal lead 17 connected to the metal heat sink 16. The metal heat sink 16 is disposed outside the second heat conductive layer 13, and the wafer layer 10 is insulated from the metal heat sink 16. The heat dissipating metal lead 17 is connected to the metal lead 11.

In this embodiment, the metal heat sink 16 and the heat dissipation metal lead 17 are added, so that not only the wire bonding (the metal lead 11 is realized) of the wafer layer 10 can be ensured, but also the heat dissipation area can be increased through the metal heat sink 16, and the heat dissipation path can be increased through the heat dissipation metal lead 17.

Fig. 10 is a top view of a chip package structure 100 according to a first set of embodiments of the present application. In fig. 10, a plurality of metal heat sinks 16 are respectively disposed at intervals (each metal heat sink 16 corresponds to one pin of a chip led out from the wafer layer 10), and a plurality of heat dissipation metal leads 17 are respectively led out from the plurality of metal heat sinks 16. In the top view of the chip package structure 100 shown in fig. 10, the metal heat sinks 16 are disconnected, so that electrical connection between the chip pins can be avoided.

Referring to fig. 11, in a first schematic diagram of a chip package structure 100 according to a second set of embodiments of the present application, the chip package structure 100 includes: the first heat conduction layer 12, the second heat conduction layer 13, the sealing layer 14, and the metal lead 11 electrically connected to the wafer layer 10 are disposed on the periphery of the wafer layer 10.

The first heat conductive layer 12 wraps the wafer layer 10 when viewed in a cross section of the chip package structure 100, and the thickness T1 of the wafer layer 10 is 0.4-0.6mm, preferably may be set to 0.5mm. The first heat conductive layer 12 includes a first upper heat conductive layer 121 and a first lower heat conductive layer 122. The metal lead 11 is connected to the wafer layer 10 and led out from a position where the first upper heat conductive layer 121 and the first lower heat conductive layer 122 are in contact, the thickness of the first upper heat conductive layer 121 is T21, the thickness of the first lower heat conductive layer 122 is T22, T22 > T21, and the thickness T21 of the first heat conductive layer 12 is 0.08-0.12mm, preferably may be set to 0.1mm. For example, in one embodiment T21 may be 0.08-0.12mm, preferably 0.1mm, T22 may be 0.2-0.3 mm, preferably 0.24mm.

The second heat conducting layer 13 does not completely wrap the first heat conducting layer 12, the area of the second heat conducting layer 13 covering the first heat conducting layer 12 is greater than 90% of the area of the first heat conducting layer 12, and the thickness T3 of the second heat conducting layer 13 is 0.18-0.22mm, preferably can be set to 0.2mm.

The second heat conductive layer 13 fills the sealing layer 14 at a position where the first heat conductive layer 12 is not completely wrapped, the thickness T4 of the sealing layer 14 is 0.18 to 0.22mm, preferably may be set to 0.2mm, and the diameter of the metal lead 11 is 0.08 to 0.12mm, preferably may be set to 0.1mm. The second heat conductive layer 13 has a heat conductivity greater than that of the first heat conductive layer 12.

In this embodiment, the thicknesses of the first upper heat conductive layer 121 and the first lower heat conductive layer 122 located at both sides of the wafer layer 10 are different, that is, t21+.t22 illustrated in fig. 11, specifically, as shown in fig. 11, the thickness T21 of the first upper heat conductive layer 121 is smaller than the thickness T22 of the first lower heat conductive layer 122, and the specific first upper heat conductive layer 121 and the first lower heat conductive layer 122 are defined only as "upper" or "lower" provided for distinction. In practical applications, the thicknesses of the first upper heat conducting layer 121 and the first lower heat conducting layer 122 are all within the protection scope of the embodiments of the present application. Because, if fig. 11 is rotated 180 ° in a plane, the thickness of the first upper heat conductive layer is greater than the thickness of the first lower heat conductive layer.

In the second group of embodiments of the present application, when t21+.t22 is calculated by the inventor, the heat dissipation effect of the entire chip package structure 100 is more obvious. The method is specifically characterized in that the method comprises the following steps: the thermal conductivity of the chip package structure 100 is calculated according to q=ka (dT/dx). Wherein Q is heat flow, K is heat conductivity coefficient, A is heat transfer area, dT is temperature difference of two sides of the infinitesimal thickness, dx is infinitesimal thickness.

The thickness of the wafer layer 10 to the upper surface of the first upper heat conducting layer 121 is a, the thickness of the wafer layer 10 to the lower surface of the first lower heat conducting layer 122 is b, and the total heat transferred from the wafer layer 10 is qtotal=ka (dT/a) +ka (dT/b) = KAdT [ (a+b)/ab ]. The maximum value of Qtotal, i.e., the maximum value of [ (a+b)/ab ], is the minimum value of ab when a+b is a constant value of C, and the maximum value of Qtotal. ab=a (C-a), and since a is a length value, Q is always maximum when a=0 or a=c. Therefore, when the first heat conductive layers on both sides of the wafer layer are asymmetrically arranged (when t21+.t22, the heat dissipation effect of the entire chip package structure 100 is more obvious), the heat dissipation speed is faster. Specifically, 1.5×t21=t22, 2×t21=t22, 2.5×t21=t22, or other multiple relationship may be set.

In this embodiment, on the basis of the first group of embodiments, the structural arrangement of the first heat conducting layer 12 is further improved, so that the heat conduction efficiency from the wafer layer 10 to the first heat conducting layer 12 is improved, and the heat dissipation effect of the chip package structure 100 is improved. Reference is made in particular to the effect diagram shown in fig. 19. Fig. 19 is a graph showing the chip surface temperature versus time for five chip package structures, respectively. The chip packaging structure shown in fig. 1 adopts the scheme in the prior art, and has poor heat dissipation effect, and the temperature of the surface of the chip reaches more than 85 ℃ after the chip is used for 8-9 minutes, and is kept at 80-90 ℃, so that the service life of the chip is seriously shortened, and the reliability of the chip is reduced. The heat dissipation effects of the symmetrical basic heat dissipation chip package structure shown in fig. 2, the symmetrical upgrade heat dissipation chip package structure shown in fig. 5, the asymmetrical basic heat dissipation chip package structure shown in fig. 11, and the asymmetrical upgrade heat dissipation chip package structure shown in fig. 12 are significantly improved. In particular, the chip surface temperature reaches 55-65 ℃ after the chip is used for 4-5 minutes by adopting the technical scheme of the application, and the chip can be kept at a lower temperature for a long time. Therefore, the whole heat dissipation effect of the chip packaging structure formed by adopting the technical scheme of the application is obviously enhanced.

Referring to fig. 12, in a second schematic diagram of a chip package structure 100 according to a second set of embodiments of the present application, a second heat conductive layer 13 includes: the second upper heat conductive layer 131 contacting the first upper heat conductive layer 121 and the second lower heat conductive layer 132 contacting the first lower heat conductive layer 122, the second upper heat conductive layer 131 has a thickness T31, the second lower heat conductive layer 132 has a thickness T32, T31 > T32, and T32 is 0.08-0.12mm, preferably may be set to 0.1mm. T32 is 0.2-0.3mm, preferably 0.26mm. For example, in one embodiment T32 is 0.1mm and T31 is 0.28mm.

The chip package structure 100 includes: the first interposer layer 12b is disposed on the first lower heat conductive layer 122, the heat conductivity coefficient of the first interposer layer 12b is greater than that of the first heat conductive layer 12, the thickness of the first interposer layer 12b is T5, T22 is greater than or equal to 0.25×t5 and less than or equal to 0.3×t22, and the vertical distance from the first interposer layer 12b to the wafer layer 10 is smaller than the vertical distance from the first interposer layer 12b to the second heat conductive layer 13.

Two first through-holes 12c are provided on both sides of the first insertion layer 12b in the longitudinal direction of the first insertion layer 12b, the two first through-holes 12c are provided in the first lower heat conductive layer 122, respectively, one ends of the two first through-holes 12c are connected to the second lower heat conductive layer 132, respectively, and the other ends of the two first through-holes 12c are connected to the first insertion layer 12b, respectively.

The second insertion layer 13a is disposed on the second upper heat conducting layer 131, the heat conductivity coefficient of the second insertion layer 13a is greater than that of the second heat conducting layer 13, the thickness of the second insertion layer 13a is T6, T31 is greater than or equal to 0.25×t6 and less than or equal to 0.3×t31, and the vertical distance from the second insertion layer 13a to the first heat conducting layer 12 is smaller than the vertical distance from the second insertion layer 13a to the outer edge of the second heat conducting layer 13.

The second through portions 13b are provided on both sides of the second insertion layer 13a in the longitudinal direction of the second insertion layer 13a, the two second through portions 13b are provided in the second upper heat conductive layer 131, respectively, and one ends of the two second through portions 13b are connected to the second upper heat conductive layer 131 in a through manner, respectively, and the other ends of the two second through portions 13b are connected to the second insertion layer 13a in a through manner, respectively.

In this embodiment, on the basis of the first schematic diagrams of the first set of embodiments and the second set of embodiments (on the basis of the asymmetric design of the first upper heat conducting layer 121 and the first lower heat conducting layer 122, and/or the asymmetric design of the second upper heat conducting layer 131 and the first lower heat conducting layer 132), the structural arrangement of the second heat conducting layer 13 is further improved, and the heat conduction efficiency from the first heat conducting layer 12 to the second heat conducting layer 13 is further improved, so as to improve the heat dissipation effect of the chip package structure 100. In the embodiment, when the second upper heat conductive layer 131 and the second lower heat conductive layer 132 are asymmetrically arranged (when t31+.t32, the heat dissipation effect of the entire chip package structure 100 is more obvious), the heat dissipation speed is faster. Similarly, in practical applications, the thicknesses of the second upper heat conductive layer 131 and the second lower heat conductive layer 132 are all within the protection scope of the embodiments of the present application.

Referring to fig. 13, in a third schematic diagram of the chip package structure 100 according to the second embodiment of the present application, the first upper heat conductive layer 121 includes a first upper body portion 121a and two first upper wrapping portions 121b disposed on two sides of the first upper body portion 121a, the first upper heat conductive layer 121 is integrally formed, and the length of the first upper body portion 121a is equal to the length of the wafer layer 10 (the length is L0 as shown in fig. 13). The length L1 of the first upper wrapping portion 121b is 0.08 to 0.12mm, and may be preferably set to 0.1mm.

The first lower heat conducting layer 122 includes a first lower body portion 122a and two first lower wrapping portions 121b respectively disposed on two sides of the first lower body portion 122a, where the first lower heat conducting layer 122 is integrally formed, and the length of the first lower body portion 122a is equal to the length of the wafer layer 10 (the lengths are L0 as shown in fig. 13). The length L1 of the first lower wrapping portion 121b is 0.08 to 0.12mm, and may be preferably set to 0.1mm.

The area of each first lower wrap portion 121b is greater than the area of each first upper wrap portion 121 b.

In this embodiment, on the basis of the asymmetric design of the first upper heat conducting layer 121 and the first lower heat conducting layer 122, and/or the asymmetric design of the second upper heat conducting layer 131 and the first lower heat conducting layer 132, the specific structures of the first upper heat conducting layer 121 and the first lower heat conducting layer 122 are further defined, the preparation process of the chip package structure 100 can be simplified by the heat conducting layers formed integrally respectively, the specific structure size of the heat conducting layers can be closer to the specific structure of the wafer layer 10, and the sealing of the metal leads 11 can be better realized.

Referring to fig. 14, in a fourth schematic diagram of the chip package structure 100 according to the second set of embodiments of the present application, the chip package structure 100 further includes, on a surface of the first heat conductive layer 12 away from the wafer layer 10: two filling layers, namely a first filling layer 151 and a second filling layer 152; the first filling layer 151 is disposed above the first upper heat conductive layer 121, and the second filling layer 152 is disposed below the first lower heat conductive layer 122. (hereinafter, the filling layer may be understood as the first filling layer 151 and/or the second filling layer 152.) and the filling layer is in contact with the first heat conducting layer 12 and the second heat conducting layer 13, respectively, the filling layer has a length L2, L0 < L2 < (l0+2×l1). In this set of embodiments, the structure and location of the filler layer may be set to be consistent with the structure and location in the first set of embodiments.

The first heat conducting layer 12 includes four retaining wall structures 12a, the retaining wall structures 12a are respectively disposed on the two first upper wrapping portions 121b and the two first lower wrapping portions 121b, and the filling layer is respectively in full contact with the first upper body portion 121a and the first lower body portion 122a, and the retaining wall structures 12a are used for limiting the material of the filling layer between the first heat conducting layer 12 and the second heat conducting layer 13. Specifically, the thickness of the two filling layers may be equal or unequal.

In this embodiment, the chip package structure 100 further includes a filling layer and a barrier wall structure 12a based on the asymmetric design of the first upper heat conductive layer 121 and the first lower heat conductive layer 122, and/or the asymmetric design of the second upper heat conductive layer 131 and the first lower heat conductive layer 132. When the first heat conducting layer 12 is a heat conducting silica gel, there are voids on the surface of the heat conducting silica gel, that is, the fine structures such as holes, cracks or protrusions on the surface of the silica gel have an influence on the surface morphology and performance. The filling layer (silicone grease) in this embodiment may be disposed to fill the surface voids of the thermally conductive silica gel (the first thermally conductive layer 12). In addition, because of extrusion phenomenon and thixotropic property of the heat-conducting silicone grease, the filling layer (heat-conducting silicone grease) needs to be limited by the baffle wall structure 12a, and is further completely wrapped by the first heat-conducting layer 12 and the second heat-conducting layer 13.

Referring to fig. 15, in a fifth schematic diagram of a chip package structure 100 according to a second set of embodiments of the present application, the chip package structure 100 further includes: two first interposer layers 12b are disposed within the first upper thermally conductive layer 121 and the first lower thermally conductive layer 122, respectively.

The thermal conductivity of the first interposer layer 12b is greater than that of the first thermal conductive layer 12, the thickness of the first interposer layer 12b is T5, T21 is greater than or equal to 0.25 and less than or equal to T5 and less than or equal to 0.3 and T21, and the vertical distance from the first interposer layer 12b to the wafer layer 10 is less than the vertical distance from the first interposer layer 12b to the second thermal conductive layer 13. If the first heat conductive layer 12 is cut evenly in a direction perpendicular to the thickness direction, the first interposer 12b is located closer to the half of the wafer layer 10 than the first heat conductive layer 12.

Specifically, the thickness of the first interposed layer 12b located in the first lower heat conductive layer 122 may be equal to the thickness of the first interposed layer 12b located in the first upper heat conductive layer 121. The thickness of the first interposed layer 12b in the first lower heat conductive layer 122 may be greater than the thickness of the first interposed layer 12b in the first upper heat conductive layer 121, i.e., the thickness of the first interposed layer 12b in the first lower heat conductive layer 122 may be greater than T5 and less than T22.

In this embodiment, the first interposer 12b with higher thermal conductivity is further inserted into the first thermal conductive layer 12 based on the asymmetric design of the first upper thermal conductive layer 121 and the first lower thermal conductive layer 122, and/or the asymmetric design of the second upper thermal conductive layer 131 and the first lower thermal conductive layer 132. Specifically, the first insertion layer 12b material with higher heat conductivity such as metal particles and metal sheets is added into the heat-conducting silica gel layer to improve the heat dissipation speed. Specifically, the first interposer 12b can reduce the thermal resistance of the first heat conductive layer 12, thereby increasing the heat dissipation speed of the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

Referring to fig. 16, in a sixth schematic view of a chip package structure 100 according to a second set of embodiments of the present application, a second heat conductive layer 13 includes: a second upper heat conductive layer 131 in contact with the first upper heat conductive layer 121 and a second lower heat conductive layer 132 in contact with the first lower heat conductive layer 122, the second upper heat conductive layer 131 having a thickness T31, the second lower heat conductive layer 132 having a thickness T32, T31 > T32. For example, in one embodiment T32 is 0.1mm and T31 is 0.25mm.

The thermal conductivity of the first interposed layer 12b is equal to the thermal conductivity of the second thermal conductive layer 13. It may be provided that the material of the first interposed layer 12b is identical to the material of the second heat conductive layer 13.

In this embodiment, the first through portion 12c is further added on the basis of the asymmetric design of the first upper heat conducting layer 121 and the first lower heat conducting layer 122 and/or the asymmetric design of the second upper heat conducting layer 131 and the first lower heat conducting layer 132, so that the heat collected in the first heat conducting layer 12 can be more conveniently led out to the second heat conducting layer 13. The heat in the first heat conducting layer 12 can be quickly conducted out to the second heat conducting layer 13 along the first through portion 12c, and the heat conducting effect is improved.

Referring to fig. 17, in a seventh schematic diagram of a chip package structure 100 according to a second set of embodiments of the present application, the chip package structure 100 further includes: two second interposed layers 13a are disposed within the second upper and lower heat conductive layers 131 and 132, respectively.

The thermal conductivity of the second interposer layer 13a is greater than that of the second thermal conductive layer 13, the length of the second interposer layer 13a is L3, the length of the second thermal conductive layer 13 is L4, (l0+2χl1) < L3 < L4. The thickness of the second insertion layer 13a is T6, T32 is greater than or equal to 0.25 and less than or equal to 0.3T 32, and the vertical distance from the second insertion layer 13a to the first heat conduction layer 12 is smaller than the vertical distance from the second insertion layer 13a to the outer edge of the second heat conduction layer 13. If the second heat conductive layer 13 is cut evenly in a direction perpendicular to the thickness direction, the second interposed layer 13a is located closer to the half of the first heat conductive layer 12 than the second heat conductive layer 13.

Specifically, the thickness of the second interposed layer 13a located in the second lower heat conductive layer 132 may be equal to the thickness of the second interposed layer 13a located in the second upper heat conductive layer 131. The thickness of the second interposed layer 13a located in the second upper heat conductive layer 131 may be greater than the thickness of the second interposed layer 13a located in the second lower heat conductive layer 132, i.e., the thickness of the second interposed layer 13a located in the second upper heat conductive layer 131 may be greater than T6 and less than T31.

In this embodiment, the second insertion layer 13a with higher thermal conductivity is further inserted into the second thermal conductive layer 13 based on the asymmetric design of the first upper thermal conductive layer 121 and the first lower thermal conductive layer 122, and/or the asymmetric design of the second upper thermal conductive layer 131 and the first lower thermal conductive layer 132. Specifically, graphene material with higher heat conductivity coefficient is added into the metal layer to serve as a second insertion layer, so that the heat dissipation speed is improved. Specifically, the second interposer 13a can reduce the thermal resistance of the second heat conductive layer 13, thereby accelerating the heat dissipation speed of the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

Referring to fig. 18, in an eighth schematic view of a chip package structure 100 according to a second set of embodiments of the present application, the chip package structure 100 further includes: four second through portions 13b, wherein two second through portions 13b are respectively disposed on the second upper heat conductive layer 131, and one ends of the two second through portions 13b are respectively connected to the outer surface of the entire chip package structure 100 through the second upper heat conductive layer 131, and the other ends of the two second through portions 13b are respectively connected to the second insertion layer 13a disposed on the second upper heat conductive layer 131.

In this embodiment, the second through portion 13b is added on the basis of the asymmetric design of the first upper heat conducting layer 121 and the first lower heat conducting layer 122 and/or the asymmetric design of the second upper heat conducting layer 131 and the first lower heat conducting layer 132, so that the heat collected in the second heat conducting layer 13 can be more conveniently led out far from the wafer layer 10. The heat in the second heat conducting layer 13 can be quickly conducted out of the wafer layer 10 along the second through portion 13b, so as to improve the heat conducting effect.

In one embodiment, the metal heat spreader 16 and the heat spreader metal leads 17 added in the first set of embodiments described above in connection with fig. 9 and 10 may also be provided in the chip package structure 100 of the second set of embodiments described in connection with fig. 11-18. The addition of the metal heat spreader 16 and the heat spreader metal leads 17 in the chip package structure 100 of the second group of embodiments shown in fig. 11-18 can ensure the wire bonding (implementation of the metal leads 11) of the wafer layer 10, and can increase the heat dissipation area through the metal heat spreader 16 and increase the heat dissipation path through the heat spreader metal leads 17. The plurality of metal heat sinks 16 are provided at intervals (each metal heat sink 16 corresponds to one pin of the chip led out from the wafer layer 10), and the plurality of heat dissipation metal leads 17 are led out from the plurality of metal heat sinks 16. The metal heat sink 16 is disconnected to avoid electrical connection between the chip pins.

In one embodiment, the present application further provides a method for manufacturing the chip package structure 100, including the following steps:

s01, providing the wafer layer 10, and electrically connecting the wafer layer 10 with the metal lead 11.

S02, the first heat conductive layer 12 is formed on the first surface and the second surface of the wafer layer 10 by dispensing, coating, liquid pouring or lamination. The first heat conductive layer 12 wraps the wafer layer 10 as seen in a cross section of the chip package structure 100. The first thermally conductive layer 12 may be provided as an insulating material, such as thermally conductive silicone. In some embodiments, the first heat conductive layer 12 may include a first upper heat conductive layer 121 and a first lower heat conductive layer 122 (the first upper heat conductive layer 121 and the first lower heat conductive layer 122 may be symmetrical structures, and the first upper heat conductive layer 121 and the first lower heat conductive layer 122 may also be asymmetrical structures). In some embodiments, a filler layer may be disposed on an outer surface of the first thermally conductive layer 12 remote from the wafer layer 10. In some embodiments, a first interposer 12b may be disposed in the first thermally conductive layer 12. In some embodiments, a first through portion 12 may be further disposed in the first heat conductive layer 12, for reducing thermal resistance and improving heat dissipation efficiency.

S03, forming a second heat conducting layer 13 on the outer side of the first heat conducting layer 12 by means of dispensing, coating, liquid pouring or sheet lamination. The second heat conductive layer 13 does not completely encapsulate the first heat conductive layer 12. And the area of the second heat conduction layer 13 covering the first heat conduction layer 12 is more than 90% of the area of the first heat conduction layer 12 itself. The second heat conductive layer 13 may be provided as a metal or ceramic material. In some embodiments, the second thermally conductive layer 13 may include a second upper thermally conductive layer 131 and a second lower thermally conductive layer 132 (the second upper thermally conductive layer 131 and the second lower thermally conductive layer 132 may be symmetrical structures, the second upper thermally conductive layer 131 and the second lower thermally conductive layer 132 may also be asymmetrical structures, in some embodiments, in some embodiments, a second interposer 13a may be disposed in the second heat conductive layer 13, and in some embodiments, a second through portion 13b may be disposed in the second heat conductive layer 13 to reduce thermal resistance and improve heat dissipation efficiency.

S04, forming a sealing layer 14 at a position where the second heat conduction layer 13 does not completely wrap the first heat conduction layer 12. The sealing layer 14 may be provided as an epoxy resin. The sealing layer 14 may seal the metal lead 11, and achieve insulation between the wafer layer 10 and the outside.

In some embodiments, the step may further include S05, forming a plurality of metal heat sinks 16 outside the second heat conductive layer 13 (in this case, the second heat conductive layer 13 is made of a ceramic material). And S06, forming a heat dissipation metal lead 17 at a position where the metal heat sink 16 is close to the metal lead 11. The heat dissipating metal lead 17 is connected to the metal lead 11. The wafer layer 10 is insulated from the metal heat sink 16.

In this embodiment, a method for manufacturing each structure in the two embodiments is provided, so as to form the chip package structure 100 with good heat dissipation performance.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip package structure, comprising: the first heat conduction layer, the second heat conduction layer and the sealing layer are arranged on the periphery of the wafer layer, and the metal lead is electrically connected with the wafer layer;

the heat-conducting layer is characterized in that the first heat-conducting layer wraps the wafer layer, and the thickness T1 of the wafer layer is 0.4-0.6mm;

2. The chip package structure according to claim 1, wherein the first upper heat conductive layer includes a first upper body portion and two first upper package portions separately disposed on two sides of the first upper body portion, the first upper heat conductive layer is integrally formed, and a length of the first upper body portion is equal to a length of the wafer layer; the length L1 of the first upper wrapping part is 0.08-0.12mm;

3. The chip package structure of claim 2, wherein the surface of the first thermally conductive layer remote from the wafer layer further comprises: the two filling layers are respectively a first filling layer and a second filling layer; the first filling layer is arranged above the first upper heat conduction layer, the second filling layer is arranged below the first lower heat conduction layer, the filling layer is respectively contacted with the first heat conduction layer and the second heat conduction layer, the length of the filling layer is L2, L0 is less than L2 < (L0+2) and L1;

4. The chip package structure according to claim 2, further comprising: the two first inserting layers are respectively arranged in the first upper heat conducting layer and the first lower heat conducting layer;

5. The chip package structure of claim 4, wherein the second thermally conductive layer comprises: a second upper heat conductive layer in contact with the first upper heat conductive layer and a second lower heat conductive layer in contact with the first lower heat conductive layer;

6. The chip package structure of claim 5, the chip packaging structure is characterized by further comprising: the two second inserting layers are respectively arranged in the second upper heat conduction layer and the second lower heat conduction layer;

7. The chip package structure of claim 6, the chip packaging structure is characterized by further comprising: the four second through parts are respectively arranged on the second upper heat conduction layers, one ends of the two second through parts are respectively connected to the outer surface of the whole chip packaging structure through the second upper heat conduction layers, and the other ends of the two second through parts are respectively connected with the second insertion layers arranged on the second upper heat conduction layers in a through way;

8. The chip package structure according to any one of claims 1 to 7, wherein the second heat conductive layer is a ceramic material;