CN117276187A - Method for manufacturing through silicon via in semiconductor substrate - Google Patents
Method for manufacturing through silicon via in semiconductor substrate Download PDFInfo
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- CN117276187A CN117276187A CN202210666856.7A CN202210666856A CN117276187A CN 117276187 A CN117276187 A CN 117276187A CN 202210666856 A CN202210666856 A CN 202210666856A CN 117276187 A CN117276187 A CN 117276187A
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- 239000000758 substrate Substances 0.000 title claims abstract description 111
- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 54
- 239000010703 silicon Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 238000009713 electroplating Methods 0.000 claims abstract description 34
- 230000000149 penetrating effect Effects 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 238000007747 plating Methods 0.000 claims description 26
- 238000000926 separation method Methods 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000011135 tin Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 241000724291 Tobacco streak virus Species 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for manufacturing a through silicon via in a semiconductor substrate, which comprises the following steps: forming a plurality of through-hole trenches penetrating from the second main surface to the first main surface of the semiconductor substrate, an end portion of each through-hole trench on the first main surface of the semiconductor substrate being covered with a corresponding through-hole bottom electrode; forming an auxiliary electrode in the side wall of the through hole groove adjacent to the opening; and electroplating a metal plug in the through hole groove through the electroplating electrode. The invention connects the bottom electrode of the through hole to the electroplating electrode through the electrode connecting wire, applies a voltage to the electroplating electrode to electroplate the metal plug in the through hole groove by using the bottom electrode of the through hole as the first seed layer, and further utilizes the auxiliary electrode positioned on the inner side wall near the opening of the through hole groove as the second seed layer in the later stage of electroplating, thereby realizing the filling mode from bottom to top, accelerating the electroplating speed, improving the filling quality of the silicon through hole and reducing the manufacturing difficulty of the silicon through hole.
Description
Technical Field
The present invention relates to the field of fabrication and packaging of semiconductor integrated circuits and microelectromechanical systems, and more particularly to a method of fabricating through silicon vias.
Background
Through-silicon vias are widely used in advanced packaging of semiconductor integrated circuits (Integrated Circuit; ICs) and microelectromechanical systems (Micro Electro Mechanical Systems; MEMS), such as packaging microelectromechanical systems and their driving circuits together in stacks via through-silicon via interconnect structures, with high transmission bandwidth and low transmission delay.
The conventional through silicon via manufacturing process comprises the following steps: deep holes are etched on a substrate, and an electroplating process is performed by utilizing a seed layer deposited in the deep holes in a subsequent step to realize metal filling, but blind holes prepared on a thicker substrate have higher depth-to-width ratio, so that seed layer metal is difficult to uniformly deposit on the side walls of the through holes by a physical sputtering method in the manufacturing process, and meanwhile, metal fillers are difficult to uniformly fill in the through holes with high depth-to-width ratio, so that the realization of high-density through silicon holes on the thicker substrate is challenging. For this purpose, a certain voltage is applied to the bottom electrode of the via hole, so as to realize bottom-up metal filling.
On the other hand, the through hole (via-middle) process technology is used as a main stream technology for manufacturing TSVs, so that the TSVs can be connected with metals in a circuit, multiple interconnection layers do not need to be etched, the process is relatively simple, but the bottom electrode of the through hole is difficult to be connected with electroplating voltage due to devices on the front surface of a substrate, and therefore, in the manufacturing process of the through hole, the lead mode of the bottom electrode is critical. The current lead mode can introduce unnecessary parameters such as parasitic capacitance and the like, and the performance of the circuit is affected.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for fabricating a through silicon via in a semiconductor substrate, which is used for solving the problem that it is difficult to achieve high-efficiency metal filling in the through silicon via with high aspect ratio and parasitic capacitance caused by the lead mode of the bottom electrode in the conventional fabrication process.
To achieve the above and other related objects, the present invention provides a method for fabricating a through silicon via in a semiconductor substrate, comprising the steps of:
providing a semiconductor substrate comprising opposite first and second major faces;
forming a conductive pattern on a first main surface of the semiconductor substrate, the conductive pattern including a plating electrode, an electrode wire, and a plurality of via bottom electrodes, wherein the plurality of via bottom electrodes are electrically connected to the plating electrode through the electrode wire, the plating electrode being at least partially exposed on the first main surface of the semiconductor substrate;
forming a plurality of through-hole trenches penetrating from the second main surface to the first main surface of the semiconductor substrate, each through-hole trench being provided in pairs with a through-hole bottom electrode, and an end portion of each through-hole trench on the first main surface of the semiconductor substrate being covered with a corresponding through-hole bottom electrode;
forming an auxiliary electrode in the side wall of the through hole groove adjacent to the opening;
electroplating a metal plug in the via trench through the electroplating electrode, comprising:
filling metal from bottom to top by using the bottom electrode of the through hole as a first seed layer; subsequently, the first and second heat exchangers are connected,
when the metal filling in the through hole groove is carried out until the metal filling is combined with the auxiliary electrode, the auxiliary electrode is used for carrying out metal filling on a second seed layer;
wherein an end face of the metal plug opposite to the via bottom electrode is not lower than the second main face of the semiconductor substrate.
Optionally, an end surface of the auxiliary electrode, which is close to the bottom electrode of the through hole, is spaced from the second main surface of the semiconductor substrate by a distance of between 10 micrometers and 200 micrometers.
Optionally, the substrate is a silicon substrate, and the silicon substrate is etched by a deep reactive ion etching process to form a plurality of through hole trenches penetrating from the second main surface to the first main surface of the silicon substrate, wherein the aspect ratio of the through hole trenches is between 5:1 and 20:1.
Optionally, the auxiliary electrodes in any two of the via trenches are electrically isolated from each other.
Optionally, a major portion of the electrode wires are distributed in scribe lanes of the semiconductor substrate, and a width of the electrode wires is less than or equal to a width of the scribe lanes, and the manufacturing method further includes: and removing the main part of the electrode connecting wire from the chip during the chip separation processing of the semiconductor substrate along the scribing channel, so as to realize the electrical separation among the plurality of through silicon vias.
Optionally, the manufacturing method further includes: an insulating film is formed to cover the surface of the electrode wiring.
Optionally, the material of the metal plug is an element selected from copper, tungsten, nickel, tin, or gold, or an alloy of the above metals.
Optionally, the cross section of the through hole groove is cylindrical with approximately vertical side walls, conical without sharp, the side walls are arc-shaped or in a central asymmetric shape.
Optionally, the manufacturing method further includes: and processing the end surface of the metal plug, which is far away from the bottom electrode of the through hole, in a chemical mechanical polishing mode so that the polished end surface is basically flush with the second main surface of the semiconductor substrate.
As described above, the method for manufacturing the through silicon via in the semiconductor substrate of the present invention has the following advantages:
the invention provides a method for manufacturing a silicon through hole in a semiconductor substrate, which comprises the steps of connecting a through hole Bottom electrode to an electroplating electrode through an electrode connecting wire, applying a voltage to the electroplating electrode, electroplating a metal plug in a through hole groove by taking the through hole Bottom electrode as a first seed layer, and further utilizing an auxiliary electrode positioned on the inner side wall near an opening of the through hole groove as a second seed layer in the later stage of electroplating, thereby realizing a Bottom-up filling mode, accelerating the electroplating speed, improving the filling quality of the silicon through hole, and reducing the manufacturing difficulty of the silicon through hole and even the manufacturing difficulty of the whole device.
According to the invention, when the chip of the semiconductor substrate is separated along the scribing channel, the main part of the electrode connection wire is removed from the chip, so that on one hand, the performance of the front-side electrical structure of the substrate is ensured, and the adverse effects on the introduction of parasitic capacitance and other parameters caused by the front-side electrical structure of the substrate are reduced, so that the reliability of TSV electrical interconnection can be improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some of the embodiments of the present application.
Fig. 1 is a schematic top view of a through silicon via structure fabricated in accordance with an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a through silicon via structure fabricated in accordance with an embodiment of the invention.
Fig. 3A to 3F are schematic structural diagrams showing steps of a method for fabricating a through silicon via in a semiconductor substrate according to a first embodiment of the invention.
Fig. 4A to 4F are schematic structural views showing steps of a method for fabricating a through silicon via in a semiconductor substrate according to a second embodiment of the invention.
Fig. 5 is a schematic top view of a single chip obtained by the method for fabricating through silicon vias in a semiconductor substrate according to an embodiment of the present invention.
Description of element reference numerals
10. Substrate board
20. Electrical structure
30. Scribing channel
40. Insulating film
50. Conductive pattern
51. Bottom electrode of through hole
52. Electrode wire
53. Electroplating electrode
60. Through hole trench
70. Metal plug
80. Auxiliary electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the fabrication of through-silicon vias, electroplating is one of the common techniques for forming through-silicon via metal fills. The conventional process of electroplating metal filler in the via trench, for example, using a substrate with a through silicon via as an electroplating cathode, can achieve a better metal filling effect. However, when the thickness of the substrate increases to some extent, it becomes difficult to uniformly deposit the seed layer on the sidewall of the via hole, and it is difficult to achieve a seamless metal filling from the bottom of the via hole to the top of the via hole, resulting in the generation of a slotted metal plug in the via hole trench. Therefore, for high density, high aspect ratio through silicon vias on thick substrates, bottom-up high quality metal filling can be achieved by connecting the via bottom electrode to the plating cathode, or applying a certain voltage.
However, in the Via Middle (Via Middle) process technology, since the fabrication process of the through-silicon Via is performed after the integrated circuit front-end fabrication process forms the electrical structure in the device region of the semiconductor substrate, it is necessary to lead the Via bottom electrode to other regions through the wire to achieve the application of a plating voltage to the Via bottom when the metal filler is plated; after the electroplating process is completed, the connection between the bottom electrodes of each through hole needs to be disconnected, so that the performance of the front-side electrical structure of the substrate is ensured.
In order to realize high-efficiency metal filling in a silicon through hole with high aspect ratio, the invention provides a manufacturing method of the silicon through hole in a semiconductor substrate, which comprises the following steps:
providing a semiconductor substrate comprising opposite first and second major faces;
forming a conductive pattern on a first main surface of the semiconductor substrate, the conductive pattern including a plating electrode, an electrode wire, and a plurality of via bottom electrodes, wherein the plurality of via bottom electrodes are electrically connected to the plating electrode through the electrode wire, the plating electrode being at least partially exposed on the first main surface of the semiconductor substrate;
forming a plurality of through-hole trenches penetrating from the second main surface to the first main surface of the semiconductor substrate, each through-hole trench being provided in pairs with a through-hole bottom electrode, and an end portion of each through-hole trench on the first main surface of the semiconductor substrate being covered with a corresponding through-hole bottom electrode;
forming an auxiliary electrode in the side wall of the through hole groove adjacent to the opening;
electroplating a metal plug in the via trench through the electroplating electrode, comprising:
filling metal from bottom to top by using the bottom electrode of the through hole as a first seed layer; subsequently, the first and second heat exchangers are connected,
when the metal filling in the through hole groove is carried out until the metal filling is combined with the auxiliary electrode, the auxiliary electrode is used for carrying out metal filling on a second seed layer;
wherein an end face of the metal plug opposite to the via bottom electrode is not lower than the second main face of the semiconductor substrate.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to fig. 1, which is a schematic top view of a through-silicon via structure obtained by the method for fabricating a through-silicon via in a semiconductor substrate according to the present invention, fig. 2 is a schematic cross-sectional view of the through-silicon via structure along A-A' in fig. 1. As shown in fig. 1 to 2, the present embodiment provides a method for manufacturing a through silicon via in a semiconductor substrate, including: forming a via bottom electrode 51, an electrode wiring 52, and a plating electrode 53 on a first main surface of the semiconductor substrate 10; forming an electrical structure 20 over the via bottom electrode 51; covering the surface of the electrode wire 52 with an insulating film 40; etching a through hole trench 60 in the second main surface of the semiconductor substrate 10; forming an auxiliary electrode 80 on a sidewall of the through-hole trench 60 in the vicinity of an end face of the second main surface; a voltage is applied to the plating electrode 53 to plate the metal plug 70.
After the electroplating of the metal plug 70 is completed, the fabrication method further includes: and (3) chip separation processing is performed on the semiconductor substrate, and the electrode connecting wires 52 are removed from the chip to realize electrical separation among the plurality of through silicon vias.
In one embodiment, the method of making comprises the steps of: 1) Forming a through hole bottom electrode 51, an electrode connection line 52 and a plating electrode 53 on a first main surface of the semiconductor substrate 10, wherein a main part of the electrode connection line is distributed in the inside of the dicing street, and the width of the electrode connection line is smaller than the width of the dicing street; 2) Forming an electrical structure 20 over a first main surface of the semiconductor substrate, the electrical structure 20 including structures such as an Integrated Circuit (IC) and a MEMS device, and covering an insulating film on a surface of the electrode wiring; 3) Etching on the second main surface of the semiconductor substrate to form a plurality of through-hole trenches 60 penetrating from the second main surface to the first main surface of the semiconductor substrate; 4) Forming an auxiliary electrode 80 on the sidewall of the through-hole trench adjacent to the opening; 5) Applying a voltage to the electroplating electrode, and electroplating a metal plug along the penetrating direction of the through hole groove; 6) And (3) chip separation processing of the semiconductor substrate along the scribing channel 30, and removing the electrode connecting wires from the chip to realize electrical separation among the plurality of through silicon vias.
In one embodiment, N via trenches are etched in the second major surface of the semiconductor substrate, where N is a plurality of greater than or equal to 2.
In one embodiment, the via bottom electrode is disposed on both sides of the scribe line along the extending direction of the scribe line.
In one embodiment, forming the conductive pattern on the first major surface of the semiconductor substrate includes: forming a conductive film on a first main surface of the semiconductor substrate by adopting a sputtering method or a vacuum evaporation method; the conductive film is patterned by an etching method, or a lift-off method, to form a conductive pattern 50 on the first main surface of the semiconductor substrate.
In one embodiment, the plating electrodes are uniformly distributed on the semiconductor substrate, the plating electrodes being at least partially exposed on the first major face of the semiconductor substrate.
In one embodiment, after the electrode connection line is formed, an insulating film is formed on the surface of the electrode connection line by a chemical vapor deposition method, so as to prevent the electrode connection line from being exposed on the first main surface.
In one embodiment, after forming the conductive pattern, at step 2), an electrical structure 20 is formed over the first major face of the semiconductor substrate, wherein the electrical structure includes an integrated circuit and a MEMS device.
In one embodiment, at step 2), the insulating film is coated on the surface of the electrode wire by a chemical vapor deposition method.
In one embodiment, the via trench is formed using an etching method including one of a wet etching method and a plasma etching method.
In one embodiment, the via trench 60 is formed using a deep reactive ion etch process, wherein the aspect ratio of the via trench ranges from 5:1 to 20:1.
In one embodiment, the cross section of the through hole groove is cylindrical, without sharp cone, with the side wall being arc-shaped and with the center being asymmetric, which is approximately vertical to the side wall.
In one embodiment, the end face of the auxiliary electrode, which is close to the bottom electrode of the through hole, is separated from the second main surface of the semiconductor substrate by a distance of between 10 micrometers and 200 micrometers, and the auxiliary electrodes in any two through hole grooves are electrically isolated from each other.
In one embodiment, the material of the metal plug is selected from any one of the following metal materials: elemental copper, tungsten, nickel, tin, or gold, or alloys of the foregoing metals.
In one embodiment, the end surface of the metal plug remote from the via bottom electrode is processed by Chemical Mechanical Polishing (CMP) such that the polished end surface is substantially flush with the second major surface.
In one embodiment, after the through silicon via is completed, structures such as IC circuits and MEMS devices are further formed over the first major surface of the semiconductor substrate.
Fig. 3A to 3F are schematic cross-sectional views of structures along A-A' obtained at each stage of the method for fabricating through-silicon vias in a semiconductor substrate according to the first embodiment of the present invention.
As shown in fig. 3A, step 1) is first performed to provide a semiconductor substrate 10; forming a conductive film on a first main surface of the semiconductor substrate by adopting a sputtering deposition method under the room temperature condition; the conductive film is patterned using an etching method or a lift-off (lift-off) process to form a conductive pattern 50 including a plurality of via bottom electrodes 51, electrode lines 52, and plating electrodes 53. The via bottom electrode 51, the electrode wiring 52 and the plating electrode 53 are substantially the same layer of conductive pattern, and each via bottom electrode 51 has an approximate potential. The positions and/or the number of the via bottom electrodes 51 may be appropriately determined according to the through-silicon vias to be formed later so that each via trench is provided in pairs with the via bottom electrode, and the end of the via trench on the first main surface of the semiconductor substrate is covered with the corresponding via bottom electrode.
As shown in fig. 3B, step 2) is then performed to complete the fabrication process of the remaining devices on the first main surface of the semiconductor substrate 10. A major portion of the electrode lines 52 are distributed in the scribe line 30. Step 2) further comprises: the insulating film 40 is coated on the surface of the electrode wire 52 by a chemical vapor deposition method.
As shown in fig. 3C, step 3) is performed, and a via trench 60 is formed by etching from the second main surface to the first main surface of the semiconductor substrate 10. The etching method for forming the via trench 60 includes: spin-coating a photoresist on the second main surface of the semiconductor substrate 10; then, a pattern corresponding to the via trench is defined on the second main surface of the semiconductor substrate 10 through exposure and development operations; etching the second main surface of the semiconductor substrate 10 based on the photoresist developed pattern until the surface of the bottom electrode of the through hole is exposed; finally, the residual photoresist is removed.
As shown in fig. 3D, step 4) is then performed, and an auxiliary electrode 80 is formed in the sidewall of the via trench 60 adjacent to the opening by a sputtering method. Preferably, the end surface of the auxiliary electrode 80 near the bottom electrode of the through hole is spaced apart from the second main surface of the semiconductor substrate by a distance of between 10 micrometers and 200 micrometers.
As shown in fig. 3E, step 5) is then performed to plate the metal plug 70 by applying a voltage to the plating electrode 53, including: filling metal in the via trench 60 from bottom up with the via bottom electrode 51 as a first seed layer; when the metal filling in the through hole trench is performed to be electrically connected with the auxiliary electrode 80 and the auxiliary electrode 80, that is, when the metal filling in the through hole trench is combined with the auxiliary electrode 80 located on the side wall of the through hole trench, the auxiliary electrode 80 is further used as a second seed layer to fill metal, so that a filling mode from bottom to top in the through hole trench as a whole is realized, the manufacturing efficiency and the metal filling quality of the metal plug 70 are improved, and the end face of the formed metal plug 70, which is far away from the bottom electrode of the through hole, is not lower than the second main surface of the semiconductor substrate. After the electroplating of the metal plug 70 is completed, an end surface of the metal plug 70 away from the bottom electrode of the through hole is processed by a chemical mechanical polishing method, and the polished end surface is substantially flush with the second main surface of the semiconductor substrate.
As shown in fig. 3F, step 6) is then performed to perform chip separation processing on the semiconductor substrate 10 along the dicing streets 30; the electrode connection lines 52 in the scribe line 30 are removed from the chip while cutting the scribe line 30, so that electrical separation between the plurality of through-silicon vias is achieved, and the performance of the front-side electrical structure of the substrate is ensured.
As shown in fig. 4A to 4F, a schematic cross-sectional view of a structure along A-A' obtained at each stage of a method for manufacturing a through silicon via in a semiconductor substrate according to a second embodiment of the present invention is shown.
As shown in fig. 4A, step 1) is first performed to provide a semiconductor substrate 10; forming a conductive film on a first main surface of the semiconductor substrate by adopting a sputtering deposition method under the room temperature condition; the conductive film is patterned using an etching method or a lift-off process to form a conductive pattern 50 including a plurality of via bottom electrodes 51, electrode lines 52, and plating electrodes 53. The via bottom electrode 51, the electrode wiring 52 and the plating electrode 53 are substantially the same layer of conductive pattern, and each via bottom electrode 51 has an approximate potential.
As shown in fig. 4B, step 2) is then performed to complete the desired device fabrication process on the first main surface of the semiconductor substrate 10. A major portion of the electrode lines 52 are distributed in the scribe line 30. Step 2) further comprises: the insulating film 40 is coated on the surface of the electrode wire 52 by a chemical vapor deposition method.
Next, step 3) is performed, and a via trench 60 is formed by etching from the second main surface to the first main surface of the semiconductor substrate 10. The step of forming the via trench 60 by the etching method includes: spin-coating a photoresist on the second main surface of the semiconductor substrate 10; then, a pattern corresponding to the via trench is defined on the second main surface of the semiconductor substrate 10 through exposure and development operations; etching the second main surface of the semiconductor substrate 10 based on the photoresist developed pattern until the surface of the bottom electrode of the through hole is exposed; finally, the residual photoresist is removed. The cross section of the via trench may be any shape as long as a substantially bottom-up void-free filling in the via trench can be achieved by the plating method, such as: the cross section of the through hole groove is cylindrical, without sharp cone, with the side wall being arc-shaped or with the center being asymmetric, which is approximately vertical to the side wall. In one example, as shown in fig. 4C, the cross-section of the via trench 60 is conical without a tip.
As shown in fig. 4D, next, step 4) is performed by applying a voltage to the plating electrode 53, and performing plating with the via bottom electrode 51 as a seed layer to fill the metal plug 70 from the bottom up in the via trench so that the end face of the metal plug 70 away from the via bottom electrode is not lower than the second main face of the semiconductor substrate; next, an end surface of the metal plug 70 remote from the via bottom electrode is processed by a chemical mechanical polishing method, the polished end surface being substantially flush with the second main surface of the semiconductor substrate.
As shown in fig. 4E, step 5) is then performed to fill the metal plug 70 in the via trench 60 from the bottom up by applying a voltage to the plating electrode 53, performing plating with the via bottom electrode 51 as a first seed layer; when the metal filling in the via hole trench is performed to be electrically connected with the auxiliary electrode 80, that is, when the metal filling in the via hole trench is engaged with the auxiliary electrode 80 located on the inner side wall near the opening of the via hole trench, the auxiliary electrode 80 is further used as a second seed layer to fill metal, thereby improving the electroplating efficiency and the metal filling quality, and the end surface of the formed metal plug 70, which is far from the bottom electrode of the via hole, is not lower than the second main surface of the semiconductor substrate. After the electroplating of the metal plug 70 is completed, an end surface of the metal plug 70 away from the bottom electrode of the through hole is processed by a chemical mechanical polishing method, and the polished end surface is substantially flush with the second main surface of the semiconductor substrate.
As shown in fig. 4F, step 6) is then performed to perform chip separation processing on the semiconductor substrate 10 along the dicing streets 30; the electrode connection lines 52 in the scribe line 30 are removed from the chip while cutting the scribe line 30, so that electrical separation between the plurality of through-silicon vias is achieved, and the performance of the front-side electrical structure of the substrate is ensured.
As shown in fig. 5, after the chip separation process is completed, a main portion of the electrode wire 52 is removed from the chip, and only a portion of the electrode wire 52 within a single chip remains, thereby reducing the adverse effect of parasitic capacitance introduction on the electrical structure of the front surface of the substrate. The manufacturing method of the through silicon via can reduce the manufacturing difficulty of the MEMS device packaging structure realized by the through silicon via and the TSV, and reduce the overall cost of the device.
The invention provides a micro-machining method, which has the following beneficial effects:
electroplating a metal plug in the through hole groove by using the electroplating electrode and the bottom electrode of the through hole as a first seed layer; when the metal filler in the through hole groove is electrically connected with the auxiliary electrode, the auxiliary electrode is further used as a second seed layer, so that a Bottom-up filling mode is realized, the electroplating rate is also accelerated, and the filling quality of the silicon through hole is improved.
According to the invention, through disconnecting the electrical connection between the through hole electrodes after electroplating is finished, on one hand, the performance of the electrical structure on the front side of the substrate is ensured, and the provided lead mode of the through hole bottom electrode can also reduce adverse effects such as parasitic capacitance parameter introduction and the like on the electrical structure on the front side of the substrate, so that the reliability of TSV electrical interconnection can be improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A method for manufacturing a through silicon via in a semiconductor substrate is characterized by comprising the following steps:
providing a semiconductor substrate comprising opposite first and second major faces;
forming a conductive pattern on a first main surface of the semiconductor substrate, the conductive pattern including a plating electrode, an electrode wire, and a plurality of via bottom electrodes, wherein the plurality of via bottom electrodes are electrically connected to the plating electrode through the electrode wire, the plating electrode being at least partially exposed on the first main surface of the semiconductor substrate;
forming a plurality of through-hole trenches penetrating from the second main surface to the first main surface of the semiconductor substrate, each through-hole trench being provided in pairs with a through-hole bottom electrode, and an end portion of each through-hole trench on the first main surface of the semiconductor substrate being covered with a corresponding through-hole bottom electrode;
forming an auxiliary electrode in the side wall of the through hole groove adjacent to the opening;
electroplating a metal plug in the via trench through the electroplating electrode, comprising:
filling metal from bottom to top by using the bottom electrode of the through hole as a first seed layer; subsequently, the first and second heat exchangers are connected,
when the metal filling in the through hole groove is carried out until the metal filling is combined with the auxiliary electrode, the auxiliary electrode is used for carrying out metal filling on a second seed layer;
wherein an end face of the metal plug opposite to the via bottom electrode is not lower than the second main face of the semiconductor substrate.
2. The method of manufacturing according to claim 1, wherein: the end face of the auxiliary electrode, which is close to the bottom electrode of the through hole, is separated from the second main surface of the semiconductor substrate by 10-200 micrometers.
3. The method of manufacturing according to claim 1, wherein: the substrate is a silicon substrate, and the silicon substrate is etched through a deep reactive ion etching process to form a plurality of through hole grooves penetrating from a second main surface to a first main surface of the silicon substrate, wherein the depth-to-width ratio of the through hole grooves is between 5:1 and 20:1.
4. The manufacturing method according to claim 1 or 2, characterized in that: the auxiliary electrodes in any two through hole trenches are electrically isolated from each other.
5. The method of manufacturing according to claim 1, wherein: the main part of the electrode connecting wire is distributed in the scribing channel of the semiconductor substrate, the width of the electrode connecting wire is smaller than or equal to the width of the scribing channel, and the manufacturing method further comprises the following steps: and removing the main part of the electrode connecting wire from the chip during the chip separation processing of the semiconductor substrate along the scribing channel, so as to realize the electrical separation among the plurality of through silicon vias.
6. The method of manufacturing according to claim 1, further comprising: an insulating film is formed to cover the surface of the electrode wiring.
7. The method of manufacturing according to claim 1, wherein: the material of the metal plug is any one selected from the following metal materials: elemental copper, tungsten, nickel, tin, or gold, or alloys of the foregoing metals.
8. The method of manufacturing according to claim 1, wherein: the cross section of the through hole groove is cylindrical with approximately vertical side walls, has no taper cone shape, and the side walls are arc-shaped or have asymmetric centers.
9. The method of fabricating a through silicon via of claim 1, further comprising: and processing the end surface of the metal plug, which is far away from the bottom electrode of the through hole, in a chemical mechanical polishing mode so that the polished end surface is basically flush with the second main surface of the semiconductor substrate.
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