CN117251103B - Memory device for low latency entry into deep low power consumption state and method therefor - Google Patents
Memory device for low latency entry into deep low power consumption state and method therefor Download PDFInfo
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Abstract
The application provides a memory device and a method thereof for low latency entry into a deep low power consumption state. The provided method comprises the following steps: before the storage device is ready to enter a second power consumption state of the storage device, backing up the first firmware of the control component to the NVM chip and backing up the bootloader to the second memory; and negotiating with the host to cause the physical link to enter a second power consumption state in response to the storage device being ready to enter the second power consumption state of the storage device, wherein in the second power consumption state of the physical link, the first power supply port is powered down and the second power supply port is powered up; and acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, and storing the wake-up data into the second memory, wherein the wake-up data comprises field data of the control component.
Description
Technical Field
The present disclosure relates to the field of storage devices, and in particular, to a method for implementing a storage device, a method for controlling a storage device, a host, an electronic device, and a computer readable storage medium.
Background
Along with the rapid development of the internet, the storage demand of people for data information is continuously improved, and the solid state disk (SSD, solid state drives, also called solid state storage device or storage device) is widely applied because of the advantages of fast read-write speed, low energy consumption, small volume and the like. The schematic structure of the memory device is shown in fig. 1, fig. 1 is a schematic structure of a memory device provided in the prior art, and as shown in fig. 1, the memory device includes: an interface 103, a control unit (also referred to as a master chip) 104, one or more Non-Volatile Memory (NVM) chips 105, and a dynamic random access Memory (DRAM, dynamic Random Access Memory) 110.
The interface 103 may be adapted to exchange data with a host by means of, for example, serial advanced technology attachment (SATA, serial Advanced Technology Attachment), integrated drive electronics (IDE, integrated Drive Electronics), universal serial bus (USB, universal Serial Bus), peripheral component interconnect express (PCIE, peripheral Component Interconnect Express), non-volatile memory standard (NVMe, non-Volatile Memory Express), serial attached SCSI (SAS, serial Attached SCSI), ethernet, fibre channel, etc. The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and DRAM110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of a Field programmable gate array (FPGA, field-programmable gate array), an ASIC (application-specific integrated circuit, application Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process Input/Output (IO) commands. Control unit 104 may also be coupled to DRAM110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.
Wherein the control part 104 may include: a host interface module 201, a host command processing module 202, a storage command processing module 203, a media interface control module 204 (or flash interface controller or flash channel controller), and a storage media management module 205. The schematic structure of the memory device is shown in fig. 2, and fig. 2 is a schematic diagram of a control unit in a memory device according to the prior art. As shown in fig. 2, the host interface module 201 acquires an IO command provided by a host, and generates a storage command to be provided to the storage command processing module 203. The storage commands, for example, access the same size of storage space, e.g., 4KB. The data unit of the data accessed by the corresponding one of the storage commands recorded in the non-volatile memory NVM chip is referred to as a data frame. The physical page records one or more frames of data.
The storage media management module 205 maintains a logical to physical address translation for each storage command. For example, the storage media management module 205 includes a flash translation layer FTL table. For read commands, the storage medium management module 205 outputs the physical address corresponding to the logical address accessed by the storage command, for write commands, the storage medium management module 205 allocates an available physical address thereto, and records the mapping relationship between the logical address accessed by the storage medium management module and the allocated physical address. The storage medium management module 205 also maintains the functions required to manage the non-volatile memory NVM chips, such as garbage collection, wear leveling, etc.
The storage command processing module 203 operates the medium interface control module 204 to issue a storage medium access command to the NVM chip according to the physical address provided by the storage medium management module 205. And the command sent by the storage command processing module 203 to the media interface control module 204 is referred to as a media interface command, and the command sent by the media interface control module 204 to the NVM chip is referred to as a storage media access command. The storage medium access command follows the interface protocol of the NVM chip.
In the related art, according to the NVMe protocol, a host may issue an NVMe management command to a storage device to instruct the storage device to enter a specified power consumption state. Among other things, the NVMe protocol defines a Power State (Power State). The power consumption states include a plurality of levels, e.g., PS0-PS4, each corresponding to a power consumption level of the memory device. In power consumption state PS0, the memory device has the highest performance and the greatest power consumption, while in power consumption state PS4 (commonly referred to as deep low power consumption state), the memory device stops processing IO commands. To reduce power consumption, the storage device also turns off the high speed serial signal transceiver that connects to the host's PCIe interface and places the PCIe link in the L1.2 state while L1.2 is the power consumption state associated with the link as defined by the PCI e protocol at power consumption state PS 4. In the L1.2 state, the PCIe link stops supplying power to the storage device.
Disclosure of Invention
According to the NVMe protocol, the host sends an NVMe management command to the storage device to indicate the storage device to enter a specified power consumption state, when the storage device enters a PS4 power consumption state, the storage device needs to be powered down in a corresponding PCIe link L1.2 state, the storage device can complete entering the PS4 power consumption state after finishing a power down processing flow, and when the storage device exits from the PS4 power consumption state, the storage device needs to complete a power up processing flow. The power-on/power-off process flow of the storage device is relatively time-consuming, for example, when the storage device is powered on, operations such as loading firmware, initializing each component, loading an address mapping table and the like need to be completed; at power-down of the storage device, it is necessary to record the operating state in the NVM. The time for the storage device to process the NVMe management command indicating that it enters the specified power consumption state, and the time after the host requests the storage device to exit from, for example, the PS4 state to be able to start responding to the IO command, have strict requirements, such as 50ms,25ms, etc. The current NVMe protocol does not define the operations required by the storage device to enter or exit a specified power consumption state level. For a solid state disk that uses a PCIe protocol to carry an NVMe protocol, only the power consumption state of a PCIe link, for example, an L1.2 state, is defined in the current PCIe protocol, and the power consumption state PS4 of the NVMe protocol is not involved, and how the storage device enters the L1.2 state and how the storage device exits the L1.2 state is not defined. The time delay jamming of the storage device caused by entering or exiting low power consumption in the non-working state influences the customer experience.
The application provides a method for realizing a storage device, a method for controlling the storage device, a host, an electronic device and a computer readable storage medium, so as to at least solve the problem that in the related art, the storage device is blocked due to time delay caused by entering or exiting a low-power consumption state in a non-working state, so that user experience is reduced. The technical scheme of the application is as follows:
according to a first aspect of embodiments of the present application, there is provided a method implemented by a storage device, the storage device including a control component, an NVM chip, a memory, a first power supply port and a second power supply port, the memory including a first memory and a second memory; when the storage device is in a first power state, the control component, the NVM chip and the memory are powered through the first power port; when the storage device is in a second power supply state, the second memory is powered through the second power supply port, and the first power supply port is powered down; the storage device is connected with the host through a physical link, and the state of the physical link comprises a first power consumption state and a second power consumption state;
the method comprises the following steps:
Backing up the first firmware of the control component to the NVM chip and backing up a bootloader to the second memory before the storage device is ready to enter a second power consumption state of the storage device;
negotiating with the host to enter the physical link into a second power consumption state in response to the storage device being ready to enter the second power consumption state of the storage device, wherein in the second power consumption state of the physical link, the first power supply port is powered down and the second power supply port is powered up; acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, wherein the wake-up data comprises field data of the control component;
storing the wake-up data into the second memory.
Optionally, backing up the first firmware of the control component to the NVM chip and backing up a bootloader to the second memory before the storage device is ready to enter the second power consumption state of the storage device, including:
acquiring first firmware from a NOR flash memory after the storage device is powered on and before the storage device is ready to enter a second power consumption state of the storage device; backing up the first firmware into the NVM chip, wherein the NVM chip is a NAND flash memory; and
And acquiring a boot loader from the NOR flash memory, and backing up the boot loader to the second memory.
Optionally, before the storage device is ready to enter the second power consumption state of the storage device, the method further comprises:
acquiring second firmware from the NOR flash memory, which the control unit uses to access the NVM chip; and backing up the second firmware in the second memory.
Optionally, the method further comprises:
recording a portion or all of the entries of the address mapping table to the NVM chip in response to the memory device being ready to enter a second power consumption state;
checking whether the first firmware of the control component has been backed up to the NVM chip; and
checking whether the boot loader and the second firmware have been backed up to the second memory.
Optionally, the method further comprises:
stopping receiving a command sent by the host to access the storage device according to a storage device interface protocol in response to the first firmware of the control component having been backed up to the NVM chip and the boot loader and the second firmware having been backed up to the second memory;
And backing up control information corresponding to the storage device interface protocol in the control part to the second memory.
Optionally, the physical link is a PCIe link.
Optionally, the method further comprises:
checking whether the control means satisfies a condition to enter a second power consumption state of the storage device;
and if the control component meets the condition of entering the second power consumption state of the storage device, indicating a PCIe controller of the storage device to negotiate with the host to enable the physical link to enter the second power consumption state of the physical link.
Optionally, the method further comprises:
suspending each CPU of the control component in response to receiving a message provided by the PCIe controller indicating that the physical link is to enter a second power consumption state of the physical link;
and supplying power to the second memory through the second power supply port.
Optionally, after storing the wake-up data to the second memory, the method further comprises:
marking that the storage device is in a second power consumption state of the storage device;
powering down the control component, the NVM chip, and the first memory.
Optionally, the method further comprises:
In response to receiving a management command meeting an NVMe protocol sent by a host, determining that a storage device is ready to enter a second power consumption state of the storage device based on the second power consumption state of the storage device indicated by the management command; or (b)
Determining that the storage device is ready to enter a second power consumption state of the storage device based on state information of the storage device itself.
According to a second aspect of embodiments of the present application, there is provided a method of controlling a memory device, the memory device comprising a control component, an NVM chip, a memory, a first power supply port and a second power supply port, the memory comprising a first memory and a second memory; when the storage device is in the first power state, the control component, the NVM chip, and the memory are powered through the first power port; when the storage device is in the second power supply state, the second memory is powered through the second power supply port and powered down through the first power supply port; the storage device is connected with the host through a physical link, and the state of the physical link comprises a first power consumption state and a second power consumption state;
the method comprises the following steps:
And the driver of the host responds to the fact that the storage device enters a second power consumption state of the storage device, the physical link is set in the second power consumption state of the physical link, and the first power supply port is controlled to be powered down and the second power supply port is controlled to be powered up, so that all other devices except the second memory in the storage device are powered down.
According to a third aspect of embodiments of the present application, there is provided a storage device including: a control component, an NVM chip, a memory, a first power port and a second power port, the memory comprising: a first memory and a second memory; when the storage device is in a first power state, the control component, the NVM chip and the memory are powered through the first power port; when the storage device is in a second power supply state, the second memory is powered through the second power supply port and powered down through the first power supply port; the storage device is connected with the host through a physical link, and the state of the physical link comprises a first power consumption state and a second power consumption state; wherein,
The control unit is configured to backup the first firmware of the control unit to the NVM chip and backup a boot loader to the second memory before the storage device is ready to enter a second power consumption state of the storage device;
the control component is further configured to negotiate with the host to enable the physical link to enter a second power consumption state of the physical link in response to the storage device preparing to enter the second power consumption state of the storage device, where in the second power consumption state of the physical link, the first power supply port is powered down, and the second power supply port is powered up; and acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, and storing the wake-up data into the second memory, wherein the wake-up data comprises field data of the control component.
Optionally, before the storage device is ready to enter the second power consumption state of the storage device, the control unit backs up the first firmware of the control unit to the NVM chip and backs up the boot loader to the second memory, including:
acquiring first firmware from a NOR flash memory after the storage device is powered on and before the storage device is ready to enter a second power consumption state of the storage device; backing up the first firmware into the NVM chip, wherein the NVM chip is a NAND flash memory; and
And acquiring a boot loader from the NOR flash memory, and backing up the boot loader to the second memory.
Optionally, the control unit is further configured to obtain, from the NOR flash memory, a second firmware used by the control unit to access the NVM chip before the storage device is ready to enter a second power consumption state of the storage device; and backing up the second firmware in the second memory.
Optionally, the control unit is further configured to record, in response to the storage device preparing to enter a second power consumption state, a part of or all of an entry of an address mapping table to the NVM chip;
checking whether the first firmware of the control component has been backed up to the NVM chip; and
checking whether the boot loader and the second firmware have been backed up to the second memory.
Optionally, the control unit is further configured to stop receiving a command sent by the host to access the storage device according to a storage device interface protocol, in response to the first firmware of the control unit having been backed up to the NVM chip and the boot loader and the second firmware having been backed up to the second memory; and backing up control information corresponding to the storage device interface protocol in the control part to the second memory.
Optionally, the physical link is a PCIe link.
Optionally, the control unit is further configured to check whether the control unit meets a condition of entering a second power consumption state of the storage device; and if the control component meets the condition of entering the second power consumption state of the storage device, indicating a PCIe controller of the storage device to negotiate with the host to enable the physical link to enter the second power consumption state of the physical link.
Optionally, the control unit is further configured to suspend each CPU of the control unit in response to receiving a message provided by the PCIe controller indicating that the physical link is to enter a second power consumption state of the physical link; and supplying power to the second memory through the second power supply port.
Optionally, the control unit is further configured to mark that the storage device is in a second power consumption state of the storage device after storing the wake-up data in the second memory; powering down the control component, the NVM chip, and the first memory.
Optionally, the control unit is further configured to determine, in response to receiving a management command sent by the host and meeting an NVMe protocol, that the storage device is ready to enter a second power consumption state of the storage device based on the second power consumption state of the storage device indicated by the management command; or determining that the storage device is ready to enter a second power consumption state of the storage device based on state information of the storage device itself.
According to a fourth aspect of embodiments of the present application, there is provided a host controlling a storage device, the storage device including a control component, an NVM chip, a memory, a first power supply port and a second power supply port, the memory including a first memory and a second memory; when the storage device is in the first power state, the control component, the NVM chip, and the memory are powered through the first power port; when the storage device is in the second power supply state, the second memory is powered through the second power supply port and powered down through the first power supply port; the storage device is connected with the host through a physical link, and the state of the physical link comprises a first power consumption state and a second power consumption state; wherein,
the host is configured to respond to the second power consumption state of the storage device by using a driver, set the physical link in the second power consumption state of the physical link, and control the first power supply port to be powered down and the second power supply port to be powered up, so that all devices except the second memory in the storage device are powered down.
According to a fifth aspect of embodiments of the present application, there is provided an electronic device, including:
a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the storage device implemented method as described above or the method of controlling a storage device as described above.
According to a sixth aspect of embodiments of the present application, there is provided a computer readable storage medium, which when executed by a processor of an electronic device, enables the electronic device to perform a storage device implemented method as described above or a method of controlling a storage device as described above.
According to a seventh aspect of embodiments of the present application, there is provided a computer program product comprising a computer program or instructions which, when executed by a processor of an electronic device, implement a storage device implemented method as described above or a method of controlling a storage device as described above.
The technical scheme provided by the embodiment of the application at least brings the following beneficial effects:
in this embodiment, before the storage device is ready to enter the second power consumption state of the storage device, the first firmware of the control component is backed up to the NVM chip, and the boot loader is backed up to the second memory; and negotiating with the host to enter a second power consumption state of the storage device in response to the storage device being ready to enter the second power consumption state of the storage device, wherein in the second power consumption state of the physical link, the first power supply port is powered down and the second power supply port is powered up; and acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, and storing the wake-up data into the second memory, wherein the wake-up data comprises field data of the control component. That is, in this embodiment of the present application, before the storage device prepares to enter the second power consumption state of the storage device, the storage device backs up firmware and a boot loader into a static random access memory that is not powered down, and when the storage device prepares to enter the second power consumption state of the storage device, negotiates with the host to make the physical link enter the second power consumption state, obtains wake-up data required by the storage device entering the first power consumption state from the second power consumption state, stores the wake-up data into the second memory, and then orderly executes power-down operation of each hardware module, thereby implementing a low power consumption mode. And when the wake-up is performed, the loader is directly guided from the second memory, so that the wake-up is accelerated. Namely, the method and the device can enable the client to not experience the time delay jamming of the system due to low power consumption of the in-out depth on the premise of reducing the power consumption, and improve the satisfaction degree of the user.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application and do not constitute an undue limitation on the application. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief description will be given below of the drawings that are needed in the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a block diagram of a prior art memory device.
Fig. 2 shows a block diagram of a control unit of a memory device according to the prior art.
Fig. 3 illustrates a flowchart of a method implemented by a storage device according to an embodiment of the present application.
Fig. 4 is a flowchart illustrating a negotiation process between a storage device and a host according to an embodiment of the present application.
Fig. 5 illustrates another flowchart of a negotiation process between a storage device and a host provided in an embodiment of the present application.
Fig. 6 illustrates a block diagram of a storage device provided in an embodiment of the present application.
FIG. 7 illustrates a block diagram of a host controlled storage device provided by an embodiment of the present application.
Fig. 8 illustrates a block diagram of a memory device for implementing deep low power consumption according to an embodiment of the present application.
FIG. 9 illustrates a schematic diagram of a data backup strategy for a storage device to enter and exit a deep low power state in accordance with an embodiment of the present application.
Detailed Description
In order to enable those of ordinary skill in the art to better understand the technical solutions of the present application, the technical solutions of the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
Fig. 3 illustrates a flowchart of an implementation method of a storage device according to an embodiment of the present application, where, as shown in fig. 3, the storage device includes: the memory comprises a first memory and a second memory; when the storage device is in a first power state, the control component, the NVM chip and the memory are powered through the first power port; when the storage device is in a second power supply state, the second memory is powered through the second power supply port, and the first power supply port is powered down; the storage device is connected with the host through a physical link, and the states of the physical link comprise a first power consumption state and a second power consumption state. The method for realizing the storage device comprises the following steps:
step 301: backing up the first firmware of the control component to the NVM chip and backing up a bootloader to the second memory before the storage device is ready to enter a second power consumption state of the storage device;
step 302: negotiating with the host to enter the physical link into a second power consumption state in response to the storage device being ready to enter the second power consumption state of the storage device, wherein in the second power consumption state of the physical link, the first power supply port is powered down and the second power supply port is powered up; acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, wherein the wake-up data comprises field data of the control component;
Step 303: storing the wake-up data into the second memory.
The method for implementing the storage device described in the present application may be applied to a terminal, etc., and the terminal implementation device may be an electronic device such as a storage device, a hard disk, etc., which is not limited herein.
The following describes in detail the specific implementation steps of a method implemented by a storage device according to an embodiment of the present application with reference to fig. 3.
In step 301, the first firmware of the control unit is backed up to the NVM chip and the bootloader is backed up to the second memory before the memory device is ready to enter the second power consumption state of the memory device.
In this step, after the storage device is powered on and before the storage device is ready to enter a second power consumption state of the storage device, a first firmware is obtained from the NOR flash memory, where the first firmware is, for example, a boot loader (BootLoader), a firmware image (FW Img), a configuration image (CFG Img), etc.; backing up the first firmware into the NVM chip, wherein the NVM chip is a NAND flash memory; and obtaining a boot loader (B ootLoader) from the NOR flash memory, and backing up the boot loader to the second memory, wherein the second memory may be SR AM0, and the boot loader backed up to the second memory may be referred to as a low power consumption boot loader (PSBL).
Optionally, the second firmware used by the control unit to access the NVM chip, such as media interface control module firmware, may also be obtained from the NOR flash memory; and backing up the second firmware in the second memory.
In this embodiment, the NVMe protocol defines a Power State (Power State), where the Power State includes multiple levels, for example, PS0-PS4, and the Power states each correspond to a Power consumption level of the storage device. In power consumption state PS0, the memory device has the highest performance and the greatest power consumption, PS1, PS2, and PS3, and so on, while in power consumption state PS4 (also referred to herein as a deep low power consumption state), the memory device stops processing IO commands. In this embodiment, the first power consumption state of the memory device is PS0, PS1, PS2 or PS3, and the second power consumption state is PS4.
In step 302, negotiating with a host to enter a physical link into a second power consumption state in response to the storage device being ready to enter the second power consumption state of the storage device, wherein in the second power consumption state of the physical link, the first power supply port is powered down and the second power supply port is powered up; and acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, wherein the wake-up data comprises field data of a control component.
In the step, when the storage device is ready to enter a second power consumption state of the storage device, the storage device negotiates with the Host to enable the physical link to enter the second power consumption state (namely, L1.2 state), namely, the power consumption management module in the storage device informs the Host interface module that the L1.2 state can be entered, the Host interface module negotiates with a Host (Host), enters the L1.2 state, and informs the power consumption management module of the negotiation result; in the L1.2 state of the physical link, the first power supply port is powered down, and the second power supply port is powered up, at this time, the power consumption management module obtains wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, where the wake-up data is, for example, CPU field data.
In step 303, the wake-up data is stored in the second memory.
In this step, the power consumption management module in the storage device stores the acquired wake-up data in the second memory (i.e. SRAM 0), marks that the storage device is in the second power consumption state (i.e. deep sleep state) of the storage device, and notifies each component of the control component of power failure.
In this embodiment, before the storage device is ready to enter the second power consumption state of the storage device, the first firmware of the control component is backed up to the NVM chip, and the boot loader is backed up to the second memory; and negotiating with the host to enter a second power consumption state of the storage device in response to the storage device being ready to enter the second power consumption state of the storage device, wherein in the second power consumption state of the physical link, the first power supply port is powered down and the second power supply port is powered up; and acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, and storing the wake-up data into the second memory, wherein the wake-up data comprises field data of the control component. That is, in this embodiment of the present application, before the storage device prepares to enter the second power consumption state of the storage device, the storage device backs up firmware and a boot loader into a static random access memory that is not powered down, and when the storage device prepares to enter the second power consumption state of the storage device, negotiates with the host to make the physical link enter the second power consumption state, obtains wake-up data required by the storage device entering the first power consumption state from the second power consumption state, stores the wake-up data into the second memory, and then orderly executes power-down operation of each hardware module, thereby implementing a low power consumption mode. And when the host computer is awakened, the loading program is directly guided from the second memory, handshake information between the host computer interface module and the host computer is restored, and the awakening is accelerated. Namely, the method and the device can enable the client to not experience the time delay jamming of the system due to low power consumption of the in-out depth on the premise of reducing the power consumption, and improve the satisfaction degree of the user.
Optionally, in another embodiment, based on the foregoing embodiment, the method may further include: recording a portion or all of the entries of the address mapping table to the NVM chip in response to the memory device being ready to enter a second power consumption state; checking whether the first firmware of the control component has been backed up to the NVM chip; and checking whether the boot loader and the second firmware have been backed up to the second memory. In this application, the address mapping table includes a plurality of entries, and each entry records a mapping relationship from a logical address to a physical address.
Further, in response to the first firmware of the control component having been backed up to the NVM chip and the boot loader and the second firmware having been backed up to the second memory, ceasing to receive a command sent by the host to access the storage device according to a storage device interface protocol, backing up control information in the control component corresponding to the storage device interface protocol to the second memory.
That is, in this embodiment, when the storage device is ready to enter the second power consumption state, a part of the entries of the address mapping table may be recorded in the NVM chip, for example, the updated entries of the address mapping table may be recorded in the NVM chip, and of course, all the entries of the address mapping table may be recorded in the NVM chip as required, which is not limited in this embodiment. Then, judging whether the first firmware of the control component is backed up to the NVM chip; judging whether the boot loader and the second firmware are backed up to the second memory, if so, stopping receiving a command sent by the host to access the storage device according to a storage device interface protocol; and backing up control information (such as handshake information between a storage device and a host, etc.) corresponding to the storage device interface protocol in the control unit to the second memory.
In this embodiment, before the storage device is ready to enter the second power consumption state (for example, before the storage device enters the deep low power consumption state), it is checked whether the boot loader, the first firmware and the second firmware are already backed up in the corresponding memories, if so, the power-down flow of each component is executed, so that when the boot loader and the firmware thereof are quickly loaded during power-up wakeup, handshake information of the front end and the host is directly restored, and wakeup is accelerated.
Optionally, in another embodiment, based on the foregoing embodiment, the method may further include: checking whether the control means satisfies a condition to enter a second power consumption state of the storage device; if the control component meets the condition of entering the second power consumption state of the storage device, indicating a PCIe controller of the storage device to negotiate with the host to enable the physical link to enter the second power consumption state of the physical link; and suspending the respective CPUs of the control component in response to receiving a message provided by the PCIe controller indicating that the physical link is to enter a second power consumption state of the physical link; and supplying power to the second memory through the second power supply port.
Specifically, it is possible to check whether each of the control parts is in an idle state, and to check whether hardware configuration active state power management (ASPM, active State Power Management) and L1.2 are enabled, and the like. In a processor system, the low power mode of the processor needs to work in concert with the low power mode of the PCIe device to optimize the power consumption of the grooming processor system. In order to obtain a better low power consumption effect, the deep low power consumption mode support of the control unit enables ASPM functions. The ASPM function is a power management system autonomously performed by the PCIe link when the PCIe link is not involved in system software. The low power state (e.g., PS2, PS3, SP 4) depends on the link L1 or L1.2 state to complete the switching of the power state.
In this embodiment, in order to achieve the purpose of reducing latency, it may also be checked whether to cache important data required for waking up, such as firmware images, configuration images, boot loader, media interface control module firmware, etc., whether the firmware images and configuration images have been copied into NAND flash memory, if not cached or if the cached has been invalidated, then cached again, otherwise, not cached again, so as to achieve the purpose of reducing latency.
Optionally, in another embodiment, based on the above embodiment, after storing the wake-up data in the second memory, the method may further include: marking that the storage device is in a second power consumption state of the storage device; powering down the control component, the NVM chip, and the first memory. I.e. the control unit is informed that the components enter the power down flow.
Optionally, in another embodiment, on the basis of the foregoing embodiment, the method further includes: in response to receiving a management command meeting an NVMe protocol sent by a host, determining that a storage device is ready to enter a second power consumption state of the storage device based on the second power consumption state of the storage device indicated by the management command; or determining that the storage device is ready to enter a second power consumption state of the storage device based on state information of the storage device itself.
Referring also to fig. 4 and 5, fig. 4 illustrates a flowchart of a negotiation process between a storage device and a host provided in an embodiment of the present application, for the convenience of those skilled in the art; FIG. 5 is another flow chart illustrating a negotiation process between a storage device and a host provided in an embodiment of the present application;
As shown in fig. 4, the second power consumption state of the storage device is prepared for the storage device, which specifically includes:
step 401: the Host (Host) sends a management command (NVMe Admin command) meeting the NVMe protocol to the storage device based on the NVMe protocol, wherein the management command indicates any one of power consumption levels (such as PS0-PS1-PS2-PS3-PS 4) corresponding to the NVMe protocol; in this embodiment, PS0-PS1-PS2-PS3 are referred to as a first power consumption state, and PS4 is referred to as a second power consumption state, for example, the management command indicates that the power consumption level corresponding to the NVMe protocol is PS4, that is, the storage device is ready to enter the second power consumption state of the storage device.
Step 402: the storage device determines whether to enter the indicated power consumption state according to the power consumption level indicated by the management command in response to receiving the management command meeting the NVMe protocol sent by the host. Such as determining that the storage device is ready to enter a second power consumption state based on the power consumption level indicated by the management command.
Step 403: the power consumption management module in the storage device informs the host command processing module to stop receiving the NVMe command, and after each part enters an idle state, the power consumption management module informs the host interface module in the storage device to start a flow of entering an L1.2 power consumption state;
Step 404: the host interface module in the storage device negotiates with the PCIe controller of the host to enable the physical link to enter a second power consumption state of the physical link, namely, enter a PCIe L1.2 power consumption state, and the Vacc port of the PCIe interface is powered off; the host interface module notifies the power consumption management module to enter an L1.2 power consumption state.
Wherein, the Vacc power-off is host controlled, and the host cuts off the power supply of the Vacc port according to the PCIe protocol in the negotiation process. Optionally, the host interface notifies the power management module to enter the L1.2 power consumption state before or after the Vacc port is powered down. Still alternatively, the storage device includes a backup power source such that after the Vacc port is powered down, the backup power source may provide a short period of power to cause the power management module to process notification of entering the L1.2 power consumption state. The power consumption management module backs up the field data of the control component in response to the notification of entering the L1.2 power consumption state.
Step 405: the power consumption management module backs up wake-up data (i.e. field data of the control unit) required for the storage device to enter the first power consumption state from the second power consumption state into the second memory (i.e. SRAM 0), thereby completing the final state backup.
Step 406: after the power consumption management module finishes the final state backup, notifying each hardware to enter a power-down flow; the storage device enters a deep sleep state.
In this embodiment of the present application, the storage device needs to enter the deep low power consumption state in response to receiving a command (i.e., a deep low power consumption state command) issued by the host based on the NVMe protocol that the storage device is ready to enter the second power consumption state. Before entering the deep low power consumption state, the storage device stores important wake-up data, such as boot loader bootloader (PSBL), medium interface control module firmware and the like, in the SRAM0 area of the static random access memory, then orderly executes power-down work of each hardware, and other modules enter the power-down state in the SRAM0 area which is not powered down in the deep low power consumption state and keep power, so that the power consumption of the storage device is reduced.
As shown in fig. 5, the embodiment shown in fig. 5 is different from the embodiment shown in fig. 4 in that the storage device determines, based on the state information of the storage device itself, that the storage device is ready to enter the second power consumption state of the storage device, that is, the storage device determines that it is required to enter the PS4 power consumption state according to the low power consumption management policy preset by the storage device itself. The method specifically comprises the following steps:
step 501: the storage device needs to enter an L1.2 state according to a low-power consumption management strategy preset by the storage device, a host command processing module in the control part is informed to stop receiving NVMe commands, and after each hardware is idle, the power consumption management module informs a host interface to start a flow of entering the L1.2 power consumption state;
Step 502: the host interface negotiates with a PCIe controller of the host to enable the physical link to enter a second power consumption state of the physical link, namely, enter a PCIe L1.2 power consumption state, and the Vacc port is powered off; the host interface module informs the power consumption management module to enter an L1.2 power consumption state;
step 503: the power consumption management module backs up wake-up data (i.e. field data of the control unit) required for the storage device to enter the first power consumption state from the second power consumption state into the second memory (i.e. SRAM 0), thereby completing the final state backup.
Step 504: and the power consumption management module completes the final state backup and notifies each hardware to enter a power-down flow, and the storage equipment enters a deep sleep state.
In the embodiment of the application, when the storage device needs to enter low power consumption based on a preset policy, the storage device needs to enter a sleep state. Before entering a sleep state, the storage device stores important wake-up data, such as a boot loader, a medium interface control module firmware and the like, in an SRAM0 area of the static random access memory, then orderly executes power-down work of each hardware, only the SRAM0 area which is not powered down is kept powered up in a deep low-power-consumption state, and other modules enter a power-down state to realize a low-power-consumption mode.
Optionally, in an embodiment of the present application, a method for controlling a storage device is further provided, where the storage device includes a control unit, an NVM chip, a memory, a first power supply port and a second power supply port, and the memory includes a first memory and a second memory; when the storage device is in the first power state, the control component, the NVM chip, and the memory are powered through the first power port; when the storage device is in the second power supply state, the second memory is powered through the second power supply port and powered down through the first power supply port; the storage device is connected with the host through a physical link, and the state of the physical link comprises a first power consumption state and a second power consumption state;
the method comprises the following steps: and the driver of the host responds to the fact that the storage device enters a second power consumption state of the storage device, the physical link is set in the second power consumption state of the physical link, and the first power supply port is controlled to be powered down and the second power supply port is controlled to be powered up, so that all other devices except the second memory in the storage device are powered down. Wherein, optionally, the physical link may be a PCIe link.
In this embodiment of the present application, a driver of a master control sets an L1.2 state of a physical link in response to the storage device entering a second power consumption state of the storage device, and controls a first power supply port of the storage device to be powered down and the second power supply port to be powered up, so that all devices except for the second memory in the storage device are powered down. Therefore, the time delay and the blocking condition of the storage device entering the low-power-consumption state are reduced, and the user experience is improved.
It should be noted that, for the sake of simplicity of description, the method embodiments are all described as a series of combinations of actions, but it should be understood by those skilled in the art that the present disclosure is not limited by the order of actions described, as some steps may take place in other order or simultaneously in accordance with the present application. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments and that the acts referred to are not necessarily required in the present application.
Referring also to fig. 6, a block diagram of a storage device according to an embodiment of the present application is shown. As shown in fig. 6, the storage device 600 includes: a control component 601, an NVM chip 602, a memory 603, a first power port 604 and a second power port 605, the memory 603 comprising a first memory 6031 and a second memory 6032; the control component 601, the NVM chip 602, and the memory 603 are powered through the first power port 604 while the memory device is in a first power state; while the storage device is in a second power state, the second memory 6032 is powered through the second power port 605 and the first power port 604 is powered down; the storage device is connected to the host via a physical link 606, the states of the physical link 606 including a first power consumption state and a second power consumption state. In one embodiment, the physical link is a PCIe link, and the NVM chip is a NAND flash memory; the first Memory and the second Memory are the same or different Static Random Access Memories (SRAM), for example, the first Memory may be SRAM1, the second Memory may be SRAM0, etc.
The control unit 601 is configured to backup the first firmware of the storage device to the NVM chip 602 and backup a boot loader to the second memory 6032 before the storage device is ready to enter the second power consumption state of the storage device;
the control unit 601 is further configured to negotiate with the host to enable the physical link to enter a second power consumption state of the physical link in response to the storage device preparing to enter the second power consumption state of the storage device, where the first power supply port 604 is powered down and the second power supply port 605 is powered up in the second power consumption state of the physical link; and acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, and storing the wake-up data into the second memory 6032, wherein the wake-up data comprises field data of the control component.
Optionally, in another embodiment, based on the foregoing embodiment, the controlling means backs up the first firmware of the controlling means to the NVM chip and the boot loader to the second memory before the storage device is ready to enter the second power consumption state of the storage device, including: acquiring first firmware from a NOR flash memory after the storage device is powered on and before the storage device is ready to enter a second power consumption state of the storage device; backing up the first firmware into the NVM chip, wherein the NVM chip is a NAND flash memory; and acquiring a boot loader from the NO R flash memory, and backing up the boot loader to the second memory.
Optionally, in another embodiment, based on the foregoing embodiment, the control unit is further configured to obtain, from the NOR flash memory, a second firmware used by the control unit to access the NVM chip before the storage device is ready to enter the second power consumption state of the storage device; and backing up the second firmware in the second memory.
Optionally, in another embodiment, based on the foregoing embodiment, the control unit is further configured to record, in response to the storage device preparing to enter the second power consumption state, a part of or all of an entry of an address mapping table to the NVM chip; checking whether the first firmware of the control component has been backed up to the NVM chip; and checking whether the boot loader and the second firmware have been backed up to the second memory.
Optionally, in another embodiment, based on the foregoing embodiment, the control unit is further configured to stop receiving a command sent by the host to access the storage device according to a storage device interface protocol, in response to the first firmware of the control unit having been backed up to the NVM chip and the boot loader and the second firmware having been backed up to the second memory; and backing up control information corresponding to the storage device interface protocol in the control part to the second memory.
Optionally, in another embodiment, based on the foregoing embodiment, the physical link in the embodiment of the present application is a PCIe link.
Optionally, in another embodiment, based on the above embodiment, the control unit is further configured to check whether the control unit meets a condition of entering a second power consumption state of the storage device; and if the control component meets the condition of entering the second power consumption state of the storage device, indicating a PCIe controller of the storage device to negotiate with the host to enable the physical link to enter the second power consumption state of the physical link.
Optionally, in another embodiment, the controlling unit is further configured to suspend each CPU of the controlling unit in response to receiving a message provided by the PCIe controller indicating that the physical link is to enter the second power consumption state of the physical link; and supplying power to the second memory through the second power supply port.
Optionally, in another embodiment, the control unit is further configured to, based on the foregoing embodiment, mark the storage device as being in a second power consumption state of the storage device after storing the wake-up data in the second memory; powering down the control component, the NVM chip, and the first memory.
Optionally, in another embodiment, based on the foregoing embodiment, the control unit is further configured to, in response to receiving a management command sent by the host and meeting an NVMe protocol, determine, based on a second power consumption state of the storage device indicated by the management command, that the storage device is ready to enter the second power consumption state of the storage device; or determining that the storage device is ready to enter a second power consumption state of the storage device based on state information of the storage device itself.
Optionally, referring also to fig. 7, a block diagram of a host 701 for controlling a storage device 600 provided in an embodiment of the present application is shown, where the storage device 600 includes a control unit 601, an NVM chip 602, a memory 603, a first power supply port 604 and a second power supply port 605, and the memory 603 includes a first memory 6031 and a second memory 6032; the control component 601, the NVM chip 602, and the memory 603 are powered through the first power port 604 while the memory device 600 is in the first power state; while the storage device 600 is in the second power supply state, the second memory 6032 is powered on through the second power supply port 605 and powered off through the first power supply port 604; the storage device 600 is connected to the host 701 through a physical link 606, where the states of the physical link 606 include a first power consumption state and a second power consumption state; wherein,
The host 701 is configured to respond to the storage device 600 entering a second power consumption state of the storage device 600 by using a driver, set the physical link in the second power consumption state of the physical link, and control the first power supply port 604 to be powered down and the second power supply port 605 to be powered up, so that all devices except the second memory 6032 in the storage device 600 are powered down.
Referring also to fig. 8, a block diagram of a memory device for implementing deep low power consumption according to an embodiment of the present application is shown.
The host is coupled to the storage device through, for example, a PCIe interface. The memory device includes a control component, an NVM chip, and a memory. The memory includes, for example, SRAM0 and SRAM1. Alternatively, SRAM0 and SRAM1 are provided by a single memory circuit, and are distinguished based on the memory space provided. The memory may be integrated inside the control unit or located outside the control unit as a separate memory chip. Still alternatively, the memory device also includes, for example, DRAM and NOR flash. The NVM chip shown in fig. 8 is, for example, NAND flash memory.
The PCIe interface coupling the host and the storage device includes a PCIe protocol defined power port Vacc and an auxiliary power port Vaux. The PCIe interface also includes a #clkreq port that passes a clock signal through a #wake port that passes a Wake signal. The PCIe port also includes a data lane for passing PCIe high speed differential signals.
According to the PCIe protocol, in the L0 power consumption state of the PCIe link, the host supplies power to the storage device through the Vacc port. The power provided by the Vacc port is provided to the control component, NVM chip and memory of the memory device. In the L1.2 power consumption state of the PCIe link, the Vacc port is powered down and the host provides power to the storage device through the Vaux port. According to the embodiment of the application, in the memory device, the power provided by the Vaux port is provided to the SRAM0, so that in the L1.2 power consumption state, although the Vacc port is powered down, the power provided by the Vaux port ensures that the SRAM0 works, and the data stored in the SRA M0 is not lost (while the data stored in the SRAM1 is lost).
The storage device is required to be loaded with firmware when in operation. Firmware is a program running in a processor or media interface control module of the control unit. According to the embodiment of the application, the firmware comprises main firmware running by a processor of the control component and medium interface control module firmware running by the medium interface control module. Firmware stored in NVM chips (NAND flash and NOR flash) is referred to as firmware image. The NVM chip also stores a configuration image and a Bootloader image. Configuration mirroring is used to provide configuration information required for storage. The boot loader is a program executed after the storage device is powered on, for loading firmware and configuring the storage device.
After the storage device is powered up, the control unit first executes a primary boot program (BootROM). The primary boot procedure is, for example, integrated inside the control unit and is executed first after the control unit is powered up. According to an embodiment of the present application, the control component is powered up by Vacc port power, and accordingly the primary boot program (BootROM) detects when it is executing whether the current power up is a normal power up or a power up to exit from the L1.2 power consumption state. For the former, the primary boot program obtains and runs a boot loader image from the NOR flash memory, and the boot loader continues to load a firmware image, wherein in the embodiment, in actual application, the boot loader image and the boot loader refer to the same program file, but the names are different; for the latter, the primary boot program executes a low power boot loader located in SRAM 0. The low power boot loader is a boot loader for exiting from the L1.2 power consumption state. And loading the medium interface control module from the SRAM0 by running a low-power-consumption boot loader, so that the medium interface control module has access to the NAND flash memory. Next, a firmware image is loaded from the NAND flash memory, and CPU field information and NVMe handshake information are acquired from the SRAM 0. At this point, the storage device can respond to the host's NVMe command and complete the exit from the PS4 power consumption state.
According to embodiments of the present application, a boot loader image, a firmware image, and a configuration image are stored in, for example, a NOR flash memory. When the storage device is normally powered on, the primary boot program acquires the boot loader image from the NOR flash memory and runs, and the boot loader continues to load the firmware image. After the storage device is booted, the boot loader image, the firmware image, and the configuration image in the NO R flash are also copied to the NAND flash under control of, for example, the host firmware. Compared with a NOR flash memory, the NAND flash memory has larger read bandwidth, and loading the firmware image and the optional configuration image from the NAND flash memory can complete the loading process more quickly, so that the time required for exiting from the PS4 power consumption state is shortened. Further, when the storage device is to enter the PS4 power consumption state, the task of copying the boot loader image, the firmware image and the configuration image from the NOR flash memory to the NAND flash memory may not be completed, and in order to enter the PS4 power consumption state, it is checked whether the task of copying the boot loader image, the firmware image and the configuration image from the NOR flash memory to the NAND flash memory is completed, and if not, it is waited for the copying task to be completed and then other preparation tasks required for entering the PS4 power consumption state are performed.
According to embodiments of the present application, the request for the storage device to enter the PS4 power consumption state is initiated by the host through, for example, NVMe management commands, or the control unit is initiated based on its own operating conditions. In order to enter the PS4 power consumption state, in addition to completing the work of copying the boot loader image, the firmware image, and the configuration image from the NOR flash memory to the NAND flash memory, the low power consumption boot loader is copied to SRAM0. The low power boot loader is, for example, the same as the boot loader of the NOR flash memory, and its runtime checks whether the memory device is normally powered up or is exited from the PS4 power consumption state, and performs the corresponding operation.
To enter the PS4 power consumption state, the host command processing module is notified that the NVMe command of the host is no longer received, and the NVMe handshake information (e.g., the contents of the NVMe controller registers) is copied to SRAM0. When exiting from the PS4 power consumption state, the working state of the NVMe protocol of the storage device is recovered from the NVMe handshake information in the SRAM0 without implementing an initialization process of the NVMe protocol, thereby shortening the processing time for exiting from the PS4 power consumption state.
Due to the PS4 power consumption state, the control component will power down, and in accordance with some embodiments of the present application, also backup part or all of the address mapping table in the NVM chip. The entries of the address mapping table record the mapping relationship of the logical addresses and the physical addresses of the storage device.
To enter the PS4 power consumption state, it is also necessary to enter the PCIe link into the L1.2 state. For this purpose, it is checked whether the control means fulfill the condition for entering the L1.2 power consumption state of the PCIe link, and if the condition is fulfilled, the PCIe link is brought into the L1.2 state by negotiation with the host by the host interface module (PCIe controller). The host interface module of the host and control component negotiates based on the P CIe protocol and initiates a flow to enter the PCIe link L1.2 state. The host interface module also notifies the host firmware or power management module of the result before determining to enter the L1.2 state. Next, each CPU of the control unit is suspended, each CPU is currently saved in the field to SRAM0, the storage device is marked as PS4 power consumption (i.e., deep sleep state), and the Vaux port is ensured to supply power to SRAM 0. The preparation for entering the PS4 power consumption state is completed, the host interface module enters the L1.2 power consumption state, vacc is powered down, and the storage device enters the PS4 power consumption state. Since the field of each CPU is saved, when exiting from the PS4 power consumption state, by restoring the CPU field, each CPU of the control section is immediately in the field environment before entering the PS4 power consumption state, without other configuration or initialization processes, thereby further shortening the time of exiting from the PS4 power consumption state.
Optionally, the Vacc post-power-down control unit also performs a corresponding power-down process flow. The power down process flow may be accomplished by, for example, prior art power down processing methods or hardware circuitry.
When the storage device is in the PS4 power consumption state, the host can wake up the storage device to enable the storage device to exit the PS4 power consumption state, and respond to the IO command of the NVMe protocol. For example, the host's application need not be aware that the storage device is in P S power consumption state, but accesses the storage device in the usual manner. Also because the application is unaware that the storage device is in the PS4 power consumption state, it expects the storage device to respond to IO commands in a short time (e.g., 25ms to 50 ms), otherwise it would consider the storage device to be malfunctioning. In response to an access to the storage device, the operating system of the host or the storage device driver recognizes that the storage device is in a PS4 power consumption state or its PCIe link is in an L1.2 power consumption state, requests the storage device to exit the PS4 power consumption state by applying a Wake signal to the #wake port of the PCIe interface of the storage device, and/or powering the Vacc port.
For a storage device, power-up flow is initiated upon receiving power from the Vacc port. A primary boot loader (BootROM) of the control component is executed and distinguishes between a normal power up or a power down from PS4 power consumption state by identifying whether there is a flag for the storage device to be in the PS4 power consumption state. If the storage device is to be exited from the PS4 power consumption state, according to embodiments of the present application, the storage device has been prepared for a fast completion of the exit from the PS4 power consumption state, including recording the firmware image and/or the configuration image in the NAND flash memory, recording the low power boot loader, CPU site, NVMe handshake information, and the media interface control module firmware in SRAM 0.
In order to quickly exit from the PS4 power consumption state, according to the embodiment of the present application, the primary boot program gives control of the control unit to the low power consumption boot loader in SRAM 0. Because the low power boot loader is in SRAM0, no further low power boot loader is needed to be loaded from the NVM chip, thereby shortening the exit time from the PS4 power state. The low-power-consumption boot loader loads the firmware of the medium interface control module in the SRAM0 to the medium interface control module of the control part, so that the control part obtains the capability of accessing the NAND flash memory. Next, the low power boot loader loads the firmware image from the NAND flash memory through the media interface control module. Compared with loading the firmware image from the NOR flash memory, the NAND flash memory has larger read bandwidth, so that the loading time of the firmware image is shortened, and the time of exiting from the PS4 power consumption state is shortened. Optionally, the low power boot loader further loads the configuration image from the NAND flash memory through the media interface control module.
Next, the low power consumption boot loader also acquires NVMe handshake information from the SRAM0 for restoring the state of the NVMe protocol controller of the host command processing module, and restores the work sites of the CPUs of the control unit with the CPUs acquired from the SRAM0, and transfers the control right of the control unit to the host firmware. Because the state before the control part enters the PS4 power consumption state (including the recovery of the SQ/CQ according to the NVMe protocol) is restored on site by utilizing the NVMe handshake information in the SRAM0 and the CPU, the control part can continue to enter the work before the PS4 power consumption state without executing the initialization of the NVMe controller, reconstructing the work according to the SQ/CQ of the NVMe protocol and the like, the time for exiting from the PS4 power consumption state is further shortened, and an application program of the host and even an NVMe driver of the host do not need to perceive that the storage device enters the PS4 power consumption state.
The host interface module negotiates with the host to exit from the L1.2 power consumption state. The NVMe IO command corresponding to the access of the host application program to the storage device is sent to the host command processing module. Since the main firmware is already loaded, the host command processing module can work normally to process NVMe IO commands.
Alternatively or further, according to the memory device of the embodiment of the present application, when exiting from the PS4 power consumption state, in order to shorten the time of exiting from the PS4 power consumption state, loading of the address mapping table does not need to be completed. After receiving the N VMe IO command sent by the host, the corresponding portion of the load address mapping table is processed I O according to the logical address accessed by the IO command, so that the delay of the load address mapping table is hidden, and the delay of the load address mapping table is not required to be perceived when exiting from the PS4 power consumption state.
Referring also to FIG. 9, a schematic diagram of a data backup strategy for a storage device to enter and exit a deep low power state according to an embodiment of the present application is shown.
The SRAM0 includes a plurality of memory spaces with designated addresses, denoted as S0, S1, S2, S3, and S4, respectively. In fig. 9, the left downward arrow represents the time lapse direction.
After the storage device is powered on, the firmware image, the configuration image and the boot loader image in the NOR flash memory are copied to the NAND flash memory. The images can be copied so that the memory device can load the images from the NAND flash memory rather than the NOR flash memory when exiting from the PS4 power consumption state, to reduce the time to exit from the PS state by taking advantage of the higher read bandwidth of the NAND flash memory relative to the NOR flash memory. The process of copying the image is time consuming, and may not be completed when the storage device is ready to enter the PS4 power consumption state, and optionally waits for the copying image process to complete reprocessing into other operations of the PS4 power consumption state.
Still alternatively, the storage device undergoes multiple rounds of power up (including normal power up, and power up exiting from the PS4 power consumption state), the copied image may have been recorded in the NAND flash memory. Thus, after the storage device is powered up or ready to enter the PS4 power consumption state, it is also checked whether the copied image is already included in the NAND flash memory and whether the copied image is the latest version image (whether the version of the image in the NOR flash memory is consistent). If the latest version of the image is already included in the NAND flash, the image need not be copied from the NOR flash to the NAND flash. If the image version in the NAND flash is not up to date or has not been copied, then the firmware image, the configuration image and the boot loader image are copied from the NOR flash to the NAND flash.
After the storage device is powered up, during normal operation of the control unit, for example, the host interface module firmware and the host command processing module firmware are in the storage space S1 of the SRAM 0. The CPU of the control part executes the host interface module firmware and the host command processing module firmware to realize the host interface module and the host command processing module. According to the embodiment of the application, in the PS4 power consumption state, the storage space S1 is replaced with the media interface control module firmware. By storing different contents in different power consumption states by the memory space S1, the overall memory capacity required by the memory device is reduced.
During normal operation of the control unit, the low power consumption boot loader may be stored in the memory space S0 of the SRAM0, or data may not be stored. For example, when the storage device does not experience the PS4 power consumption state, the storage space S0 is not written with data; and memory space S0 is written with data after experiencing the PS4 power consumption state. Similarly, the storage spaces S2, S3, and S4 may not store data.
After the storage device is ready to enter the PS4 power consumption state, the storage space S0 is written into the low power consumption boot loader, the storage space S1 is written into the media interface control module firmware, and the storage space S3 is written into the current NVMe handshake information. Before the storage space S1 is written to the media interface control module firmware, the host interface module and the host command processing module are also suspended, so that the storage device no longer receives an NVMe command from the host, and the NVMe controller is in a determined state, and the state of the NVMe controller is backed up by writing current NVMe handshake information to the storage space S3. After the storage space S1 is written into the firmware of the media interface control module, the host interface module and the host command processing module do not work any more. At this time, the CPU site in the storage space S2 has not been updated yet.
After the storage device is ready to enter the L1.2 power consumption state, before the Vacc port is powered down, the C PU is backed up in the field to the storage space S2 with a last time, so that the CPU can participate in the process flow of entering the L1.2 power consumption state. A flag that the memory device is in the PS4 power consumption state is also recorded in the memory space S4. Recording the flag in the PS4 power consumption state at the last moment before entering the L1.2 power consumption state helps to avoid identifying false flags for the memory device in the PS4 power consumption state at power up. If the flag in the PS4 power consumption state is recorded prematurely, and the storage device is powered down before entering the L1.2 state due to other reasons, the flag that the false storage device is in the PS4 power consumption state can be identified when the storage device is powered up.
When the storage device exits from the L1.2 state, the storage device undergoes a power-up procedure. And initiates a procedure to exit from the PS4 power consumption state according to an embodiment of the present application by identifying a flag that the memory device is in the PS4 power consumption state from, for example, memory space S4.
According to the storage device, deep low power consumption can be achieved by entering the L1.2 power consumption state through the PCIe link in the PS4 power consumption state and powering down the Vacc port, and the actually measured power consumption can reach about 2 milliwatts. The system power consumption is saved, the storage equipment can be kept in a low-temperature state, and the problem of excessively fast aging of each device in the storage equipment due to high temperature is solved. Meanwhile, the low-delay scheme provided by the embodiment can enable the client to not perceive the katon experience brought by the system information preparation in the wake-up state.
According to the embodiment of the application, the time delay of the solid-state storage device entering the PS4 power consumption state from the working state can reach less than 18ms, and the time delay of the solid-state storage device exiting from the PS4 power consumption state can reach less than 25ms. For example, for a solid state storage device, the latency requirement for its exit from the PS4 power consumption state is, for example, less than 25ms.
For user experience, when the host computer is a notebook computer in an application scene, the notebook computer is closed by closing an upper cover or a screen, the solid-state storage device is in a PS4 power consumption state, and when a user wakes up the notebook computer by knocking a keyboard or uncaps the notebook computer, the solid-state storage device has finished exiting from the PS4 state within 25ms and can be used as a system disk to respond to a wake-up task of an operating system, and system wake-up and system data recovery are completed in a short time, so that the user feels extremely experienced.
The specific manner in which the various components perform operations in relation to the storage device or host in the above-described embodiments has been described in detail in relation to the embodiments of the method and will not be described in detail herein.
The storage device or host embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
Optionally, an embodiment of the present application further provides an electronic device, including:
a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the storage device implemented method as described above or the method of controlling a storage device as described above.
Optionally, embodiments of the present application further provide a computer readable storage medium, where instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the storage device implemented method described above or the method for controlling a storage device as described above. For example, the computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
Optionally, embodiments of the present application further provide a computer program product comprising a computer program or instructions which, when executed by a processor of an electronic device, cause the electronic device to perform the storage device implemented method shown above or the method of controlling a storage device as described above.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A method implemented by a memory device, wherein the memory device comprises a control component, an NVM chip, a memory, a first power port and a second power port, the memory comprising a first memory and a second memory; when the storage device is in a first power state, the control component, the NVM chip and the memory are powered through the first power port; when the storage device is in a second power supply state, the second memory is powered through the second power supply port, and the first power supply port is powered down; the storage device is connected with the host through a physical link, and the state of the physical link comprises a first power consumption state and a second power consumption state;
the method comprises the following steps:
backing up the first firmware of the control component to the NVM chip and backing up a bootloader to the second memory before the storage device is ready to enter a second power consumption state of the storage device;
Negotiating with the host to enter the physical link into a second power consumption state in response to the storage device being ready to enter the second power consumption state of the storage device, wherein in the second power consumption state of the physical link, the first power supply port is powered down and the second power supply port is powered up; acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, wherein the wake-up data comprises field data of the control component;
storing the wake-up data into the second memory.
2. The storage device implemented method of claim 1, wherein backing up the first firmware of the control component to the NVM chip and backing up a bootloader to the second memory before the storage device is ready to enter the second power consumption state of the storage device, comprising:
acquiring first firmware from a NOR flash memory after the storage device is powered on and before the storage device is ready to enter a second power consumption state of the storage device; backing up the first firmware into the NVM chip, wherein the NVM chip is a NAND flash memory; and
and acquiring a boot loader from the NOR flash memory, and backing up the boot loader to the second memory.
3. The storage device implemented method of claim 2, wherein before the storage device is ready to enter the second power consumption state of the storage device, the method further comprises:
acquiring second firmware from the NOR flash memory, which the control unit uses to access the NVM chip; and backing up the second firmware in the second memory.
4. A storage device implemented method according to any of claims 1 to 3, wherein the method further comprises:
recording a portion or all of the entries of the address mapping table to the NVM chip in response to the memory device being ready to enter a second power consumption state;
checking whether the first firmware of the control component has been backed up to the NVM chip; and
checking whether the boot loader and the second firmware have been backed up to the second memory.
5. The storage device implemented method of claim 4, wherein the method further comprises:
stopping receiving a command sent by the host to access the storage device according to a storage device interface protocol in response to the first firmware of the control component having been backed up to the NVM chip and the boot loader and the second firmware having been backed up to the second memory;
And backing up control information corresponding to the storage device interface protocol in the control part to the second memory.
6. A storage device implemented method according to any of claims 1 to 3, wherein the method further comprises:
checking whether the control means satisfies a condition to enter a second power consumption state of the storage device;
and if the control component meets the condition of entering the second power consumption state of the storage device, indicating a PCIe controller of the storage device to negotiate with the host to enable the physical link to enter the second power consumption state of the physical link.
7. The storage device implemented method of claim 6, wherein the method further comprises:
suspending each CPU of the control component in response to receiving a message provided by the PCIe controller indicating that the physical link is to enter a second power consumption state of the physical link;
and supplying power to the second memory through the second power supply port.
8. A storage device implemented method according to any of claims 1-3, wherein after storing the wake-up data to the second memory, the method further comprises:
Marking that the storage device is in a second power consumption state of the storage device;
powering down the control component, the NVM chip, and the first memory.
9. A storage device implemented method according to any of claims 1 to 3, wherein the method further comprises:
in response to receiving a management command meeting an NVMe protocol sent by a host, determining that a storage device is ready to enter a second power consumption state of the storage device based on the second power consumption state of the storage device indicated by the management command; or (b)
Determining that the storage device is ready to enter a second power consumption state of the storage device based on state information of the storage device itself.
10. A storage device, the storage device comprising: a control component, an NVM chip, a memory, a first power port and a second power port, the memory comprising: a first memory and a second memory; when the storage device is in a first power state, the control component, the NVM chip and the memory are powered through the first power port; when the storage device is in a second power supply state, the second memory is powered through the second power supply port and powered down through the first power supply port; the storage device is connected with the host through a physical link, and the state of the physical link comprises a first power consumption state and a second power consumption state; wherein,
The control unit is configured to backup, before the storage device is ready to enter a second power consumption state of the storage device, a first firmware of the control unit to the NVM chip, and backup a boot loader to the second memory;
the control component is further configured to negotiate with the host to enable the physical link to enter a second power consumption state of the physical link in response to the storage device preparing to enter the second power consumption state of the storage device, where in the second power consumption state of the physical link, the first power supply port is powered down, and the second power supply port is powered up; and acquiring wake-up data required by the storage device to enter the first power consumption state from the second power consumption state, and storing the wake-up data into the second memory, wherein the wake-up data comprises field data of the control component.
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| JP2017194769A (en) * | 2016-04-19 | 2017-10-26 | 株式会社エルイーテック | Device storing information on work ram in non-volatile memory |
| CN113791738A (en) * | 2021-09-16 | 2021-12-14 | 深圳忆联信息系统有限公司 | Normalized low-power-consumption processing method and device based on solid state disk and computer equipment |
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| WO2021087221A1 (en) * | 2019-10-30 | 2021-05-06 | Nix John A | Secure and flexible boot firmware update for devices with a primary platform |
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| JP2017194769A (en) * | 2016-04-19 | 2017-10-26 | 株式会社エルイーテック | Device storing information on work ram in non-volatile memory |
| CN113791738A (en) * | 2021-09-16 | 2021-12-14 | 深圳忆联信息系统有限公司 | Normalized low-power-consumption processing method and device based on solid state disk and computer equipment |
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