CN117254797B - Level shift circuit for quick response of wide working voltage amplitude of DC-DC drive - Google Patents

Abstract

A high-voltage level shift circuit with a wide operating voltage range suitable for DC-DC drive that can be used for level shifting of signals between different power rails, can solve the problem that a high-voltage level shifter cannot transmit signals normally at a low power supply voltage or has a long signal delay time, can ensure fast and reliable flipping of the high-voltage level shifter, and can have a good balance between flipping speed and static power consumption.

Description

A fast-response level shift circuit with wide operating voltage range for DC-DC drive

Technical Field

The present invention relates to the technical field of integrated circuits, and in particular to a level shifting circuit suitable for level shifting of signals between different power rails.

Background technique

In the prior art, in order to meet the application requirements of high-voltage DC-DC converters, some wafer foundries have developed a process suitable for high-voltage power chip design. This process has the characteristics of thin/thick gate oxide layer and higher rated voltage. However, how to solve the problem that the high-voltage level shifter cannot transmit signals normally or the signal delay time is long at low power supply voltage has become a difficult problem.

PVT (process, voltage, temperature) performance is a key factor affecting whether integrated circuits can be successfully mass-produced. P refers to the process deviation in the chip manufacturing process. Between different transistors/wafers/batches, the driving capability of NMOS or PMOS (sometimes also understood as current size or carrier mobility) will change, and the performance of all logic gates will change within the five process corners (ss, ff, sf, fs, tt). V refers to the power supply voltage of the chip. Generally speaking, the higher the voltage, the larger the transistor current and the faster the chip speed. T is the operating temperature of the chip. The effect of temperature on chip performance is relatively complex. It is generally believed that the higher the temperature, the more severe the silicon lattice vibration, the lower the carrier mobility, the lower the transistor saturation current, and the slower the chip. However, this theory is only applicable to non-advanced processes. In advanced processes, the transistor threshold voltage VT and the power supply voltage are very low, making the influence of VT on the logic gate delay more and more important, and VT will increase as the temperature decreases. Therefore, when the temperature drops to a certain level, the influence of VT on the logic gate delay becomes non-negligible, causing the logic gate delay to increase as the temperature decreases. This phenomenon is called temperature inversion.

Chinese patent document CN103856208A records a system for a level shifter, as shown in FIG1 , common-gate NMOS devices M5 and M6 are used together with a low-voltage control block 232 to increase the pull-down driver strength and reduce the competition of the level shifter 230. By using low-voltage devices to implement the low-voltage control block 232, a higher signal strength per unit area can be obtained compared to using high-voltage devices. The low-voltage control block 232 is connected to nodes A and B coupled to the sources of the common-gate transistors M5 and M6, respectively. The inverter 206 coupled to the drain of the PMOS transistor M2 buffers the output of the level shifter 230 as an output signal Dout. The inverter 206 is referenced to the high-voltage power supply VDDH. The cross-coupled NMOS devices M9 and M10 accelerate the voltage switching at nodes A and B via positive feedback in a manner similar to that of the PMOS transistors M1 and M2. The common-gate devices M5 and M6 isolate the high-voltage domain of the PMOS transistors M1 and M2 from the low-voltage control block 232, thereby protecting the low-voltage devices in the low-voltage control block 232 from breakdown and/or damage. When VDDH is low enough so that the common-gate devices M5 and M6 can work safely, the common-gate devices M5 and M6 can also be implemented using low-voltage devices. This situation exists when VDDH is less than twice VDDL. The common-gate devices M5 and M6 are shown as having their gates biased relative to the low-voltage power supply VDDL, but in fact other suitable bias voltages can be used. However, this solution is only suitable for switching between two power supplies (VDDL to VDDH), and is not suitable for level shifting of DC-DC high-end power tube drive signals.

Chinese patent document CN102904565B records a level shift circuit with ultra-low static current for DC-DC drive. As shown in FIG2 , the level shift circuit includes: a first power supply VCC, whose input voltage range is 0V to 6V; a switch node voltage VX, which is a floating ground potential, connected to the common end of the high voltage side and the low voltage side of the DC-DC converter, and whose input voltage range is 0V to 30V; a second power supply VBOOT, which is a bootstrap high voltage power supply of the DC-DC converter, and whose input voltage range is 5V to 35V; the second power supply VBOOT is a voltage formed by superimposing a fixed voltage (e.g. 5V) on the basis of the switch node voltage VX of the DC-DC converter, and VBOOT changes with the switch node voltage VX, and the difference between VBOOT and the switch node voltage VX is always constant within the full output range. The logic input terminal IN is used to receive a logic input signal with a high level of the first power supply VCC and a low level of 0V; and input a level signal to the circuit; the logic output terminal OUT is used to provide a logic output signal with a high level of the second power supply VBOOT and a low level of the third power supply VX. In this scheme, M5 and M6 are high-voltage PMOS. When the voltage of VBOOT-LX (shown in Figure 2) is low, point A may not be able to flip or the flip delay is too large. This is because when the Level Shifter is in a state where point A is high and point B is low, point A can be pulled up to VBOOT through M7. Point B is pulled down to LX+Vgs by M6. When the input signal changes from high to low and you want to pull A down through M5, VGS5=VBOOT-LX. At this time, M7 is in the on state, and VGS7 is VBOOT-LX-Vgs. However, M7 is a low-voltage tube with a small Vth, while M5 is a high-voltage PDEMOS with a large Vth. As point A is pulled down, the pull-down capability of M5 becomes weaker. Under extreme PVT conditions, point A may not be pulled low enough to ensure the subsequent stage flip. Therefore, this solution is suitable for level conversion from low-voltage power supply VCC to VBOOT and switch node LX, but it will encounter problems such as weak driving capability and slow conversion rate under low voltage (VBOOT-LX).

Summary of the invention

In view of the technical problems existing in the prior art, the present invention aims to provide a high-voltage level shift circuit with a wide operating voltage range suitable for DC-DC drive, which can be used for level shifting of signals between different power rails, can solve the problem that a high-voltage level shifter cannot transmit signals normally at a low power supply voltage or the signal delay time is long, can ensure fast and reliable flipping of the high-voltage level shifter, and can have a good balance between flipping speed and static power consumption.

Specifically, according to a first aspect of the present invention, there is provided a high voltage level shift circuit suitable for a wide operating voltage range of a DC-DC drive, characterized in that:

The level shift circuit comprises:

The first power supply VCC,

The switch node VX is connected to the common terminal of the high voltage side and the low voltage side of the DC-DC converter;

The second power supply VBOOT is a bootstrap high voltage power supply for the DC-DC converter. The second power supply VBOOT is a voltage formed by superimposing a fixed voltage on the switching node VX of the DC-DC converter. VBOOT changes with the switching node VX.

The logic input terminal IN is used to receive a logic input signal of the first power supply VCC with a high level, and input a level signal to the circuit;

A logic output terminal OUT, used to provide a logic output signal whose high level is a second power supply VBOOT;

The two capacitors C1 and C2 have their upper plates connected to VCC through switching transistors M5 and M6, respectively, and their lower plates directly connected to the gates of transistors M3 and M4, respectively, for quickly pulling up the gates of transistors M3 and M4 at the moment of switching, so as to open transistors M1 and M2 in a short time for strong pull-down.

Transistors MA and MB use high-voltage NMOS to protect transistors M1 and M2 from voltage breakdown and have high-voltage isolation. Transistors M13 and M14 use low-voltage large-size PMOS. The lower the voltage at points A and B, the stronger the pull-up capability of transistors M13 and M14. At the moment of level shift flipping, the size of PMOS must ensure that the voltage at points A and B is not lower than VBOOT-5V.

The core point of the operation of this circuit is to utilize the capacitor bootstrap characteristics to enhance the pull-down capability of transistor M1 or M2 at the moment of input signal flipping, to ensure smooth flipping of circuit nodes A and B and output under low voltage, and to accelerate the flipping speed.

When the input signal IN is 0, the right branch of the converter in the horizontal direction is observed, and the gates of transistors M8 and M10 become the inverse signal of IN. At this time, M8 and M10 are turned on, and M6 whose source is connected to the first power supply VCC is turned off. The upper and lower plates of capacitor C2 are discharged to 0 through transistors M8 and M10 respectively.

When the input signal IN changes from 0 to 1, observe the right branch. At this time, transistors M8 and M10 change from on to off, and M6 changes from off to on. The first power supply VCC quickly charges the upper plate of capacitor C2 through transistor M6. Since the capacitor has the characteristic of retaining charge, the lower plate of C2 will also be pulled up quickly, so that the pull-down ability of M2 increases rapidly in a short time, ensuring the discharge of point B (the drain of M14 is shown in the figure). Observe the left branch, transistors M7 and M9 change from off to on, capacitor C1 is mainly discharged through M7 and M9, and the gate voltage of M3 has been quickly discharged to close to Vth before the jump. At this time, the current flowing through M1 and M3 is close to 0, and M11 disconnects the weak pull-down of the I1 current source.

At this time, transistor M2 has a strong pull-down current I2, which is mirrored to transistor M16 through transistor M14. The current of transistor M1 is close to 0, and is mirrored to transistor M15 through transistor M13 (in order to ensure fast Level shift flipping, the current difference between the two branches is as large as possible. The current of one branch is close to 0, and the current of the other branch can be designed to be hundreds of uA or even several mA in a short time). The currents of transistors M15, M19 and M21 are all close to 0. The currents of transistors M1 and M2 are mirrored, and finally the currents of transistors M21 and M16 are compared, and a high and low signal of the output voltage is generated.

Since the MOS between VBOOT-LX are all low-voltage PMOS, the operating voltage of the current level shift circuit (between VBOOT-LX) can be very low (about 1 VGS).

In the present invention, additional switch transistors M11, M12 and current sources I1, I2 are constructed, and only one of M11 and M12 is in the on state, in order to ensure a certain state in the steady state.

Take the state where the input signal IN is high as an example,

On the left branch, M1 is disconnected, M11 is disconnected, and there is no pull-down current at point A.

In the right branch, after a delay of a period of time after the flipping moment, the voltage on the lower plate of C2 has been discharged through M4 until M4 is disconnected. At this time, M2 is also disconnected, M12 is turned on, and there is a weak pull-down of I2 at point B. If this weak pull-down of I2 is cancelled, both A and B will be pulled up to VBOOT-Vth, and the output state cannot be determined. Therefore, the weak pull-down of I1 and I2 is essential.

According to the present invention, the bootstrap characteristic of the capacitor is utilized to increase the pull-down capability of the node at the moment of input signal flipping, so as to ensure fast and reliable flipping of the high-voltage level shifter. Thus, the present invention has a good balance between flipping speed and static power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a low-voltage control circuit of a level shifter according to the prior art.

FIG. 2 is a schematic diagram of a level shift circuit related to the prior art.

FIG3 is a schematic diagram of a level shift circuit with a wide operating voltage range and fast response for a DC-DC drive according to a specific embodiment of the present invention.

In the accompanying drawings, M1~M21 represent the first transistor to the twenty-first transistor respectively, C1 and C2 represent the first capacitor and the second capacitor respectively, VIN represents the input terminal voltage, VX represents the switch node voltage, and VSS represents the ground voltage.

Detailed ways

The level shift circuit according to the present invention is described in detail below with reference to the accompanying drawings in combination with specific embodiments. Those skilled in the art will appreciate that the description is exemplary and the present invention is not limited to the specific embodiments.

As shown in FIG3 , a high-voltage level shift circuit with a wide operating voltage range suitable for DC-DC driving according to a specific embodiment of the present invention is shown. The level shift circuit includes:

The first power supply VCC,

The switch node VX is connected to the common terminal of the high voltage side and the low voltage side of the DC-DC converter;

The second power supply VBOOT is a bootstrap high-voltage power supply for the DC-DC converter. The second power supply VBOOT is a voltage formed by superimposing a fixed voltage on the switching node VX of the DC-DC converter. VBOOT changes with the switching node VX. When the high-end power tube between VIN and VX is turned on, VX will quickly jump from 0V to VIN, and when the low-end power tube between VSS and VX is turned on, VX will quickly drop from VIN to a negative voltage, and the voltage value is the current flowing through the low-end power tube multiplied by the on-resistance of the power tube.

The logic input terminal IN is used to receive a logic input signal of the first power supply VCC with a high level, and input a level signal to the circuit;

When the input signal is low,

The NMOS transistors M7 and M9 on the left branch are turned off, the PMOS transistor M5 is turned on, and the upper plate of C1 is charged to VCC through M5. The lower plate can rise to 4~5V (the specific value depends on the design) when M5 is turned on, but as time goes by, the charge on the lower plate of C1 will be discharged through M3 until M3 is turned off. At this time, the lower plate of C1, that is, the gate voltage of M3 is about Vth. Therefore, at this time, M1 is in the off state, M11 is turned on, and I1 has a weak pull-down on the source of MA through M11.

1. The moment the input signal changes from low to high

In the left branch, M7 and M9 are turned on, M5 is turned off, the upper plate of C1 starts to discharge through M7 and M9, the lower plate of C1 discharges through M9, the voltage of the lower plate of C1 is pulled down from Vth to nearly 0V, and M11 is turned off. Therefore, M1 is in the off state at this time, and the weak pull-down of I1 on the source of MA is also disconnected.

In the right branch, M8 and M10 are turned off, and M6 is turned on. At this time, VCC charges the upper plate of C2 through M6. Since the capacitor has the characteristic of maintaining voltage, the voltage of the lower plate of C2 will also rise rapidly. Therefore, M2 is in a strong pull-down state at this time. At the same time, M12 is also turned on, and the weak pull-down of I2 is also in a valid state.

2. After the input signal jumps to high

In the left branch, M7 and M9 are turned on, M11 is turned off, M1 remains off, and the weak pull-down of I1 on the source of MA remains disconnected.

In the right branch, M8 and M10 are disconnected, and M6 is turned on. The upper plate of C2 is still VCC, and the voltage of the lower plate of C2 is discharged through M4 until M4 is turned off. At this time, the voltage of the lower plate of C2 is about Vth. At this time, M2 is in the off state, and the weak pull-down of I2 continues to be in the effective state.

A logic output terminal OUT, used to provide a logic output signal whose high level is the second power supply VBOOT;

The moment the input signal changes from low to high

According to the description of the jump moment, at this time, the left branch M1 is disconnected, I1 is also disconnected by M11, and M2 is in a strong pull-down state.

Observe the circuit between VBOOT and LX. At this time, point A has no pull-down capability and will be pulled up to VBOOT-Vth by M13. At this time, the currents of M13, M15, M17, M19 and M21 are close to 0.

Point B will be strongly pulled down by M2, generating a large current, which will be mirrored through M16, M18, M20 and M21, and finally a current comparison will be generated between M16 and M21, thereby generating the output high and low level signals.

The two capacitors C1 and C2 have their upper plates connected to VCC through switching transistors M5 and M6, respectively, and their lower plates directly connected to the gates of transistors M3 and M4, respectively, for quickly pulling up the gates of transistors M3 and M4 at the moment of switching, so as to open transistors M1 and M2 in a short time for strong pull-down.

Transistors MA and MB use high-voltage NMOS to protect transistors M1 and M2 from voltage breakdown and have high-voltage isolation. Transistors M13 and M14 use low-voltage PMOS, and their diodes are connected in such a way that points A and B can quickly follow the change of VBOOT voltage, so that all devices between VBOOT and LX work within the VBOOT-LX voltage range.

The core point of the circuit is to utilize the bootstrap characteristics of the capacitor to enhance the pull-down capability of the transistor M1 or M2 at the moment of input signal flipping, to ensure smooth flipping of the circuit node LX under low voltage, and to accelerate the flipping speed.

When the input signal IN is 0, the right branch of the converter in the horizontal direction is observed, and the gates of transistors M8 and M10 become the inverse signal of IN. At this time, M8 and M10 are turned on, and M6 whose source is connected to the first power supply VCC is turned off. The upper and lower plates of capacitor C2 are discharged to 0 through transistors M8 and M10 respectively.

When the input signal IN changes from 0 to 1, observe the right branch. At this time, transistors M8 and M10 change from on to off, and M6 changes from off to on. The first power supply VCC quickly charges the upper plate of capacitor C2 through transistor M6. Since the capacitor has the characteristic of retaining charge, the lower plate of C2 will also be pulled up quickly, so that the pull-down ability of M2 increases rapidly in a short time, ensuring the discharge of point B. Observe the left branch, transistors M7 and M9 change from off to on, capacitor C1 is mainly discharged through M7 and M9, the current flowing through M3 is small, and the pull-down ability of M1 is weak. At the same time, M11 disconnects the pull-down of the I1 current source.

At this time, transistor M2 has a strong pull-down current I2, which is mirrored to transistor M16 through transistor M14. Transistor M1 has a weak pull-down current, which is mirrored to transistor M15 through transistor M13. The current of transistor M15 flows into transistor M19 and is mirrored to transistor M21. The currents of transistors M1 and M2 are mirrored, and finally the currents of transistors M21 and M16 are compared, and a high and low signal of the output voltage is generated.

Since the MOS between VBOOT-LX are all low-voltage PMOS, the operating voltage of the current level shift circuit (between VBOOT-LX) can be very low (about 1 VGS).

In the present invention, additional switch transistors M11, M12 and current sources I1, I2 are constructed, and only one of M11 and M12 is in the on state, in order to ensure a certain state in the steady state.

According to the present invention, the bootstrap characteristic of the capacitor is utilized to increase the pull-down capability of the node at the moment of input signal flipping, so as to ensure fast and reliable flipping of the high-voltage level shifter. Thus, the present invention has a good balance between flipping speed and static power consumption.

The present invention is described in detail above with reference to the accompanying drawings in combination with specific embodiments. Those skilled in the art will understand that the description is exemplary and that various modifications and changes may be made thereto. As long as they do not depart from the purpose and spirit of the present invention, these modifications and changes shall fall within the protection scope of the present invention, and the protection scope of the present invention is defined by the appended claims.

Claims (6)

1. A high voltage level shift circuit with a wide operating voltage range suitable for DC-DC driving, the level shift circuit comprising: The first power supply VCC, The switch node VX is connected to the common terminal of the high voltage side and the low voltage side of the DC-DC converter; The second power supply VBOOT is a bootstrap high voltage power supply for the DC-DC converter. The second power supply VBOOT is a voltage formed by superimposing a fixed voltage on the switching node VX of the DC-DC converter, and VBOOT changes with the switching node LX. A logic input terminal IN, used to receive a high level logic input signal of the first power supply VCC and input a level signal to the circuit; A logic output terminal OUT, used to provide a logic output signal whose high level is the second power supply VBOOT; Two capacitors C1 and C2, the upper plates of which are respectively connected to the first power supply VCC through the switching transistors, and the lower plates of which are respectively directly connected to the gates of the third and fourth transistors, are used to quickly pull up the gates of the third and fourth transistors at the moment of switching, so as to realize opening the first and second transistors for strong pull-down in a short time, and utilize the self-bootstrapping characteristics of the capacitor to strengthen the pull-down capability of the first transistor or the second transistor at the moment of input signal flipping, so as to smoothly flip the circuit node under low voltage; The source of the first transistor is connected to the source of the third transistor, and the source of the second transistor is connected to the source of the fourth transistor. 2. The high voltage level shift circuit with a wide operating voltage range suitable for DC-DC drive according to claim 1, characterized in that: When the input signal IN is 0, the gates of the eighth transistor and the tenth transistor of the right branch of the DC-DC converter become the inverse signal of IN. At this time, the eighth transistor and the tenth transistor are turned on, the sixth transistor whose source is connected to the first power supply VCC is turned off, and the upper and lower plates of the second capacitor C2 are discharged to 0 through the eighth transistor and the tenth transistor respectively. 3. The high voltage level shift circuit with a wide operating voltage range suitable for DC-DC driving as claimed in claim 1, characterized in that: When the input signal IN jumps from 0 to 1, the eighth transistor and the tenth transistor of the right branch of the DC-DC converter change from on to off, and the sixth transistor changes from off to on. The first power supply VCC quickly charges the upper plate of the second capacitor C2 through the sixth transistor, and the lower plate of the second capacitor C2 is also quickly pulled up, thereby rapidly increasing the pull-down capability of the second transistor in a short time. 4. The high voltage level shift circuit with a wide operating voltage range suitable for DC-DC driving as claimed in claim 3, characterized in that: The seventh transistor and the ninth transistor of the left branch of the DC-DC converter are turned from off to on, and the first capacitor C1 is discharged through the seventh transistor and the ninth transistor. 5. The high voltage level shift circuit with a wide operating voltage range suitable for DC-DC driving as claimed in claim 4, characterized in that: The second transistor has a strong pull-down current I2 and is mirrored to the sixteenth transistor through the fourteenth transistor. The first transistor has a weak pull-down current and is mirrored to the fifteenth transistor through the thirteenth transistor. 6. The high voltage level shift circuit with a wide operating voltage range suitable for DC-DC driving as claimed in claim 1, characterized in that: It also includes switch transistors M11 and M12 and current sources I1 and I2 , and only one of the switch transistor M11 and the switch transistor M12 is in the on state.