CN117201718A

CN117201718A - HDMI-to-LVDS method and device for realizing video image scaling and cropping based on FPGA

Info

Publication number: CN117201718A
Application number: CN202311007266.4A
Authority: CN
Inventors: 郭伟杰; 谭兴柏; 朱丽虹; 吕毅军; 陈忠; 江芝仲; 高锋淋
Original assignee: Xiamen University
Current assignee: Xiamen University
Priority date: 2023-08-10
Filing date: 2023-08-10
Publication date: 2023-12-08

Abstract

The application provides an HDMI-to-LVDS method and device for realizing video image scaling and cropping based on an FPGA, comprising the following steps: responding to the screen parameters input into the display screen through the serial port or the keys, inputting the screen parameters to the FPGA, and outputting the screen parameters to the nixie tube for displaying; the video source outputs HDMI signals to the FPGA, video signal decoding is carried out on the FPGA, and tmds signals are decoded into RGB888 signals; the signal passes through an image processing module, and RGB888 video signal is scaled in the same proportion by adopting a bilinear scaling circuit; the cut video signal passes through a DDR3_TOP module and is buffered by adopting a ping-pong mode; and finally, converting the video signal into an LVDS differential signal according to the resolution time sequence of the display through the LCD control module, and displaying the LVDS differential signal on a display screen. The technical scheme of the application brings various beneficial effects in aspects of multi-resolution adaptation capability, high-quality image processing, simple and easy-to-use operation mode, cost effectiveness and the like, and provides better use experience and wider application scenes for users.

Description

HDMI-to-LVDS method and device for realizing video image scaling and cropping based on FPGA

Technical Field

The application belongs to the technical field of video signal processing, and particularly relates to an HDMI-to-LVDS method and device for realizing video image scaling and clipping based on an FPGA.

Background

Video signal processing techniques have been continuously developed. With the popularization of high-definition video, the processing requirements of the video signals by modern display technology are increasing. Among them, HDMI and LVDS technologies are two important video signal transmission technologies. However, due to the incompatibility between these two technologies, an efficient conversion scheme is needed to achieve interworking between them. The conventional HDMI-to-LVDS technology is mainly implemented based on an ASIC or a single chip microcomputer, and has many limitations, such as only supporting a specific resolution and a screen size, and cannot adapt to different resolutions and screen sizes, so a new conversion scheme is needed to solve these problems.

Currently, some technical schemes for converting HDMI into LVDS exist in the market, wherein some schemes are realized based on an ASIC or a singlechip, and other schemes are realized based on an FPGA.

The ASIC or single chip solutions of the prior art generally have a simple circuit structure that can accommodate some fixed resolution and screen size. However, they cannot cope with the demands of different resolutions and screen sizes, and thus a plurality of different products are required to accommodate the different demands. In addition, due to ASIC or single chip limitations, their scaling algorithms are often inflexible and do not allow high quality image processing. At the same time, they also require complex settings and adjustments to achieve adaptation.

In addition, the FPGA-based prior art may provide greater flexibility and processing power, and may accommodate more resolution and screen size. However, they use only clipping techniques to adapt to display resolution, and do not combine the two techniques of zoom clipping, the display range may be too small. In addition, since the design and debugging of the FPGA requires relatively complex techniques and tools, the development cost thereof is high.

In view of this, it is very significant to provide an HDMI-to-LVDS method and device for implementing video image scaling clipping based on FPGA.

Disclosure of Invention

In order to solve the defects and shortcomings of the HDMI-LVDS scheme in the prior art in adapting to different resolutions and screen sizes, processing image quality, cost and the like, and more efficient and flexible technology is needed to solve the problems, the application provides an HDMI-LVDS method and device for realizing video image scaling and cropping based on an FPGA, provides an efficient and flexible HDMI-LVDS scheme, realizes same-scale scaling and cropping by using the FPGA, and can adapt to different resolutions and screen sizes so as to solve the technical defects.

In a first aspect, the present application provides a method for converting HDMI to LVDS for implementing scaling and cropping of video images based on FPGA, the method comprising the steps of:

responding to the screen parameters input into the display screen through the serial port or the keys, inputting the screen parameters to the FPGA, and outputting the screen parameters to the nixie tube for displaying;

the video source outputs HDMI signals to the FPGA, video signal decoding is carried out on the FPGA, and tmds signals are decoded into RGB888 signals;

the signals pass through an image processing module, the RGB888 video signals are subjected to scaling processing in the same proportion by adopting a bilinear scaling circuit, the scaling factors and the scaled resolution are obtained by a parameter calculation module, and the scaled video signals need to recalculate XY coordinates, so that the clipping part is convenient to clip the resolution consistent with that of the LVDS display;

the cut video signal passes through a DDR3_TOP module and is buffered by adopting a ping-pong mode;

and finally, converting the video signal into an LVDS differential signal according to the resolution time sequence of the display through the LCD control module, and displaying the LVDS differential signal on a display screen.

Preferably, the video source outputs an HDMI signal to the FPGA, the video signal decoding is performed on the FPGA, and the decoding of the tmds signal into the RGB888 signal specifically further includes:

converting the incoming serial differential data into serial single-ended data by using a serial-parallel conversion module in the HDMI decoding module, and then converting the serial single-ended data into 10bit parallel data;

comparing the 10bit parallel data with 4 control characters by using a word alignment calibration module, if the control characters can be detected continuously at 16 delay values, considering that the range of the delay values is found, and taking the middle delay value as a final value at the moment to indicate that the calibration is completed;

the data of the red, green and blue groups are synchronized by utilizing a data synchronization module, so that the color deviation of an image is prevented;

and converting the parallel 10-bit data into 8-bit data by using an 8b/10b decoding module, and simultaneously generating a line field signal and data valid enabling.

Further preferably, the image processing module specifically includes two parts of video scaling and video cropping:

the video scaling part adopts bilinear interpolation algorithm to scale input video signals in the same proportion, firstly uses FIFO1 to buffer one line of data, then sequentially stores the data into RAM 1/RAM 2, stores two lines of video signals and then carries out linear interpolation, and then buffers the calculated data into RAM3 as a numerical value after line interpolation; secondly, linear interpolation is carried out on the numerical value in the row direction, the result is the numerical value which is scaled finally, and the numerical value is cached in the FIFO2;

and the video clipping part calculates boundary coordinates of the scaled video signal, wherein the upper boundary coordinates are obtained by subtracting the field resolution of the LVDS screen from the field resolution of the scaled video signal and dividing the field resolution by 2, and the other boundaries are obtained by adopting a similar calculation method.

Preferably, the method further comprises: the EDID reading module is used for communicating with the input source to tell the input source of parameters of the required performance of the monitor, wherein the parameters comprise manufacturer information, the name and serial number of the display, a list of all supported resolutions, color settings and preset values of the manufacturer.

Preferably, the screen parameters of the display screen comprise line synchronization, field synchronization, display trailing edge, display area, display leading edge and display period.

In a second aspect, an embodiment of the present application further provides an apparatus for implementing HDMI-to-LVDS conversion for video image scaling clipping based on an FPGA, where the apparatus includes:

the HDMI input interface module is configured to be used for connecting an I2C bus of HDMI to the FPGA by an interface part and transmitting EDID information; the hot plug pin needs to be connected to the tristate gate and then connected to the FPGA, and a hot plug signal is transmitted;

the FPGA chip module is configured to receive LCD screen parameter data transmitted by the serial port or the key, and the screen parameter data is displayed on the nixie tube; the analyzed video data is transmitted to an FPGA chip, and the FPGA chip is responsible for scaling and cutting the video data in the same proportion; by adopting bilinear interpolation algorithm, the FPGA can scale the input video signal and cut the video signal to adapt to displays with different resolutions;

the LVDS output interface module is configured to transmit LVDS differential signals to the FPC_40pin connector by the FPGA, so that the signals can be stably transmitted;

the control module is configured to receive external instructions or key inputs to adjust the output resolution, can receive instructions of users through the serial port or key interface, and adjust processing parameters of the FPGA according to the instructions so as to realize the output of different resolutions.

Further preferably, the method further comprises:

the LVDS screen parameter module is configured to receive LVDS screen parameter information transmitted by a serial port or a key, comprises row synchronization, field synchronization, display trailing edge, display area, display leading edge and display period, and is displayed on a nixie tube;

the EDID reading module is configured to be responsible for communication with an input source, and is used for telling the input source monitor of parameters of required performance, including manufacturer information, names and serial numbers of displays, all supported resolution lists, color settings, manufacturer preset values and other information;

the HDMI decoding module is configured to include a serial-to-parallel conversion module for converting incoming serial differential data into serial single-ended data and then converting the serial single-ended data into 10-bit parallel data; the word alignment calibration module compares the 10bit parallel data with 4 control characters, if the control characters can be detected continuously at 16 delay values, the range of the delay values is considered to be found, and the middle delay value is taken as a final value at the moment to indicate that the calibration is completed; the data synchronization module synchronizes the data of the red, green and blue groups to prevent the color deviation of the image; converting the parallel 10bit data into 8bit data by using an 8b/10b decoding module, and simultaneously generating a line field signal and data effective enabling;

the image processing module is configured to include two parts of video scaling and video clipping, and adopts a bilinear interpolation algorithm to scale an input video signal in the same proportion, and calculates boundary coordinates of the scaled video signal.

Further preferably, the method further comprises:

the parameter calculation module is configured to calculate a scaling factor, a ddr3 read-write burst length and a maximum read-write address which are needed by the video scaling module, and calculate a scaled screen parameter;

the LCD control module is configured to include LCD display time sequence control, a serial-parallel conversion module and an LVDS differential signal conversion module, read RGB888 data cached by DDR3 and convert the RGB888 data into LVDS25 signals.

In a third aspect, an embodiment of the present application provides an electronic device, including: one or more processors; and storage means for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement the method as described in any of the implementations of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in any of the implementations of the first aspect.

Compared with the prior art, the application has the beneficial effects that:

(1) The application provides an HDMI-to-LVDS scheme which uses an FPGA to realize scaling and clipping in the same proportion, and can adapt to different resolutions and screen sizes and process high-quality image signals; the scheme can be set and adjusted through serial ports or keys, and is simple to operate and flexible to use; the application can effectively improve the adaptability and the image processing capability of HDMI to LVDS, and provides better use experience and wider application range for users.

(2) The application adopts the same-proportion scaling and cutting technology realized by the FPGA, and can adapt to screens with different resolutions; the user can adjust through the serial port or the key to realize flexible control of the output resolution; the method can be widely applied to various scenes with different resolution requirements, provides greater application flexibility, and has multi-resolution adaptation capability.

(3) The application adopts bilinear interpolation algorithm to realize scaling in the same proportion, can keep the definition and detail of the image, and improves the quality of image processing; by the clipping function, the application can adapt the images to displays with different proportions, maintain the correct proportion of the images, avoid the deformation or distortion of the images and has high-quality image processing capability.

(4) The application adopts a serial port or key control mode through a simple and easy-to-use operation mode, so that a user can conveniently set and adjust the output resolution; the simple and easy-to-use operation mode not only improves the use convenience of the user, but also reduces the complexity of operation and the learning cost of the user.

(5) The application adopts the FPGA as the core processor, so that the high-efficiency image processing can be realized with lower cost; compared with the traditional hardware scheme, the application has lower cost and greater flexibility and expandability.

(6) The technical scheme of the application brings various beneficial effects in aspects of multi-resolution adaptation capability, high-quality image processing, simple and easy-to-use operation mode, cost effectiveness and the like, and provides better use experience and wider application scenes for users.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain the principles of the application. Many of the intended advantages of other embodiments and embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

Fig. 1 is a flowchart of a method for implementing HDMI-to-LVDS video image scaling clipping based on an FPGA according to an embodiment of the present application;

fig. 2 is a block diagram of an HDMI-to-LVDS system in an HDMI-to-LVDS method for implementing video image scaling clipping based on an FPGA according to an embodiment of the present application;

fig. 3 is a schematic diagram of video processing in an HDMI-to-LVDS method for implementing video image scaling clipping based on an FPGA according to an embodiment of the present application;

fig. 4 is a schematic diagram of a video scaling circuit in an HDMI-to-LVDS method for implementing video image scaling clipping based on an FPGA according to an embodiment of the present application;

fig. 5 is a schematic diagram of video cropping in an HDMI-to-LVDS method for implementing video image scaling cropping based on an FPGA according to an embodiment of the present application;

fig. 6 is a block diagram of HDMI-to-LVDS structure in an HDMI-to-LVDS device for implementing video image scaling clipping based on an FPGA according to an embodiment of the present application;

fig. 7 is a schematic diagram of an HDMI-to-LVDS device for implementing video image scaling clipping based on an FPGA according to an embodiment of the present application.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. For this, directional terms, such as "top", "bottom", "left", "right", "upper", "lower", and the like, are used with reference to the orientation of the described figures. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized or logical changes may be made without departing from the scope of the present application. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

The conventional HDMI-to-LVDS scheme has some problems, such as incapability of adapting to different resolutions and screen sizes, processing image quality, cost and the like, and has certain defects and shortcomings. In practical applications, these problems may lead to a series of problems such as reduced image quality and poor use experience. Therefore, there is a need to provide an efficient and flexible HDMI-to-LVDS scheme to address the drawbacks and deficiencies of the prior art.

The application aims to provide an HDMI-to-LVDS scheme which uses an FPGA to realize scaling and clipping in the same proportion, and can adapt to different resolutions and screen sizes and process high-quality image signals. The scheme can be set and adjusted through the serial port or the keys, and is simple to operate and flexible to use. The application can effectively improve the adaptability and the image processing capability of HDMI to LVDS, and provides better use experience and wider application range for users.

In order to achieve the above objective, the embodiments of the present application provide a method and an apparatus for converting HDMI to LVDS, which are implemented by the following technical solutions.

In a first aspect, an embodiment of the present application discloses a method for implementing HDMI to LVDS conversion for video image scaling clipping based on FPGA, as shown in fig. 1, the method includes the following steps:

s1, responding to screen parameters input into a display screen through a serial port or keys, and outputting the screen parameters to a nixie tube to display parameters;

s2, outputting an HDMI signal to an FPGA by a video source, decoding the video signal on the FPGA, and decoding the tmds signal into an RGB888 signal;

s3, the signals pass through an image processing module, the RGB888 video signals are subjected to scaling processing in the same proportion by adopting a bilinear scaling circuit, the scaling factors and the scaled resolution are obtained by a parameter calculation module, and the scaled video signals need to recalculate XY coordinates, so that the clipping part is convenient to clip out the resolution consistent with that of the LVDS display;

s4, the cut video signal passes through a DDR3_TOP module and is cached in a ping-pong mode;

and S5, finally, converting the video signal into an LVDS differential signal according to the resolution time sequence of the display through the LCD control module, and displaying the LVDS differential signal on the display screen.

Specifically, referring to fig. 2, the fpga portion includes:

LVDS screen parameter module: and receiving LVDS screen parameter information transmitted by a serial port or a key, wherein the LVDS screen parameter information comprises row synchronization, field synchronization, display trailing edge, display area, display leading edge and display period, and displaying the LVDS screen parameter information on a nixie tube.

EDID reads the module: the system is responsible for communicating with the input source and tells the input source of the parameters of the required performance of the monitor, including manufacturer information, the name and serial number of the display, all supported resolution lists, color settings, manufacturer preset values and the like. The embodiment of the application is set to 1920 x 1080@60 common resolution frame rate.

HDMI decoding module:

1) Serial-parallel conversion module: the incoming serial differential data is converted to serial single-ended data, which is then converted to 10bit parallel data.

2) Word pair Ji Jiaozhun module: comparing the 10bit parallel data with 4 control characters, if the control characters can be detected continuously at all 16 delay values, the range of delay values is considered to be found, and the middle delay value is taken as a final value at this time, so that calibration is completed.

3) And a data synchronization module: and synchronizing the data of the red, green and blue groups to prevent the color deviation of the image.

4) 8b/10b decoding module: parallel 10bit data is converted into 8bit data, and a line field signal and data effective enabling are generated at the same time.

An image processing module: mainly comprises a video scaling part and a video clipping part, and the whole schematic diagram is shown in figure 3.

1) The video scaling part adopts bilinear interpolation algorithm to scale input video signals in the same proportion, a scaling circuit is shown in fig. 4, firstly, buffers one line of data by using a FIFO1, then sequentially stores the data into a RAM 1/RAM 2, stores two lines of video signals, then carries out linear interpolation, and then buffers the calculated data into a RAM3 as a numerical value after line interpolation; next, the value is linearly interpolated in the column direction, and the result is the last scaled value, which is buffered in FIFO2.

2) The video clipping portion, schematically shown in fig. 5, calculates the boundary coordinates of the scaled video signal, where the upper boundary coordinates are obtained by subtracting the field resolution of the LVDS screen from the scaled field resolution (e.g., 720) and dividing by 2, and the other boundaries are obtained by similar calculation methods.

DDR3_top module: and the DDR3 complicated read-write operation is packaged into a user interface similar to the FIFO, so that the data can be read and written conveniently. The input data is valid in the case where the input data enable signal is pulled high, and the output data is valid when one beat is delayed after the read request enable signal is pulled high. The field signals of the LVDS screen and the field signals of the HDMI respectively generate frame reset signals for the FIFO scheduling module and the DDR read-write module.

Parameter calculation module: and calculating a scaling factor, ddr3 read-write burst length and maximum read-write address which are needed by the video scaling module, and calculating the scaled screen parameter.

LCD control module: the device comprises an LCD display time sequence control module, a serial-parallel conversion module and an LVDS differential signal conversion module, reads RGB888 data cached by DDR3, and converts the RGB888 data into LVDS25 signals.

The core technology of the application is to utilize the FPGA chip to realize the reception and processing of HDMI signals and the output of LVDS signals. The programmability and high-performance computing power of the FPGA enable the present application to flexibly process video signals of different resolutions.

The application adopts bilinear interpolation algorithm to scale video signal in same proportion so as to maintain definition and detail of image and improve quality of image processing.

In a second aspect, the embodiment of the present application further discloses a device for implementing HDMI to LVDS conversion for video image scaling clipping based on FPGA, as shown in fig. 6 and fig. 7, where the device includes: the device comprises an HDMI input interface module 71, an FPGA chip module 72, an LVDS output interface module 73, a control module 74, an LVDS screen parameter module 75, an EDID reading module 76, an HDMI decoding module 77, an image processing module 78, a parameter calculation module 79 and an LCD control module 70.

In a specific embodiment, the HDMI input interface module 71 is configured to interface the I2C bus of the HDMI to the FPGA for transmitting the EDID information; the hot plug pin needs to be connected to the tristate gate and then connected to the FPGA, and a hot plug signal is transmitted; the FPGA chip module 72 is configured to receive LCD screen parameter data transmitted from the serial port or the key, and the screen parameter data is displayed on the nixie tube; the analyzed video data is transmitted to an FPGA chip, and the FPGA chip is responsible for scaling and cutting the video data in the same proportion; by adopting bilinear interpolation algorithm, the FPGA can scale the input video signal and cut the video signal to adapt to displays with different resolutions; the LVDS output interface module 73 is configured to transmit an LVDS differential signal to the fpc_40pin connector through the FPGA, so that the signal can be stably transmitted; the control module 74 is configured to receive an external instruction or a key input to adjust the output resolution, and may receive an instruction from a user through the serial port or the key interface, and adjust a processing parameter of the FPGA according to the instruction, so as to implement output with different resolutions.

The LVDS screen parameter module 75 is configured to receive LVDS screen parameter information transmitted by the serial port or the key, including line synchronization, field synchronization, display trailing edge, display area, display leading edge, display period, and display on the nixie tube; the EDID reading module 76 is configured to communicate with the input source, and is used for informing the input source of the parameters of the required performance of the monitor, including information of manufacturer information, names and serial numbers of the displays, all supported resolution lists, color settings, preset values of the manufacturer, and the like; an HDMI decoding module 77 configured to include a serial-to-parallel conversion module to convert incoming serial differential data to serial single-ended data, and then to convert the serial single-ended data to 10bit parallel data; the word alignment calibration module compares the 10bit parallel data with 4 control characters, if the control characters can be detected continuously at 16 delay values, the range of the delay values is considered to be found, and the middle delay value is taken as a final value at the moment to indicate that the calibration is completed; the data synchronization module synchronizes the data of the red, green and blue groups to prevent the color deviation of the image; converting the parallel 10bit data into 8bit data by using an 8b/10b decoding module, and simultaneously generating a line field signal and data effective enabling; the image processing module 78 is configured to perform scaling on the input video signal in the same proportion by using bilinear interpolation algorithm, and calculate boundary coordinates of the scaled video signal.

The parameter calculation module 79 is configured to calculate a scaling factor, ddr3 read-write burst length and maximum read-write address required by the video scaling module, and calculate a scaled screen parameter; the LCD control module 70 is configured to include an LCD display timing control, a serial-parallel conversion module, and an LVDS differential signal conversion module, read RGB888 data buffered by DDR3, and convert the data into an LVDS25 signal.

Working principle: firstly, inputting screen parameters (row synchronization, field synchronization, display trailing edge, display area, display leading edge and display period) of a display screen through a serial port or keys, and displaying on a nixie tube; and then the video source outputs HDMI signals to the FPGA, video signal decoding and processing are carried out on the FPGA, DDR3 is used for caching in a ping-pong mode, and finally differential signals are output and displayed on the LVDS display screen through the FPC.

The application has the following beneficial effects:

1. multiresolution adaptation capability: the application adopts the same-proportion scaling and cutting technology realized by the FPGA, and can adapt to screens with different resolutions; the user can adjust through the serial port or the key to realize flexible control of the output resolution; this makes the application widely applicable to various scenes with different resolution requirements, providing greater application flexibility.

2. High quality image processing: the application adopts bilinear interpolation algorithm to realize scaling in the same proportion, can keep the definition and detail of the image, and improves the quality of image processing; by the clipping function, the application can adapt the images to displays with different proportions, maintain the correct proportion of the images and avoid the deformation or distortion of the images.

3. Simple and easy-to-use operation mode: the application adopts a serial port or key control mode, so that a user can conveniently set and adjust the output resolution; the simple and easy-to-use operation mode not only improves the use convenience of the user, but also reduces the complexity of operation and the learning cost of the user.

4. Cost effectiveness: the application adopts the FPGA as the core processor, so that the high-efficiency image processing can be realized with lower cost; compared with the traditional hardware scheme, the application has lower cost and greater flexibility and expandability.

In summary, the technical scheme of the application brings various beneficial effects in aspects of multi-resolution adaptation capability, high-quality image processing, simple and easy-to-use operation mode, cost effectiveness and the like, and provides better use experience and wider application scenes for users.

The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the application referred to in the present application is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept described above. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.

Claims

1. A method for converting HDMI to LVDS for realizing video image scaling clipping based on FPGA is characterized by comprising the following steps:

2. The method for converting HDMI to LVDS for implementing video image scaling clip based on FPGA of claim 1, wherein the video source outputs HDMI signals to the FPGA, the video signal decoding is performed on the FPGA, and the decoding of tmds signals into RGB888 signals further comprises:

3. The method for converting HDMI to LVDS for implementing video image scaling clip based on FPGA of claim 2, wherein the image processing module specifically comprises two parts, video scaling and video clip:

4. The method for converting HDMI to LVDS for implementing video image scaling clip based on FPGA of claim 1, further comprising: the EDID reading module is used for communicating with the input source to tell the input source of parameters of the required performance of the monitor, wherein the parameters comprise manufacturer information, the name and serial number of the display, a list of all supported resolutions, color settings and preset values of the manufacturer.

5. The method for converting HDMI to LVDS for implementing video image scaling clip based on FPGA of claim 1, wherein said screen parameters of the display screen comprise line sync, field sync, display back edge, display area, display front edge, display period.

6. An HDMI to LVDS device for implementing video image scaling clipping based on FPGA is characterized in that the device comprises:

7. The device for converting HDMI to LVDS for implementing video image scaling clip based on FPGA of claim 6, further comprising:

8. The device for converting HDMI to LVDS for implementing video image scaling clip based on FPGA of claim 7, further comprising:

9. An electronic device, comprising:

one or more processors;

a storage means for storing one or more programs;

when executed by the one or more processors, causes the one or more processors to implement the method of any of claims 1 to 5.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method according to any one of claims 1 to 5.