CN117194281B - Asymmetric access method for variable-length data in ASIC - Google Patents

Abstract

The invention discloses an asymmetric access method for data with indefinite length in an ASIC (application specific integrated circuit), which belongs to the field of storage, and adopts a plurality of read-write fingers to perform read-write operation on the data with indefinite length, wherein each finger corresponds to one storage unit in an operation storage circuit; and (3) defining the maximum bit width of the written data and the read data in each clock period, wherein the result of dividing the maximum bit width of the written data and the bit width of each storage unit is the number of write pointers, and the maximum bit width of the read data is the number of read pointers. The invention is suitable for storing and forwarding the indefinite length data with bit width changed in each clock period or a plurality of clock periods, can realize the situation that the bit widths of the interactive data of two systems are not matched in a plurality of different application scenes, can be used for replacing the traditional bit width conversion circuit, and can realize the data storing and forwarding in a plurality of scenes by changing the processing of changing the read pointer and the write pointer into indefinite length or definite length data.

Description

Asymmetric access method for variable-length data in ASIC

Technical Field

The present invention relates to the field of memory technologies, and in particular, to an asymmetric access method for variable-length data in an ASIC (Application SPECIFIC INTEGRATED Circuit).

Background

In some complex circuitry, the interaction between data is particularly complex. Performing data interaction on two circuits with unmatched data bit widths, and performing operations such as storage, interception, splicing, displacement and the like on the data; however, in the case where the data bit width to be processed is continuously changed, a new circuit and method are needed to solve the problem, and a typical application example in the MIPI-PAL GPIO (General-purpose input/output) circuit is given below.

As shown in fig. 1, for sampling multiple GPIO signals, for different configurations of PAL GPIOs (Protocol Adaptation Layer ) in the over-sampling mode, the bit width of the data captured at each sampling point is different, the data needs to be stored in the continuous sampling process, the sampling in the over-sampling mode is a continuous and uninterrupted process, a large amount of data generated during the sampling needs to be temporarily stored, and the captured data needs to be temporarily stored at each sampling point, because the bit width of the data captured at each sampling point is indefinite, that is, the bit width of the data stored at each clock period is indefinite, and the bit width of the data to be read out at each clock period is also indefinite, so a method for storing data with indefinite length is needed.

Disclosure of Invention

The present invention is directed to an asymmetric access method for variable length data in an ASIC to solve the problems in the background art.

In order to solve the above technical problems, the present invention provides an asymmetric access method for variable-length data in an ASIC, including:

performing read-write operation on data with indefinite length by adopting a plurality of read-write fingers, wherein each pointer corresponds to one storage unit in an operation storage circuit;

And (3) defining the maximum bit width of the written data and the read data in each clock period, wherein the result of dividing the maximum bit width of the written data and the bit width of each storage unit is the number of write pointers, and the maximum bit width of the read data is the number of read pointers.

In one embodiment, the bit width for each actual write or read of data is indeterminate, each write or read of data bit width being calculated by the algorithm circuitry, requiring an additional algorithm circuitry to provide the data bit width for each read or write operation;

the data writing operation in the storage circuit is performed, and data with specific length is written into the storage by controlling the number of the write pointers with specific number in each clock cycle;

the read data operation in the memory circuit reads data of a specific length from the memory cells by controlling the number of read pointers matching the read data bit width every clock cycle.

In one embodiment, the sequence number of the read-write pointer corresponds to the low order to the high order of one clock cycle data from small to large; the number of memory cells in the memory circuit, i.e. the depth of the memory circuit, needs to be calculated according to the actual read/write speed.

In one embodiment, the memory unit of the memory circuit is 1 bit wide, and the data written with the maximum bit width at the same time in one clock cycle is 4 bits;

In the first period, bits 0 and 3 in the valid bits are 1 which are valid data stored in the memory circuit, so that four write pointers operate simultaneously, the values of the first three write pointers are 1, the value of the fourth write pointer is 2, the data with two bits are respectively written into a memory cell 0 and a memory cell 1 of the memory circuit, and the next writing operation is performed to prepare writing operation of the following data from the memory cell 2;

In the second cycle, since bits 2 and 3 in the valid bits are 1 as valid data stored in the memory circuit, four write pointers operate simultaneously, the first write pointer has a value of 3, and the last three write pointers have a value of 4, which means that data having 2 bits are written into the memory cell 2 and the memory cell 3 of the memory circuit, respectively, and the next write operation is performed in preparation for the following data writing operation from the memory cell 4.

The asymmetric access method for the variable-length data in the ASIC is suitable for storing and forwarding the variable-length data with the bit width changed in each clock cycle or in a plurality of clock cycles, can realize the situation that the bit widths of the interactive data of two systems are not matched in a plurality of different application scenes, can be used for replacing a traditional bit width conversion circuit, and can realize the data storing and forwarding in a plurality of scenes by changing a read pointer and a write pointer into the variable-length or fixed-length data.

Drawings

Fig. 1 is a schematic diagram of GPIO signal sampling.

Fig. 2 is a schematic diagram of a general memory circuit.

FIG. 3 is a schematic diagram of an indefinite length data storage circuit according to the present invention.

Fig. 4 is a schematic diagram of an indefinite length data writing memory circuit according to the present invention.

Detailed Description

An asymmetric access method for variable length data in an ASIC according to the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

As shown in fig. 2, a general memory circuit is shown, in which there is a read pointer and a write pointer, and each time the read pointer and the write pointer are added with 1, there is a fixed bit width of data to be read from or written into the memory, and the read/write of data with an indefinite length cannot be completed by using the general memory.

The invention provides a memory circuit for storing and forwarding data with indefinite length, as shown in fig. 3, wherein a plurality of read and write pointers are adopted in the memory circuit for performing read and write operations on the data with indefinite length, each pointer corresponds to one memory cell in the operation memory circuit, the maximum bit width of the data written in and read out in each clock period is required to be defined, the division result of the maximum bit width of the data written in each time and the bit width of each memory cell is the number of write pointers, and the maximum bit width of the data read out each time is the number of read pointers.

The actual bit width of each write or read of data is uncertain, and the bit width of each write or read of data is calculated by the algorithm circuit, so an additional algorithm circuit is needed to provide the bit width of each read or write operation; for a write data operation in a memory circuit, a specific length of data is written into the memory by controlling the number of write pointers for a specific number of clock cycles. Also for stored read data operations, data of a particular length is read from the memory cells by controlling the number of read pointers that match the read data bit width per clock cycle. Wherein the sequence numbers of the read-write pointers correspond to the low order to the high order of one clock cycle data from small to large. The number of the storage units in the storage circuit, namely the depth of the storage circuit, is calculated according to the actual reading and writing speed, and the designed storage is required to be used according to the actual application, so that the problem that the storage circuit overflows upwards and overflows downwards in the reading and writing process is avoided.

As shown in fig. 4, an example of writing data with an indefinite length into a memory circuit is shown, wherein a memory cell of the memory circuit is 1 bit wide, and simultaneously, data with a maximum bit width can be written simultaneously in one clock cycle is 4 bits. In the first cycle, since bits 0 and 3 in the valid bits are 1 as valid data stored in the memory circuit, four write pointers operate simultaneously, the first three write pointers have values of 1, the fourth write pointer has a value of 2, which indicates that data having 2 bits are written into the memory cell 0 and the memory cell 1 of the memory circuit, respectively, and the next write operation is performed in preparation for the following data writing operation from the memory cell 2. In the second period, since bits 2 and 3 in the valid bits are 1 as valid data stored in the memory circuit, four write pointers operate simultaneously, the first write pointer has a value of 3, and the last three write pointers have a value of 4, which means that data having 2 bits are written into the memory cell 2 and the memory cell 3 of the memory circuit, respectively, and the next write operation is performed in preparation for the writing operation of the following data from the memory cell 4.

In the asymmetric access method for the data with the indefinite length in the ASIC, a storage circuit adopts a plurality of pointers to simultaneously perform read-write operation in one clock cycle, each read-write pointer corresponds to effective data on one address respectively, and the number of the effective pointers is multiplied by the data bit width under one address in each clock cycle, namely the effective bit width of the corresponding data; the bit width of the corresponding memory cell at an address in the memory circuit can be changed, but all bits are required to be valid at the same time, and the states of the bits are bound together; the storage depth is changed, the fixed width of one storage unit is changed, and the maximum number of read-write pointers is used for solving the problem of storing the data with different lengths in different application scenes; by changing the behavior of the read-write pointer, the read data is controlled to be of an indefinite length and the write data is controlled to be of a definite length, and the write data is controlled to be of a definite length when the write data is of an indefinite length and is simultaneously in three different circuit behaviors of the indefinite length.

The invention provides a method for storing and forwarding data with indefinite length through a storage circuit with a special structure, which solves the problem that the universal storage can only read and write fixed bit width data in each clock cycle and can not store the data with indefinite bit width which is possibly changed in each clock cycle.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (1)

1. An asymmetric access method for variable length data in an ASIC, comprising:

performing read-write operation on data with indefinite length by adopting a plurality of read-write fingers, wherein each pointer corresponds to one storage unit in an operation storage circuit;

the method comprises the steps of determining the maximum bit width of data written and read in each clock cycle, wherein the result of dividing the maximum bit width of data written in each time by the bit width of each storage unit is the number of write pointers, and the maximum bit width of data read out each time is the number of read pointers;

the bit width of the data written or read each time is uncertain, the data bit width of each time is calculated by an algorithm circuit, and an extra algorithm circuit is needed to provide the data bit width of each time of read-write operation;

the data writing operation in the storage circuit is performed, and data with specific length is written into the storage by controlling the number of the write pointers with specific number in each clock cycle;

reading data in the storage circuit, and reading data with specific length from the storage unit by controlling the number of read pointers matched with the bit width of the read data in each clock cycle;

The sequence numbers of the read-write pointers correspond to the low order to the high order of data in one clock period from small to large; the number of storage units in the storage circuit, namely the depth of the storage circuit, is calculated according to the actual reading and writing speed;

the memory unit of the memory circuit is 1 bit wide, and simultaneously data with the maximum bit width is written into the memory circuit at the same time in one clock period to be 4 bits;

In the first period, bits 0 and 3 in the valid bits are 1 which are valid data stored in the memory circuit, so that four write pointers operate simultaneously, the values of the first three write pointers are 1, the value of the fourth write pointer is 2, the data with two bits are respectively written into a memory cell 0 and a memory cell 1 of the memory circuit, and the next writing operation is performed to prepare writing operation of the following data from the memory cell 2;

In the second cycle, since bits 2 and 3 in the valid bits are 1 as valid data stored in the memory circuit, four write pointers operate simultaneously, the first write pointer has a value of 3, and the last three write pointers have a value of 4, which means that data having 2 bits are written into the memory cell 2 and the memory cell 3 of the memory circuit, respectively, and the next write operation is performed in preparation for the following data writing operation from the memory cell 4.