CN117155074A

CN117155074A - TURBO mode switching converter and control circuit thereof

Info

Publication number: CN117155074A
Application number: CN202310987279.6A
Authority: CN
Inventors: 王牧晨
Original assignee: Junying Semiconductor Shanghai Co ltd
Current assignee: Junying Semiconductor Shanghai Co ltd
Priority date: 2023-08-07
Filing date: 2023-08-07
Publication date: 2023-12-01

Abstract

The invention discloses a TURBO mode switching converter and a control circuit thereof. Comprising the following steps: a timer circuit configured to determine a duration and to generate a timer expiration signal upon expiration of the duration, the timer expiration signal being used to generate the first control signal; logic circuitry configured to switch the first switch from the second state to the first state based on the first control signal; a TURBO comparator configured to generate an acceleration mode signal when the feedback voltage is less than a threshold voltage; and a time adjustment circuit configured to generate an adjustment signal to the timer circuit based on the acceleration mode signal, the adjustment signal for changing a time of generation of the timer expiration signal to adjust a length of the duration. The control circuit can more rapidly adjust the turn-off time of the switching element in the power circuit when the load jumps, and quickens the rising of the inductance current, thereby reducing undershoot of the output voltage and improving the dynamic response speed of the load.

Description

TURBO mode switching converter and control circuit thereof

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a TURBO mode switching converter and a control circuit thereof.

Background

Modern portable electronic devices are often provided with a power source, such as a battery, which serves as the Direct Current (DC) for the various electronic components within the device. However, typically these components will have different voltage requirements, and so such devices typically employ one or more voltage converters that reduce the nominal voltage associated with the power supply to a voltage suitable for the different electronic components.

Existing voltage converters typically employ both linear regulators and switching converters. In a linear regulator, the output voltage is regulated by regulating a passive element (e.g., a variable resistor) to control the continuous flow of current from a voltage source to a load. Switching converters control the output voltage by switching the current on or off, typically using one or more switches and inductive and capacitive components to store and transfer energy to the load side, and regulators regulate the magnitude of the voltage delivered to the load side by controlling the switching elements on and off, thereby controlling the amount of power delivered through the inductor in the form of discrete current pulses. The inductor and capacitor convert the delivered current pulses into a stable load current for regulating the load voltage. Finally, regulation of the output voltage is achieved by adjusting the on and off times of the switching elements in accordance with feedback signals representing the output voltage and the load current.

Switching converters operating in current mode provide good linearity and load transient signal suppression and have good current limiting capability during fault conditions (e.g., output shorts) and are therefore widely used.

When the DCDC switching converter is switched between light load and heavy load, the output voltage VOUT is instantaneously reduced due to rapid rising of load current. The change of the output voltage caused by the load jump is the load adjustment capability of the switching converter, and the better the load adjustment capability, the smaller the influence of the load change on the converter is. In order to improve the load regulation capability of the switching converter, a TURBO mode may be introduced into the converter, the operating principle of which is: when the feedback voltage of the output voltage VOUT is lower than the threshold voltage of the TURBO comparator, entering a TURBO mode; when the feedback voltage is higher than the threshold voltage of the TURBO comparator, the TURBO mode is exited. During the TURBO mode, the down tube on time is shortened and the up tube on time is lengthened, so that the output voltage VOUT can be raised more quickly.

The drawbacks of the existing TURBO mode switching converters are: the action time and effect of the TURBO mode are fixed, and cannot change along with external input and output voltage and load, so that the problem of output oscillation or under-voltage caused by the fixed action time of the TURBO under different working conditions can be caused. In addition, the conventional TURBO mode switching converter may have abrupt changes in inductor current before and after the TURBO mode is switched, thereby causing problems such as overshoot or undershoot of the output voltage at the time of mode switching.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a TURBO mode switching converter and a control circuit thereof, which can dynamically adjust the turn-off time of a switching element in a power circuit during mode switching, so as to reduce undershoot of an output voltage and improve dynamic response speed of a load.

According to an aspect of an embodiment of the present invention, there is provided a control circuit of a TURBO mode switching converter including a first switch connected to a switching node, the control circuit being configured to switch the first switch between first and second states based on an input voltage and an output voltage of the switching converter, the control circuit comprising: a timer circuit configured to determine a duration and to generate a timer expiration signal upon expiration of the duration, the timer expiration signal being used to generate a first control signal; logic circuitry configured to switch the first switch from a second state to a first state based on the first control signal; a TURBO comparator configured to compare a feedback voltage of the output voltage with a predetermined threshold voltage and generate an acceleration mode signal when the feedback voltage is less than the threshold voltage; a time adjustment circuit configured to generate an adjustment signal to the timer circuit based on the acceleration mode signal, the adjustment signal for changing a time of generation of the timer expiration signal to adjust a length of the duration.

Optionally, the control circuit further includes: a single pulse circuit configured to generate a narrow pulse signal based on the acceleration mode signal; and an or gate configured to or the narrow pulse signal with the timer expiration signal to generate the first control signal.

Optionally, the time adjustment circuit is further configured to: the adjustment signal is generated based on an error between the feedback voltage and a predetermined first reference voltage such that a length of the duration is related to the error.

Optionally, the timer circuit includes: a reference voltage generation module configured to generate a second reference voltage that characterizes the duration; a ramp voltage generation module configured to output a gradually rising ramp voltage and start timing after the first switch is switched from the second state to the first state; and a comparator configured to generate the timer expiration signal when the ramp voltage rises to the second reference voltage, wherein the adjustment signal changes a generation timing of the timer expiration signal by changing the second reference voltage.

Optionally, the reference voltage generating module includes: a first ac small signal element and a second ac small signal element connected in series between a power supply voltage and a ground potential, the first ac small signal element configured to provide a first current related to the input voltage, the second ac small signal element configured to provide a second current related to the output voltage and a predetermined switching frequency; and a shunt resistor connected in parallel between the two ends of the second alternating current small signal element, wherein the shunt resistor is configured to generate the second reference voltage at a first end thereof based on the first current and the second current, and the adjustment signal changes the second reference voltage by drawing a current at the first end of the shunt resistor.

Optionally, the ramp voltage generating module includes: a third alternating current small signal element and a ramp capacitor connected in series between the power supply voltage and the ground potential; and a second switch connected in parallel between both ends of the ramp capacitor, wherein the on and off of the second switch is controlled based on the timer expiration signal.

Optionally, the time adjustment circuit includes: a transconductance amplifier configured to convert an error between the feedback voltage and the first reference voltage into an error current; and a transmission gate unit configured to be turned on or off in response to the acceleration mode signal and to generate the adjustment signal based on an output of the transconductance amplifier when turned on.

Optionally, the time adjustment circuit further includes: a current bias unit configured to generate a bias current to the transconductance amplifier based on the input voltage, the output voltage, and a predetermined switching frequency, wherein the current bias unit comprises: a fourth ac small signal element and a fifth ac small signal element connected in series between a power supply voltage and a ground potential, the fourth ac small signal element configured to provide a first current related to the input voltage, the fifth ac small signal element configured to provide a second current related to the output voltage and a predetermined switching frequency, wherein an intermediate node of the fourth ac small signal element and the fifth ac small signal element is configured to provide the bias current.

Optionally, the TURBO comparator is implemented by a hysteresis comparator.

Optionally, the control circuit further includes: an error amplifier configured to obtain an error amplified signal between a feedback voltage of the output voltage and a reference voltage; a current detection circuit configured to obtain a current detection signal representative of an inductor current peak of the switching converter; and a peak comparator configured to compare the error amplified signal with the current detection signal to obtain a second control signal, wherein the logic circuit is configured to switch the first switch from a first state to a second state based on the second control signal.

According to another aspect of an embodiment of the present invention, there is provided a TURBO mode switching converter including: an input terminal for receiving an input voltage; an output terminal connected to the load for providing an output voltage; a power circuit coupled to the input and output terminals, the power circuit employing at least one inductive element and at least a first switch to regulate current provided to the load; and the control circuit is connected to the first switch and is configured to switch the first switch between a first state and a second state based on the input voltage and the output voltage.

The TURBO mode switching converter is provided with the time adjusting circuit in the control circuit, the time adjusting circuit can change the generation time of the expiration signal according to the acceleration mode signal output by the TURBO comparator, and then the duration of the turn-off time of the switching element in the power circuit can be adjusted, so that the turn-off time of the switching element in the power circuit can be adjusted more quickly when a load jumps from light load to heavy load, the rising of inductance current is accelerated, undershoot of output voltage is reduced, and the dynamic response speed of the load is improved.

Furthermore, the time adjustment circuit can adjust the time length of the turn-off time according to the recovery condition of the output voltage, when the output voltage is lower, the turn-off time can be shortened to enable the inductor current to rise more rapidly, when the output voltage is higher, the turn-off time can be recovered to the time length of normal operation, and overshoot of the output voltage during mode switching can be avoided.

Further, the control circuit of the present invention further includes a single pulse circuit that generates a narrow pulse signal based on the acceleration mode signal so that the low side switch of the switching converter is turned off and the high side switch is turned on when the output of the TURBO comparator just turns high, thereby making the switching of the TURBO mode smoother and reducing abrupt changes in the output voltage.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a schematic circuit diagram of a conventional TURBO mode switching converter.

Fig. 2 is a diagram showing an output waveform of a conventional TURBO mode switching converter when a load is changed.

Fig. 3 is a schematic circuit diagram of a TURBO mode switching converter according to an embodiment of the present invention.

Fig. 4 is a schematic circuit diagram of a time adjustment circuit and a timer circuit according to an embodiment of the present invention.

Fig. 5 is a waveform diagram illustrating an operation of the TURBO mode switching converter according to an embodiment of the present invention.

Fig. 6 is a schematic waveform diagram of a TURBO mode switching converter according to an embodiment of the present invention when the load is changed.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.

Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

In the context of the present application, a transistor blocks current and/or does not substantially conduct current when the transistor is in an "off (off) state" or "off". Conversely, when the transistor is never in an "on (on) state" or "conducting", the transistor is able to conduct current significantly. For example, in one embodiment, the high voltage transistor comprises an N-channel metal oxide semiconductor (NMOS) Field Effect Transistor (FET), wherein the high voltage is provided between a first terminal (i.e., drain) and a second terminal (i.e., source) of the transistor. In some embodiments, an integrated controller circuit may be used to drive the power switch when regulating the energy provided to the load. In addition, for purposes of this disclosure, "ground" or "ground potential" in this disclosure refers to a reference voltage or potential with respect to which all other voltages or potentials of an electronic circuit or Integrated Circuit (IC) are defined or measured.

Fig. 1 is a schematic circuit diagram of a conventional TURBO mode switching converter. As shown in fig. 1, the switching converter 100 includes a power circuit, an error amplifier 131, a current detection circuit 110, a peak comparator 132, a logic circuit 140, a driving circuit 150, a timer circuit 121, a delay circuit 122, a single pulse circuit 123, a TURBO comparator 124, an AND gate AND OR gate OR.

The power circuit is connected between the input terminal and the output terminal, and uses at least one inductance element and at least one switch element to regulate the current supplied to the load connected to the output terminal, so as to provide a stable and continuous output voltage VOUT to the load according to the input voltage VIN. Illustratively, the power circuit includes switches S1 and S2 connected in series between the input and ground, and an inductor L1 is connected between a switching node Lx between the switches S1 and S2 and the output. An output capacitor Co is connected between the output terminal and ground for smoothing the output voltage VOUT.

The switching converter 100 further includes voltage dividing resistors Ra and Rb connected in series between the output terminal and ground, and an intermediate node therebetween for providing a feedback voltage VFB of the output voltage VOUT. The error amplifier 131 has a negative input terminal connected to the feedback voltage VFB, a positive input terminal receiving the reference voltage VBG, and an output terminal for outputting an error amplified signal Vc of a difference (or error) between the feedback voltage VFB and the reference voltage VBG.

The current detection circuit 110 is configured to obtain a current detection signal Vs characterizing an inductive current of at least one inductive element in the power circuit by detecting a current flowing through the at least one inductive element during conduction of a switching element in the power circuit. The above-described sampling may be implemented by sampling resistors, current transformers, current mirrors, or the like, and the current detection circuit 110 may also estimate the current flowing through the inductance element by sampling the current flowing through each switching element and acquire the current detection signal Vs.

The switching converter 100 is configured to control operation of the power circuit in a Continuous Conduction Mode (CCM) using peak current. In particular, each switching cycle comprises an on-time Ton in which the current from the input flows in the inductive element and the switching element, so that energy can be stored in the at least one inductive element, and an off-time Toff. In peak current control mode, the duration of the on-time period Ton is controlled using a suitable feedback control loop based on the voltage sensed by the current detection circuit 110. The peak comparator 132 has, for example, a positive input terminal receiving the current detection signal Vs, a negative input terminal receiving the error amplification signal Vc, and an output terminal for outputting a control signal SC. Wherein the control signal SC is used to control the duration of the on-time Ton. For example, the peak comparator 132 is configured to generate the control signal SC to switch the switch S1 in the power circuit from the on state to the off state when the current detection signal Vs rises to the error amplification signal Vc.

During the off-time Toff, the energy previously stored in the inductive element is transferred to the load side. In particular, the duration of the off-time Toff may be fixed. Illustratively, the timer circuit 121 is used to provide an internal clock for switching timing to the circuit to control the duration of the switching cycle of the switch S1 in the power circuit. Further, the timer circuit 121 is configured to generate a timer expiration signal ST1 to switch the switch S1 from the off state to the on state upon expiration of the preferred switching period.

Further, the switching converter 100 further includes a TURBO comparator 124 for switching a TURBO mode, and the TURBO comparator 124 is configured to compare the feedback voltage VFB of the output voltage VOUT with a predetermined threshold voltage turbo_ref to obtain a comparison result. The monopulse circuit 123 is configured to generate a TURBO signal of a fixed time pulse based on the output of the TURBO comparator 124, the AND gate AND is configured to AND-gate the TURBO signal with the low-side drive signal LSD, the delay circuit 122 is configured to delay the output of the AND gate AND to obtain an output signal, AND the OR gate OR is configured to OR-gate the timer expiration signal ST1 with the output signal of the delay circuit 122 to obtain the control signal ST. The logic circuit 140 is configured to generate a pulse width modulation signal PWM based on the control signal SC and the control signal ST, and then drive the on and off of the switch S1 through the driving circuit 150. For example, the logic circuit 140 may be implemented by an edge-triggered RS flip-flop that generates an inactive pulse width modulation signal PWM based on the control signal SC and generates an active pulse width modulation signal PWM based on the control signal ST.

Fig. 2 is a waveform diagram of the output of the conventional TURBO mode switching converter 100 when the load changes. In fig. 2, VFB represents a feedback voltage of the output voltage VOUT, TURBO represents an output signal of the TURBO comparator, and IL represents an inductance current flowing through the inductor L1 in the switching converter. As shown in fig. 2, when the external load changes from light load to heavy load, the output voltage VOUT will decrease rapidly, AND when the feedback voltage VFB is smaller than the set threshold voltage trubo_ref, a TURBO signal of 3.3us is generated in the switching converter, during this period, the delay circuit 122, the AND gate AND the OR gate control the signal ST with a delay of 400ns, so as to ensure that the on time of the low-side switch S2 is not greater than 400ns each time, so that the inductor current IL can climb rapidly to improve the dynamic response of the circuit.

However, the conventional switching converter 100 cannot change the duration of the TURBO mode according to the external input/output voltage and the load due to the limitation of the acting time of the TURBO mode, which may cause the problem of output oscillation or under-voltage due to the fixed acting time of the TURBO under different working conditions. In addition, the conventional TURBO mode switching converter may have abrupt changes in inductor current before and after the TURBO mode is switched, thereby causing problems such as overshoot or undershoot of the output voltage at the time of mode switching.

Fig. 3 is a schematic circuit diagram of a TURBO mode switching converter according to an embodiment of the present invention. As shown in fig. 3, the switching converter 200 includes a power circuit having one or more switching elements and filter elements (e.g., inductors and/or capacitors, etc.) configured to regulate the transfer of electrical energy from the input to the output of the switching converter in response to a switching drive signal to convert an input voltage VIN to a stable continuous output voltage VOUT.

In some embodiments, the switching converter 200 may be classified into a buck-type (buck) converter, a boost-type (boost) converter, a flyback-type (flyback) converter, and a buck-boost-type (buck-boost) converter according to the topology classification of the power circuit.

In one exemplary embodiment, the power circuit is implemented by a buck topology, including switch S1, switch S2, and inductor L1. The switches S1 and S2 are connected between a voltage supply node (e.g., an input voltage VIN) and ground, a first terminal of the inductor L1 is connected to a switch node Lx between the switches S1 and S2, and a second terminal of the inductor L1 is connected to the output node VOUT. Switches S1 and S2 (also referred to as high-side and low-side switches, respectively) may be any controllable semiconductor switching device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), etc., e.g., an N-channel MOSFET, controlled by gate drive signals HSD and LSD, respectively, to alternately operate between a first state and a second state (e.g., on and off states). In addition, the power circuit of the present embodiment further includes an output capacitor Co connected between the output node VOUT and the ground node.

It should be noted that although MOSFETs are used for the switching elements in this embodiment, any other type of suitable switching element may be used without departing from the principles of the present invention. Although the synchronous buck converter is described in this embodiment, the present invention is not limited thereto, and the present invention is equally applicable to the asynchronous buck converter, and a rectifier diode may be used instead of the switch S2 in the above embodiment by those skilled in the art.

The switching converter 200 further comprises a control circuit 210 coupled to the switching elements S1 and S2, the control circuit 210 being adapted to generate a pulse width modulated signal PWM applied to the switching elements S1 and S2 to control the switching states of the switching elements S1 and S2 via a driving circuit 216 to supply energy to the load. The driving circuit 216 is configured to generate driving signals HSD and LSD respectively applied to the gates of the switching elements S1 and S2 based on the pulse width modulation signal PWM. In another embodiment, the drive circuit 216 may be part of the control circuit 210 or may be separate from the control circuit 210.

In the present embodiment, the control circuit 210 performs energy conversion by the inductor L1 by repeatedly turning on/off the switching elements S1 and S2 alternately, thereby reducing the input voltage VIN, smoothing the reduced voltage by the inductor L1 and the output capacitor Co, and outputting the smoothed voltage as the output voltage VOUT.

In which the control circuit 210 of the switching converter 200 may be integrated into an LSI chip on a semiconductor substrate. In the present embodiment, the switching elements S1 and S2 may be provided outside the control circuit 210, but may also be provided inside the control circuit.

The switching converter 200 is configured to utilize peak current to control operation of the power circuit in a Continuous Conduction Mode (CCM). In particular, each switching cycle comprises an on-time Ton in which the switch S1 is on and the switch S2 is off, and an off-time Toff in which the current from the input flows in the inductive element and the switching element, so that energy can be stored in the at least one inductive element, the current in the inductive element rising. During the off time Toff, the switch S1 is turned off and the switch S2 is turned on, and the energy previously stored in the inductive element is transferred to the load terminal or the input terminal, so that the current in the inductive element drops.

In the present embodiment, the control circuit 210 further includes an error amplifier 211, a peak comparator 212, a current detection circuit 213, a TURBO comparator 214, a logic circuit 215, a single pulse circuit 217, a time adjustment circuit 218, and a timer circuit 219.

The positive input of the error amplifier 211 is for receiving the feedback voltage VFB of the output voltage VOUT, the negative input of the error amplifier 211 is for receiving a reference voltage VBG, and the error amplifier 211 is configured to compare the feedback voltage VFB with the reference voltage VBG to generate an error amplified signal Vc, the signal Vc representing the difference between the feedback voltage VFB and the reference voltage VBG. In an exemplary embodiment, the switching converter 200 further includes a voltage dividing network disposed at the output terminal, the voltage dividing network being formed by resistors Ra and Rb, and obtaining the feedback voltage VFB of the output voltage VOUT at a common node of the two.

The positive input of the peak comparator 212 is for receiving a current detection signal Vs characterizing the peak value of the inductor current of the inductor L1 in the switching converter 200, and the negative input of the peak comparator 212 is for receiving said error amplified signal Vc, which is configured to generate a control signal SC to switch the switch S1 from the on-state to the off-state when the current detection signal Vs rises to the error amplified signal Vc. In an embodiment, the current detection signal Vs is proportional to the current flowing through the switch S1 and obtained by the current detection circuit 213, for example, the current flowing through at least one inductive element in the power circuit may be detected by the current detection circuit 213 to obtain the current detection signal Vs. The above detection may be achieved by sampling resistors, current transformers, current mirrors, or the like, and the current detection circuit 213 may estimate the current flowing through the inductance element by sampling the current flowing through each switching element and acquire the current detection signal Vs. For example, in the present embodiment, the current detection circuit 213 may obtain the current detection signal Vs by sensing a sense resistor (not shown) connected across the high-side switch S1.

The timer circuit 219 is configured to determine a switching cycle time and to generate a timer expiration signal ST1 upon expiration of the switching cycle time, the timer expiration signal ST1 being used to generate the control signal ST. The logic circuit 215 is further configured to generate a pulse width modulation signal PWM based on the control signal SC and the control signal ST, and generate gate driving signals HSD and LSD according to the pulse width modulation signal PWM through the driving circuit 216 to drive on/off of the switches S1 and S2. For example, the logic circuit 215 may be an edge triggered SR flip-flop that provides an active (e.g., high) pulse width modulated signal PWM based on the timer expiration signal ST1 and an inactive (e.g., low) pulse width modulated signal PWM based on the control signal SC.

In this embodiment, the timer circuit 219 generates the timer expiration signal ST1 (e.g., a high level pulse) when each switching period expires, the switch S2 is switched from the on state to the off state, and after a suitable dead time, the switch S1 is switched from the off state to the on state, the input voltage VIN charges the inductor L1, so that the current IL on the inductor L1 continuously rises, the feedback voltage VFB and the reference voltage VBG are input to the negative input terminal of the peak comparator 212 after being amplified by the error amplifier 211, the current detection signal Vs is supplied to the positive input terminal of the peak comparator 212, the peak comparator 212 generates the control signal SC as the inductor current IL rises, the switch S1 is switched from the on state to the off state after a suitable dead time, and the current IL stored in the inductor L1 flows to the load, so that the current IL in the inductor L1 falls.

The negative input of the TURBO comparator 214 is for receiving the feedback voltage VFB of the output voltage VOUT, and the positive input of the TURBO comparator 214 is for receiving a predetermined threshold voltage TURBO REF. The TURBO comparator 214 is configured to compare the feedback voltage VFB of the output voltage VOUT with a predetermined threshold voltage turbo_ref and generate an acceleration mode signal TURBO when the feedback voltage VFB is less than the threshold voltage turbo_ref. Illustratively, the TURBO comparator 214 is configured to generate an inactive (e.g., low level) TURBO mode signal TURBO when the feedback voltage VFB is greater than a threshold voltage turbo_ref; and generating an active (e.g., high level) Turbo mode signal Turbo when the feedback voltage VFB is less than the threshold voltage turbo_ref. In an exemplary embodiment, the TURBO comparator 214 may be implemented by a comparator having a hysteresis function (e.g., a hysteresis comparator).

The time adjustment circuit 218 Is configured to generate an adjustment signal Is to the timer circuit 219 based on the TURBO mode signal TURBO, where the adjustment signal Is used to change the generation time of the timer expiration signal ST1 to adjust the duration of the switching period, and then adjust the duration of the off time Toff of the switch S1, so as to achieve that when the load of the switching converter 200 jumps, for example, from a light load to a heavy load, the off time of the switch S1 can be adjusted more quickly, thereby improving undershoot of the output voltage VOUT and improving the dynamic response speed of the switching converter.

Further, the time adjustment circuit 218 Is further configured to generate the adjustment signal Is based on an error between the feedback voltage VFB and a predetermined reference voltage VREF1 such that a duration of the off-time Toff Is related to the error.

In addition, the control circuit 210 is further configured to not adjust the generation timing of the timer expiration signal ST1 to maintain the duration of the switching period at a constant value when no jump occurs in the external load.

Furthermore, in the present embodiment, the single PULSE circuit 217 is configured to generate a narrow PULSE signal PULSE based on the acceleration mode signal TURBO. The OR gate OR is configured to OR the narrow PULSE signal PULSE with the timer expiration signal ST1 to generate the control signal ST.

As shown in fig. 4, the timer circuit 219 includes a reference voltage generation module 231, a ramp voltage generation module 232, and a comparator 233.

The reference voltage generation module 231 is configured to generate a reference voltage VREF2 that characterizes the duration of the off-time Toff. By way of example, the reference voltage generation module 231 includes ac small signal elements 205 and 206 connected in series between the supply voltage and ground, and a shunt resistor R1 connected between a node 221 between the ac small signal elements 205 and 206 and ground.

It will be appreciated that the reference voltage VREF2 in the present invention is formed based on the shunt of the ac small signal element 205 achieved by the parallel connection of the ac small signal element 206 and the shunt resistor R1.

Wherein the ac small signal element 205 is configured to provide a current I1 related to the input voltage VIN. For example, the current i1=gm2×vin, where GM2 is the transconductance of the ac small signal element 205. The ac small signal element 206 is configured to provide a current I2 related to the output voltage VOUT and a predetermined switching frequency. For example, the current i2=gm3×d×vout, where GM3 is the transconductance of the ac small signal element 206, D is the predetermined duty cycle of the switch S1, and d=1/fsw, fsw is the predetermined switching frequency.

As can be seen from this, the current level on the shunt resistor branch is gm2×vin-gm3×d×vout, in which case the reference voltage produced on shunt resistor R1, VREF 2= (gm2×vin-gm3×d×vout) ×r1.

The RAMP voltage generating module 232 is configured to output a gradually increasing RAMP voltage RAMP and start timing when the switch S1 is switched from the off state to the on state. By way of example, the ramp voltage generating module 232 includes an ac small signal element 207 and a ramp capacitor C1 connected in series between the supply voltage and ground, and a switch K1 connected between a first end of the ramp capacitor C1 and ground. Wherein the ac small signal element 207 is configured to start charging the RAMP capacitor C1 when the switch S1 is switched from the on state to the off state, to generate a gradually rising RAMP voltage RAMP at one end of the RAMP capacitor C1.

A positive input of the comparator 233 is configured to receive the RAMP voltage RAMP, a negative input of the comparator 233 is configured to receive the reference voltage VREF2, and the comparator 233 is configured to generate the timer expiration signal ST1 when the RAMP voltage RAMP rises to the reference voltage VREF 2. In addition, the timer expiration signal ST1 is also provided to the control terminal of the switch K1, and the switch K1 is configured to discharge the charge on the ramp capacitor C1 to ground based on the timer expiration signal ST1 and start the timing of the next cycle.

The time adjustment circuit 218 includes a transconductance amplifier 203 and a transmission gate unit 204. Wherein the transconductance amplifier 203 is configured to convert an error between the feedback voltage VFB and a reference voltage VREF1 into an error current. The transmission gate unit 204 Is connected between the output terminal of the transconductance amplifier 203 and the reference voltage generating module 241, and the transmission gate unit 204 Is configured to be turned on or off under the control of the acceleration mode signal TURBO to generate or not generate the adjustment signal Is based on the output of the transconductance amplifier 203. Illustratively, the pass gate unit 204 is configured to turn on based on an active (e.g., high) TURBO mode signal TURBO to adjust the magnitude of the current on the shunt resistance leg of the reference voltage generation module 231 based on the output of the transconductance amplifier 203 to adjust the time of generation of the timer expiration signal ST1.

In the present embodiment, the transconductance amplifier 203 includes NMOS transistors M1 to M6 and PMOS transistors M7 to M12. The drain and gate of the NMOS transistor M1 are connected to the gate of the NMOS transistor M2 and the bias current Ib, and the sources of the NMOS transistors M1 and M2 are connected to the ground potential. The drain and gate of the PMOS transistor M9 are connected to the gate of the PMOS transistor M10 and the drain of the NMOS transistor M2, and the sources of the PMOS transistors M9 and M10 are connected to the power supply voltage. The PMOS transistors M7 and M8 constitute an input pair transistor, the gate of the PMOS transistor M7 is connected to the reference voltage VREF1, the gate of the PMOS transistor M8 is connected to the feedback voltage VFB, and the sources of the PMOS transistors M7 and M8 are connected to the drain of the PMOS transistor M10. The gate and drain of the NMOS transistor M4 are connected to the gate of the NMOS transistor M3 and the drain of the PMOS transistor M7, and the sources of the NMOS transistors M3 and M4 are connected to the ground potential. The gate and drain of the NMOS transistor M5 are connected to the gate of the NMOS transistor M6 and the drain of the PMOS transistor M8, and the sources of the NMOS transistors M5 and M6 are connected to the ground potential. The sources of the PMOS transistors M11 and M12 are connected to a power supply voltage, the gate and drain of the PMOS transistor M11 are connected to the gate of the PMOS transistor M12 and the drain of the NMOS transistor M3, and the drain of the PMOS transistor M12 is connected to the drain of the NMOS transistor M6 and the output node of the transconductance amplifier 203.

In addition, the time adjustment circuit 218 of the present embodiment further includes a current bias unit formed by the ac small signal elements 201 and 202, where the current bias unit is configured to provide the bias current Ib to the transconductance amplifier 203 based on the input voltage VIN, the output voltage VOUT, and a predetermined switching frequency, so that the transconductance amplifier 203 has the same control degree on the reference voltage VREF2 under different output conditions, and avoids output fluctuations of the switching converter 200 under different working conditions. Illustratively, the ac small signal element 201 is configured to provide the current i1=gm2×vin in relation to an input voltage VIN, where GM2 is the transconductance of the ac small signal element 201. The ac small signal element 202 is configured to provide the current i2=gm3×d×vout in relation to the output voltage VOUT and a predetermined switching frequency, wherein GM3 is the transconductance of the ac small signal element 202, and d=1/fsw, fsw is the predetermined switching frequency. In addition, a node 223 between the ac small signal elements 201 and 202 provides the bias current Ib to the transconductance amplifier 203.

Fig. 5 is a waveform diagram illustrating an operation of the TURBO mode switching converter according to an embodiment of the present invention. Fig. 5 shows waveforms of the TURBO mode signal TURBO, the reference voltage VREF2, the RAMP voltage RAMP, the timer expiration signal ST1, the narrow PULSE signal PULSE, and the control signal ST, respectively. The principle of the TURBO mode switching converter of the present embodiment will be described with reference to fig. 3 to 5. As shown in fig. 5, in each switching cycle, when the switch S1 is switched from the on state to the off state, the ac small signal element 207 in the timer circuit 219 starts charging the RAMP capacitor C1 to generate a linearly rising RAMP voltage RAMP at one end of the RAMP capacitor C1, and when the RAMP voltage RAMP rises to the reference voltage VREF2, the timer circuit 219 generates a timer expiration signal ST1 of a narrow pulse.

Before time t1, the feedback voltage VFB is greater than the threshold voltage turbo_ref, the Turbo mode signal Turbo is at a low level, the transmission gate unit 204 in the time adjustment circuit 218 is turned off, and the reference voltage VREF2 is at a constant first voltage value, so that the generation time of the timer expiration signal ST1 is not changed. And since the TURBO mode signal TURBO is low, the output of the single pulse circuit 217 is also low, with the result that the waveform of the control signal ST follows the timer expiration signal ST1 so that the duration of the off time Toff of the switch S1 is a constant value.

At time t1, the load of the system rapidly jumps from a light load to a heavy load, the output voltage VOUT starts to drop, and when the feedback voltage VFB is smaller than the threshold voltage turbo_ref, the acceleration mode signal Turbo is flipped to a high level, and the single PULSE circuit 217 generates a narrow PULSE signal PULSE having a constant PULSE width according to the flipped acceleration mode signal Turbo, so that the control signal ST is rapidly generated to turn off the switch S2 and turn on the switch S1.

In addition, before the TURBO mode signal TURBO turns high, the current of the PMOS transistor M8 branch in the transconductance amplifier 203 increases due to the decrease of the feedback voltage VFB, the current of the PMOS transistor M7 branch decreases, so that the current in the PMOS transistor M12 decreases and the current in the NMOS transistor M6 increases as seen on the PMOS transistor M12 and NMOS transistor M6 side branches, and since the pass gate unit 203 is not yet turned on, the NMOS transistor M6 is adjusted to the linear region until the currents in the PMOS transistor and the NMOS transistor are equal.

When the TURBO mode signal TURBO turns high, the transfer gate unit 204 turns on, and at this time, the currents in the PMOS transistor M12, the NMOS transistor M6, and the ac small signal elements 205 and 206 in the reference voltage generating module 231 are redistributed, so that the current is drawn from the shunt resistor branch through the NMOS transistor M6, so that the reference voltage VREF2 is reduced, the duration of the switching period is shortened, and the off time Toff of the switch S1 is shortened.

Then, as the feedback voltage VFB increases, the current in the PMOS transistor M12 gradually increases, and the current in the NMOS transistor M6 gradually decreases, so that the reference voltage VREF2 also gradually returns to the previous first voltage value until, when the feedback voltage VFB is equal to the reference voltage VREF1, the current in the PMOS transistor M12 and the current in the NMOS transistor M6 are equal, as shown by time t2, the transconductance amplifier 203 no longer draws current from the shunt resistor branch of the reference voltage generating module 231, and the accelerating mode signal TURBO turns to a low level, the transmission gate unit 204 is turned off, and the duration of the switching period is recovered, that is, the off time Toff of the switch S1 is recovered to the length of normal operation.

Fig. 6 is a schematic waveform diagram of a TURBO mode switching converter according to an embodiment of the present invention when the load is changed. In fig. 6, VOUT is the output voltage of the switching converter, RAMP is the RAMP voltage output by the RAMP voltage generation module, VREF2 is the reference voltage characterizing the duration of the off time Toff, and IL is the inductor current flowing through the inductor L1 in the switching converter. As shown in fig. 6, when the load of the switching converter suddenly jumps from light load to heavy load, the output voltage VOUT drops, and as the output voltage VOUT drops, the reference voltage VREF2 correspondingly decreases, so that the off time Toff of the switch S1 can be shortened, and then the inductor current IL can be rapidly pulled up, so that undershoot occurring in the output voltage VOUT can be greatly reduced, and the dynamic response speed of the system is improved.

It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A control circuit of a TURBO mode switching converter, the switching converter comprising a first switch connected to a switching node, the control circuit configured to switch the first switch between a first and a second state based on an input voltage and an output voltage of the switching converter, the control circuit comprising:

a timer circuit configured to determine a duration and to generate a timer expiration signal upon expiration of the duration, the timer expiration signal being used to generate a first control signal;

logic circuitry configured to switch the first switch from a second state to a first state based on the first control signal;

a TURBO comparator configured to compare a feedback voltage of the output voltage with a predetermined threshold voltage and generate an acceleration mode signal when the feedback voltage is less than the threshold voltage; and

a time adjustment circuit configured to generate an adjustment signal to the timer circuit based on the acceleration mode signal, the adjustment signal for changing a time of generation of the timer expiration signal to adjust a length of the duration.

2. The control circuit of claim 1, further comprising:

A single pulse circuit configured to generate a narrow pulse signal based on the acceleration mode signal; and

an or gate configured to or the narrow pulse signal with the timer expiration signal to generate the first control signal.

3. The control circuit of claim 1, wherein the time adjustment circuit is further configured to:

the adjustment signal is generated based on an error between the feedback voltage and a predetermined first reference voltage such that a length of the duration is related to the error.

4. The control circuit of claim 1, wherein the timer circuit comprises:

a reference voltage generation module configured to generate a second reference voltage that characterizes the duration;

a ramp voltage generation module configured to output a gradually rising ramp voltage and start timing after the first switch is switched from the second state to the first state; and

a comparator configured to generate the timer expiration signal when the ramp voltage rises to the second reference voltage,

wherein the adjustment signal changes the generation time of the timer expiration signal by changing the second reference voltage.

5. The control circuit of claim 4, wherein the reference voltage generation module comprises:

a first ac small signal element and a second ac small signal element connected in series between a power supply voltage and a ground potential, the first ac small signal element configured to provide a first current related to the input voltage, the second ac small signal element configured to provide a second current related to the output voltage and a predetermined switching frequency; and

a shunt resistor connected in parallel between two ends of the second alternating current small signal element,

wherein the shunt resistor is configured to generate the second reference voltage at a first end thereof based on the first current and the second current, and the adjustment signal changes the second reference voltage by drawing a current at the first end of the shunt resistor.

6. The control circuit of claim 4, wherein the ramp voltage generation module comprises:

a third alternating current small signal element and a ramp capacitor connected in series between the power supply voltage and the ground potential; and

a second switch connected in parallel between both ends of the ramp capacitor, wherein the on and off of the second switch is controlled based on the timer expiration signal.

7. The control circuit of claim 3, wherein the time adjustment circuit comprises:

a transconductance amplifier configured to convert an error between the feedback voltage and the first reference voltage into an error current; and

and a transmission gate unit configured to be turned on or off in response to the acceleration mode signal and to generate the adjustment signal based on an output of the transconductance amplifier when turned on.

8. The control circuit of claim 7, wherein the time adjustment circuit further comprises:

a current bias unit configured to generate a bias current to the transconductance amplifier based on the input voltage, the output voltage, and a predetermined switching frequency,

wherein the current bias unit includes:

a fourth alternating current small signal element and a fifth alternating current small signal element connected in series between a supply voltage and a ground potential, the fourth alternating current small signal element configured to provide a first current related to the input voltage, the fifth alternating current small signal element configured to provide a second current related to the output voltage and a predetermined switching frequency,

wherein the intermediate nodes of the fourth alternating current small signal element and the fifth alternating current small signal element are used for providing the bias current.

9. The control circuit of claim 1, wherein the TURBO comparator is implemented by a hysteresis comparator.

10. The control circuit of claim 1, further comprising:

an error amplifier configured to obtain an error amplified signal between a feedback voltage of the output voltage and a reference voltage;

a current detection circuit configured to obtain a current detection signal representative of an inductor current peak of the switching converter; and

a peak comparator configured to compare the error amplified signal with the current detection signal to obtain a second control signal,

wherein the logic circuit is configured to switch the first switch from a first state to a second state based on the second control signal.

11. A TURBO mode switching converter comprising:

an input terminal for receiving an input voltage;

an output terminal connected to the load for providing an output voltage;

a power circuit coupled to the input and output terminals, the power circuit employing at least one inductive element and at least a first switch to regulate current provided to the load; and

the control circuit of any of claims 1-10, connected to the first switch and configured to switch the first switch between first and second states based on the input voltage and the output voltage.