CN117117012A - An avalanche photodiode and its manufacturing method - Google Patents

Abstract

The invention relates to the field of chip manufacturing technology, and in particular to an avalanche photodiode and a manufacturing method thereof. The avalanche photodiode has at least a P-type contact layer, a basic functional layer and an N-type contact layer stacked on a semi-insulating substrate. The basic functional layer An N-type electric field control layer and an I-type edge electric field buffer layer are also provided between the N-type contact layer and the semi-insulating substrate to form a first step on the side periphery of the P-type contact layer. A second step is formed on the side circumference of the basic functional layer, the N-type electric field control layer and the I-type edge electric field buffer layer, and are covered with a first passivation layer, a second passivation layer and a third passivation layer in sequence. The invention can reduce capacitance and increase bandwidth. In addition, in terms of technology, the problem of undercutting during the corrosion process can be solved and the reliability of the entire chip can be improved.

Description

An avalanche photodiode and its manufacturing method

Technical field

The present invention relates to the field of chip manufacturing technology, and in particular to an avalanche photodiode and a manufacturing method thereof.

Background technique

In optical fiber communication systems not exceeding 10Gbps, avalanche photodiodes (APDs) are widely used as optical receiver chips because they have internal gain and can achieve higher sensitivity and longer-distance signal transmission. However, in the design process of avalanche photodiodes, all of its structures cannot be considered unilaterally, but its responsivity, bandwidth and gain need to be comprehensively considered. Among them, responsivity and bandwidth will restrain each other. Increasing bandwidth requires reducing the thickness of the absorption layer and multiplication layer, which in turn will reduce the responsivity and increase the capacitance, which in turn will reduce the bandwidth. Therefore, when the optical fiber communication system develops to 100G and 400G, the structure of the avalanche photodiode in the 10Gbps system is no longer applicable. For this requirement, the traditional method is to use the evanescent wave detector structure and use waveguide transmission to solve the optical path and Crosstalk in circuits. However, this structure often results in a large difference in responsivity between TE and TM modes, causing coupling problems. Moreover, the reliability requirements of the waveguide mesa structure are difficult to match with traditional vertical incidence detectors.

In addition, for the traditional avalanche photodiode structure, the epitaxial structure is: N+-I-P-I-P+ structure. It uses molecular beam epitaxial deposition (MBE) on an InP-doped Fe-doped semi-insulating substrate to sequentially stack an N-type InP contact layer, an I-type InAlAs multiplication layer, a P-type InP electric field control layer, an I-type InGaAs light absorption layer, I-type InAlAs cladding layer, I-type InP cap layer and P-type InGaAs contact layer. This structure can be used in 100G and 400G optical fiber communication systems, but it still has some defects, such as the large PN junction area and insufficient distance between P+N+ junctions, resulting in large capacitance and reduced bandwidth. In addition, there are also some problems in the manufacturing process of existing avalanche photodiodes. For example, undercutting is prone to occur during the corrosion process; the passivation layer adopts the traditional sulfurization process, and the surface formed is not delicate and precise enough.

Therefore, in today's 100G and 400G systems, new avalanche photodiode structures and manufacturing processes are urgently needed to solve the above problems.

In view of this, overcoming the above-mentioned defects in the prior art is an urgent problem to be solved in this technical field.

Contents of the invention

One of the purposes of the present invention is based on the problems in the prior art that the PN junction area of the avalanche photodiode is large and the distance between the P+N+ junctions is insufficient, resulting in large capacitance and reduced bandwidth, and the manufacturing process is prone to undercutting and erosion. To solve the problem that the formed surface is not delicate enough, an avalanche photodiode and a manufacturing method thereof are provided. The avalanche photodiode designs an APD epitaxial wafer of InAlAs/InGaAs material and adopts a special P+-I-N-I-P-I-N+ structure. Through this special structure, the size of the active area can be reduced, the capacitance can be reduced, and the bandwidth can be increased. In addition, in terms of technology, a graded mesa corrosion process from outside to in is adopted to solve the problem of undercutting during the corrosion process. Two electroless plating self-assembly methods are used to form a cadmium sulfide passivation layer to cover the mesa side walls, which improves the efficiency of the mesa. The reliability of the entire chip.

The present invention is implemented as follows:

In a first aspect, the present invention provides an avalanche photodiode, in which at least a P-type contact layer, a basic functional layer and an N-type contact layer are stacked on a semi-insulating substrate, and between the basic functional layer and the N-type contact layer An N-type electric field control layer and an I-type edge electric field buffer layer are also provided, wherein the semi-insulating substrate and the side periphery of the P-type contact layer form a first step, and the P-type contact layer and the basic function A second step is formed on the side periphery of the layer. The side periphery of the basic functional layer, the N-type electric field control layer and the I-type edge electric field buffer layer are covered with a first passivation layer, a second passivation layer and a third passivation layer in sequence. .

Further, the basic functional layer includes an I-type light absorption layer, a P-type electric field control layer, and an I-type multiplication layer. Specifically, the P-type contact layer, the I-type light absorption layer, and the P-type electric field control layer layer, the I-type multiplication layer, the N-type electric field control layer, the I-type edge electric field buffer layer, and the N-type contact layer are sequentially stacked on the semi-insulating substrate through molecular beam vapor epitaxial deposition. .

Further, the N-type contact layer is disposed on the upper surface of the I-type edge electric field buffer layer and has a ring structure, and the P-type electric field control layer, the I-type multiplication layer, the N-type electric field control layer, The side periphery of the I-type edge electric field buffer layer and the side periphery of the I-type light absorption layer form a third step, the first passivation layer covers the third step, and the second passivation layer covers On the first passivation layer, the first step and part of the second step, the third passivation layer covers the second passivation layer.

Further, the bottom of the semi-insulating substrate is provided with a silicon nitride dielectric reflective layer and a highly reflective metal layer in sequence, an N-electrode metal contact layer is led out on the N-type contact layer, and a P-electrode metal is led out on the P-type contact layer. contact layer, and the P electrode metal contact layer extends to the upper surface of the third passivation layer.

Further, the semi-insulating substrate includes an InP-doped Fe semi-insulating substrate, the P-type contact layer includes a P-type InGaAs contact layer, the I-type light absorption layer includes an I-type InGaAs light absorption layer, and the P-type The electric field control layer includes a P-type InAlAs electric field control layer, the I-type multiplication layer includes an I-type InAlAs multiplication layer, the N-type electric field control layer includes an N-type InAlAs electric field control layer, and the I-type edge electric field buffer layer includes an I-type InP edge electric field buffer layer, the N-type contact layer includes an N-type InGaAs contact layer, the first passivation layer includes a CdS passivation layer, the second passivation layer includes a BCB passivation layer, and the third passivation layer The passivation layer includes SiN anti-reflective passivation layer.

Further, the doping concentration of the P-type InGaAs contact layer is 1e19cm ^-3 and the thickness is 0.5 μm; the doping concentration of the I-type InGaAs light absorption layer is less than 5e15cm ^-3 and the thickness is in the range of 0.4 to 0.6 μm; The P-type InAlAs electric field control layer has a doping concentration of 1e18cm ^-3 and a thickness in the range of 0.32 to 0.35 μm; the I-type InAlAs multiplication layer has a doping concentration of less than 5e15cm ^-3 and a thickness in the range of 0.2 to 0.3 μm. ; The N-type InAlAs electric field control layer has a doping concentration of 1e18cm ^-3 and a thickness in the range of 0.32 to 0.35μm; the I-type InP edge electric field buffer layer has a doping concentration of less than 5e15cm ^-3 and a thickness of 1 to 1.5 Within the range of μm; the doping concentration of the N-type InGaAs contact layer is less than 1e19cm ^-3 and the thickness is 0.15μm.

In a second aspect, the present invention also provides a method for manufacturing an avalanche photodiode, which method includes:

The P-type contact layer, I-type light absorption layer, P-type electric field control layer, I-type multiplication layer, N-type electric field control layer, and I-type edge electric field buffer layer are sequentially stacked on the semi-insulating substrate through molecular beam vapor epitaxial deposition. , N-type contact layer;

The annular N-type contact layer is formed through photolithography and etching processes, and the first step, the second step and the third step of the cylindrical platform are formed through photolithography and etching processes without removing the glue;

The first passivation layer, the second passivation layer and the third passivation layer are formed through photolithography, chemical plating process, passivation process, low-temperature plasma enhanced chemical vapor deposition and etching process under the condition of removing the glue, and are exposed P-type contact layer and N-type contact layer;

Using electron beam evaporation and stripping processes, the P electrode metal contact layer and N electrode metal contact layer are formed;

The silicon nitride dielectric reflective layer and highly reflective metal layer are formed through heat treatment, thinning polishing, enhanced plasma vapor deposition and electron beam evaporation processes;

The wafer is cleaved to form a 300X300μm ² avalanche photodiode chip.

Further, forming the annular N-type contact layer through photolithography and etching processes, and forming the first step, the second step and the third step of the cylindrical platform through photolithography and etching processes without removing glue specifically include: :

A ring-shaped N-type contact layer is formed through photolithography and etching processes;

The first step is formed through photolithography and etching processes. Specifically: use photoresist as a masking film, use hydrobromic acid, saturated bromine water and a solution with a water ratio of 1:1:1 to etch the I-type edge electric field buffer layer and N Type electric field control layer, I-type multiplication layer, P-type electric field control layer, I-type light absorption layer, P-type contact layer, and finally stop in the semi-insulating substrate to form the first step;

Without removing the glue, continue to form the second step through photolithography and etching processes. Specifically: use photoresist as a masking film, and use a solution of hydrobromic acid, saturated bromine water and water with a ratio of 1:1:1 to etch the I-type edge. The electric field buffer layer, N-type electric field control layer, I-type multiplication layer, P-type electric field control layer, and I-type light absorption layer finally stop at the P-type contact layer to form the second step;

Without removing the glue, continue to form the third step through photolithography and etching processes. Specifically: use photoresist as a masking film, and use a solution of hydrobromic acid, saturated bromine water and water with a ratio of 1:1:1 to etch the I-type edge. The electric field buffer layer, N-type electric field control layer, I-type multiplication layer, and P-type electric field control layer finally stop in the I-type light absorption layer to form the third step.

Further, the first passivation layer, the second passivation layer, and the third passivation layer are formed by photolithography, chemical plating process, passivation process, low-temperature plasma enhanced chemical vapor deposition, and etching process under the condition of removing the glue. layer, and expose the P-type contact layer and N-type contact layer, including:

Remove the glue and form the first passivation layer through photolithography and chemical plating processes. Specifically: first cover the entire epitaxial wafer surface with photoresist through the photolithography process, leaking out the side walls of the cylindrical platform; and then place it in an ammonium sulfide solution. 40-60min, then place it in a cadmium sulfate solution; blow dry, remove the glue, and finally form a 10-20nm CdS passivation layer on the side wall;

The second passivation layer is formed through photolithography and passivation processes. Specifically: the photosensitive BCB is spin-coated on the surface of the epitaxial wafer, and then covered on the side walls and surroundings of the cylindrical platform through the photolithography process, and then in a nitrogen atmosphere, Passivate at 250 degrees Celsius for 2 hours to form a BCB passivation layer;

The third passivation layer is formed by low-temperature plasma enhanced chemical vapor deposition. Specifically: deposited by low-temperature plasma enhanced chemical vapor deposition. A thick silicon nitride dielectric layer to form a SiN anti-reflective passivation layer;

The P-type contact layer and N-type contact layer are exposed through photolithography and etching processes.

Further, the formation of the silicon nitride dielectric reflective layer and the highly reflective metal layer through heat treatment, thinning polishing, enhanced plasma vapor deposition and electron beam evaporation processes specifically includes:

Heat the epitaxial wafer at 300-360°C for 1-3 minutes;

The epitaxial wafer is thinned and polished to 150μm, and the polished surface of the epitaxial wafer is deposited using enhanced plasma vapor deposition. Thick silicon nitride dielectric reflective layer;

An electron beam evaporation process is used to form a Ti/Pt/Au highly reflective metal layer on the silicon nitride dielectric reflective layer, where the Ti thickness is Pt thickness is/> Au thickness is/>

Compared with the existing technology, the beneficial effect of the present invention is that by designing an APD epitaxial wafer of InAlAs/InGaAs material and adopting a special P+-I-N-I-P-I-N+ structure, the size of the active area can be reduced and the capacitance can be reduced through this special structure. , improve bandwidth. In addition, in terms of technology, a graded mesa corrosion process from outside to in is adopted to solve the problem of undercutting during the corrosion process. Two electroless plating self-assembly methods are used to form a cadmium sulfide passivation layer to cover the mesa side walls, which improves the efficiency of the mesa. The reliability of the entire chip.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of the epitaxial structure of an avalanche photodiode provided in Embodiment 1 of the present invention;

Figure 2 is a schematic cross-sectional structural diagram of an avalanche photodiode provided in Embodiment 1 of the present invention;

Figure 3 is a schematic diagram of the electric field of the avalanche photodiode of the present invention provided in Embodiment 2 of the present invention;

Figure 4 is a schematic diagram of the electric field of a traditional avalanche photodiode provided in Embodiment 2 of the present invention;

Figure 5 is a flow chart of a manufacturing method of an avalanche photodiode provided in Embodiment 3 of the present invention;

Figure 6 is a detailed flow chart of step 200 provided in Embodiment 3 of the present invention;

Figure 7 is a detailed flow chart of step 300 provided in Embodiment 3 of the present invention;

Figure 8 is a detailed flow chart of step 500 provided in Embodiment 3 of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

In the description of the present invention, the terms "inside", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", etc. indicate an orientation or positional relationship based on the drawings. The illustrated orientation or positional relationship is only for convenience of describing the present invention and does not require that the present invention must be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

Example 1

As shown in Figure 1, with reference to Figure 2, Embodiment 1 of the present invention provides an avalanche photodiode, in which at least a P-type contact layer 2, a basic functional layer and an N-type contact layer 8 are stacked on a semi-insulating substrate 1. An N-type electric field control layer 6 and an I-type edge electric field buffer layer 7 are also provided between the basic functional layer and the N-type contact layer 8, wherein the sides of the semi-insulating substrate 1 and the P-type contact layer 2 A first step is formed around the circumference of the P-type contact layer 2 and the basic functional layer forms a second step. The side circumferences of the basic functional layer, the N-type electric field control layer 6 and the I-type edge electric field buffer layer 7 form a second step. It is covered with the first passivation layer 30, the second passivation layer 40, and the third passivation layer 50 in sequence.

In this preferred embodiment, the basic functional layer includes an I-type light absorption layer 3, a P-type electric field control layer 4, and an I-type multiplication layer 5. Specifically, as shown in Figure 1, the P-type contact layer 2, The I-type light absorption layer 3, the P-type electric field control layer 4, the I-type multiplication layer 5, the N-type electric field control layer 6, the I-type edge electric field buffer layer 7, and the N-type contact Layers 8 are sequentially stacked on the semi-insulating substrate 1 through molecular beam vapor epitaxial deposition to form the epitaxial structure of the avalanche photodiode, that is, a special P+-I-N-I-P-I-N+ structure.

Referring to Figure 2, in this preferred embodiment, the N-type contact layer 8 is provided on the upper surface of the I-type edge electric field buffer layer 7 and has a ring structure; the P-type electric field control layer 4, the I-type multiplication layer The side peripheries of layer 5, the N-type electric field control layer 6, the I-type edge electric field buffer layer 7 and the I-type light absorption layer 3 form a third step, and the first passivation layer 30 covers On the third step, the second passivation layer 40 covers the first passivation layer 30, the first step and part of the second step, and the third passivation layer 50 covers the third step. on the second passivation layer 40 . Specifically, the first step in this embodiment refers to the upper surface of the semi-insulating substrate 1 that leaks more than the P-type contact layer 2 and the sidewalls of the P-type contact layer 2, as well as the P-type contact layer. The side wall of the semi-insulating substrate 1 where the 2 side walls are connected; the second step in this embodiment refers to the upper surface of the P-type contact layer 2 that leaks more than the I-type light absorption layer 3 and the I-type light absorption The lower half sidewall of layer 3; the second step in this embodiment refers to the relative position of the I-type light absorption layer 3 to the P-type electric field control layer 4, the I-type multiplication layer 5, the N-type electric field control layer 6, and the I-type edge. The upper surface of the mostly leaked portion of the electric field buffer layer 7 and the upper half sidewall of the I-type light absorption layer 3, as well as the P-type electric field control layer 4, the I-type multiplication layer 5, the N-type electric field control layer 6, and the I-type edge electric field The side walls of the buffer layer 7. In this embodiment, the appearance of each layer after forming three steps is similar to a three-layer cylindrical cone. The side walls of the cylindrical cone are covered with the first passivation layer 30 , and most of the surface of the first passivation layer 30 and the chip surface The area is covered with the second passivation layer 40, and the surface of the second passivation layer 40 and the photosensitive area in the center of the chip are covered with the third passivation layer 50.

In this preferred embodiment, the bottom of the semi-insulating substrate 1 is provided with a silicon nitride dielectric reflective layer 20 and a high-reflective metal layer 10 in sequence. In addition, an N electrode metal contact layer 70 is drawn on the N-type contact layer 8. A P electrode metal contact layer 60 is drawn on the P-type contact layer 2, and the P electrode metal contact layer 60 extends to the upper surface of the third passivation layer 50. Preferably, the P electrode metal contact layer 60 and N The height of the electrode metal contact layer 70 is uniform.

In this preferred embodiment, the semi-insulating substrate 1 includes an InP-doped Fe semi-insulating substrate, the P-type contact layer 2 includes a P-type InGaAs contact layer, and the I-type light absorbing layer 3 includes an I-type InGaAs light absorbing layer. Absorption layer, the P-type electric field control layer 4 includes a P-type InAlAs electric field control layer, the I-type multiplication layer 5 includes an I-type InAlAs multiplication layer, and the N-type electric field control layer 6 includes an N-type InAlAs electric field control layer, so The I-type edge electric field buffer layer 7 includes an I-type InP edge electric field buffer layer, the N-type contact layer 8 includes an N-type InGaAs contact layer, the first passivation layer 30 includes a CdS passivation layer, and the second passivation layer The passivation layer 40 includes a BCB passivation layer, and the third passivation layer 50 includes a SiN anti-reflective passivation layer.

Specifically, in this preferred embodiment, the doping concentration of the P-type InGaAs contact layer is 1e19cm ^-3 and the thickness is 0.5 μm; the doping concentration of the I-type InGaAs light absorption layer is less than 5e15cm ^-3 and the thickness is 0.5μm. Within the range of 0.4 to 0.6 μm; the doping concentration of the P-type InAlAs electric field control layer is 1e18cm ^-3 and the thickness is within the range of 0.32 to 0.35 μm; the doping concentration of the I-type InAlAs multiplication layer is less than 5e15cm ^-3 and the thickness In the range of 0.2 to 0.3 μm; the N-type InAlAs electric field control layer has a doping concentration of 1e18cm ^-3 and a thickness in the range of 0.32 to 0.35 μm; the I-type InP edge electric field buffer layer has a doping concentration of less than 5e15cm ^{- 3.} The thickness is in the range of 1 to 1.5 μm; the doping concentration of the N-type InGaAs contact layer is less than 1e19cm ^-3 and the thickness is 0.15 μm.

To sum up, the above structural design of this embodiment adopts a special P+-I-N-I-P-I-N+ structure by designing an APD epitaxial wafer made of InAlAs/InGaAs material. This special structure can reduce the size of the active area and reduce the capacitance. Increase bandwidth.

Example 2

Based on the avalanche photodiode provided in the above-mentioned Embodiment 1, this Embodiment 2 compares it with an avalanche photodiode of a traditional structure through the difference in its electric field to better illustrate the advantages of the avalanche photodiode provided by the embodiment of the present invention. .

As shown in Figure 3, it is a schematic diagram of the electric field of an avalanche photodiode provided by an embodiment of the present invention. It is to sequentially stack a P-type InGaAs contact layer (P-type contact layer 2) and an I-type InGaAs light absorption layer on an InP-doped Fe semi-insulating substrate (semi-insulating substrate 1) using the molecular beam vapor epitaxy deposition method (MBE). layer (I-type light absorption layer 3), P-type InAlAs electric field control layer (P-type electric field control layer 4), I-type InAlAs multiplication layer (I-type multiplication layer 5), N-type InAlAs electric field control layer (N-type electric field control layer 6), I-type InP edge electric field buffer layer (I-type edge electric field buffer layer 7) and N-type InGaAs contact layer (N-type contact layer 8). The epitaxial structure of the embodiment of the present invention is a P+-I-N-I-P-I-N+ structure.

As shown in Figure 4, it is a schematic diagram of the electric field of a traditional avalanche photodiode. The method is to sequentially stack an N-type InP contact layer 12, an I-type InAlAs multiplication layer 13, a P-type InP electric field control layer 14, and an I-type InGaAs on an InP Fe-doped semi-insulating substrate 11 using a molecular beam vapor epitaxy deposition method (MBE). The light absorption layer 15, the I-type InAlAs cladding layer (not shown in the figure for the convenience of comparison), the I-type InP cap layer (not shown in the figure for the convenience of comparison) and the P-type InGaAs contact layer 16. The traditional epitaxial structure is N+-I-P-I-P+ structure.

Through comparison, it can be found that the active area of the embodiment of the present invention is in the upper part of the dotted trapezoidal area in the figure, while the traditional active area is in the lower part of the dotted trapezoidal area in the figure. In this way, when the trapezoids are the same, The area of the active area in the upper part of the trapezoid will naturally be smaller. That is to say, this application can reduce the area of the active area compared to the traditional technology. Furthermore, with reference to the direction of the electric field and the direction of the intensity of the electric field, under the same active area area, the present invention implements The structure provided by the example can effectively reduce the PN junction area, thereby reducing the capacitance and increasing the bandwidth; in addition, the structure of the embodiment of the present invention has more N-type InAlAs electric field control layer and I-type InP edge electric field buffer layer than the traditional structure, increasing P The distance between +N+ junctions reduces capacitance and increases bandwidth.

Example 3

Based on the structural description of the avalanche photodiode provided by the present invention in Embodiment 1, this Embodiment 3 also provides a corresponding manufacturing method of the avalanche photodiode.

As shown in FIG. 5 , it is a flow chart of the manufacturing method of the avalanche photodiode provided in Embodiment 3. The production method includes the following process steps.

Step 100: Stack P-type contact layer 2, I-type light absorption layer 3, P-type electric field control layer 4, I-type multiplication layer 5, and N-type electric field control layer in sequence on the semi-insulating substrate 1 by molecular beam vapor epitaxy deposition. Layer 6, I-type edge electric field buffer layer 7, N-type contact layer 8. It should be noted that the corresponding labels of each layer in this embodiment may refer to Figure 2 of Embodiment 1.

Step 200: Form the annular N-type contact layer 8 through photolithography and etching processes, and form the first step, the second step and the third step of the cylindrical platform through photolithography and etching processes without removing the glue.

Step 300: Form the first passivation layer 30, the second passivation layer 40, The third passivation layer 50 exposes the P-type contact layer 2 and the N-type contact layer 8 .

Step 400: Use electron beam evaporation and lift-off processes to form the P electrode metal contact layer 60 and the N electrode metal contact layer 70.

Step 500: Form the silicon nitride dielectric reflective layer 20 and the highly reflective metal layer 10 through heat treatment, thinning polishing, enhanced plasma vapor deposition (PECVD) and electron beam evaporation processes.

Step 600: Cleave the wafer to form an avalanche photodiode chip of 300×300 μm ² .

As shown in Figure 6, in this preferred embodiment, the above step 200 can be specifically refined into the following steps:

Step 201: Form a ring-shaped N-type contact layer 8 (ie, N-type InGaAs contact layer) through photolithography and etching processes.

Step 202: Form the first step through photolithography and etching processes. Specifically: use photoresist as a masking film, use hydrobromic acid, saturated bromine water and a solution with a water ratio of 1:1:1 to corrode the I-type edge electric field buffer layer 7 (that is, the I-type InP edge electric field buffer layer), N-type electric field control layer 6 (that is, N-type InAlAs electric field control layer), I-type multiplication layer 5 (that is, I-type InAlAs multiplication layer), P-type electric field control layer 4 (that is, P-type InAlAs electric field control layer), I Type light absorption layer 3 (i.e., I-type InGaAs light absorption layer), P-type contact layer 2 (i.e., P-type InGaAs contact layer), and finally stop at the semi-insulating substrate 1 (i.e., InP-doped Fe-doped semi-insulating substrate) in to form the first step.

Step 203: Without removing the glue, continue to form the second step through photolithography and etching processes. Specifically: use photoresist as a masking film, use hydrobromic acid, saturated bromine water and a solution with a water ratio of 1:1:1 to corrode the I-type edge electric field buffer layer 7, N-type electric field control layer 6, and I-type multiplication layer 5. The P-type electric field control layer 4 and the I-type light absorption layer 3 finally stop at the P-type contact layer 2 to form a second step.

Step 204: Without removing the glue, continue to form the third step through photolithography and etching processes. Specifically: use photoresist as a masking film, use hydrobromic acid, saturated bromine water and a solution with a water ratio of 1:1:1 to corrode the I-type edge electric field buffer layer 7, N-type electric field control layer 6, and I-type multiplication layer 5. The P-type electric field control layer 4 finally stops in the I-type light absorption layer 3 to form a third step.

In the above steps, when etching the first, second, and third steps to form a cylindrical platform, the largest step is etched first, and the smallest step is etched last. The photoresist is not removed during the entire photolithography and etching process. Compared with the traditional method, the small steps are etched first. , and finally corrodes a large step, which can well protect the drilling site during the corrosion process.

As shown in Figure 7, in this preferred embodiment, the above step 300 can be specifically refined into the following steps:

Step 301: Remove the glue, and form the first passivation layer 30 through photolithography and chemical plating processes. Specifically: first, cover the entire epitaxial wafer surface with photoresist through the photolithography process, leaking out the side walls of the cylindrical platform; then place it in an ammonium sulfide solution for 40-60 minutes, and then place it in a cadmium sulfate solution; blow dry and remove glue, and finally a CdS passivation layer of 10-20 nm is formed on the side wall, that is, the first passivation layer 30. This layer process is formed by two-step electroless plating and self-assembly, which can form a denser surface than the traditional vulcanization process.

Step 302: Form the second passivation layer 40 through photolithography and passivation processes. Specifically: spin-coat the photosensitive BCB on the surface of the epitaxial wafer, then cover it on the side walls and surroundings of the cylindrical platform through the photolithography process, and then passivate it in a nitrogen atmosphere at 250 degrees Celsius for 2 hours to form a BCB passivation layer , that is, the second passivation layer 40.

Step 303: Form the third passivation layer 50 by low-temperature plasma enhanced chemical vapor deposition. Specific: Deposited by low-temperature plasma enhanced chemical vapor deposition Thick silicon nitride dielectric layer to form a SiN anti-reflective passivation layer, that is, the third passivation layer 50 .

Step 304: Expose the P-type contact layer 2 and the N-type contact layer 8 through photolithography and etching processes.

As shown in Figure 8, in this preferred embodiment, the above step 500 can be specifically refined into the following steps:

Step 501: Heat-treat the epitaxial wafer at 300-360°C for 1-3 minutes.

Step 502: Thin and polish the epitaxial wafer to about 150 μm, and deposit it on the polished surface of the epitaxial wafer using enhanced plasma vapor deposition. Thick silicon nitride dielectric reflective layer 20.

Step 503: Use an electron beam evaporation process to form a Ti/Pt/Au highly reflective metal layer 10 on the silicon nitride dielectric reflective layer 20, where the Ti thickness is Pt thickness is/> Au thickness is/>

It should be noted that the data in all the above steps can have a certain error allowed in the field, and is not completely limited to precise data.

Through the above steps, compared with the existing technology, the manufacturing process of this embodiment adopts a graded table-type corrosion process from the outside to the inside, which solves the problem of undercutting during the corrosion process, and uses two electroless plating self-assembly methods to form cadmium sulfide passivation. The chemical layer covers the side walls of the mesa, improving the reliability of the entire chip.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (10)

1. The avalanche photodiode is characterized in that at least a P-type contact layer (2), a basic function layer and an N-type contact layer (8) are stacked on a semi-insulating substrate (1), an N-type electric field control layer (6) and an I-type edge electric field buffer layer (7) are further arranged between the basic function layer and the N-type contact layer (8), a first step is formed on the side periphery of the semi-insulating substrate (1) and the P-type contact layer (2), a second step is formed on the side periphery of the P-type contact layer (2) and the basic function layer, and a first passivation layer (30), a second passivation layer (40) and a third passivation layer (50) are sequentially covered on the side periphery of the basic function layer, the N-type electric field control layer (6) and the I-type edge electric field buffer layer (7).

2. The avalanche photodiode according to claim 1, characterized in that the basic functional layer comprises an I-type light absorbing layer (3), a P-type electric field control layer (4), an I-type multiplication layer (5), in particular the P-type contact layer (2), the I-type light absorbing layer (3), the P-type electric field control layer (4), the I-type multiplication layer (5), the N-type electric field control layer (6), the I-type edge electric field buffer layer (7), the N-type contact layer (8) are stacked on the semi-insulating substrate (1) in sequence by means of molecular beam weather epitaxial deposition.

3. The avalanche photodiode according to claim 2, wherein the N-type contact layer (8) is disposed on the upper surface of the I-type edge electric field buffer layer (7) and has a ring structure, the P-type electric field control layer (4), the I-type multiplication layer (5), the N-type electric field control layer (6), the side periphery of the I-type edge electric field buffer layer (7) and the side periphery of the I-type light absorption layer (3) form a third step, the first passivation layer (30) is covered on the third step, the second passivation layer (40) is covered on the first passivation layer (30), the first step and a part of the second step, and the third passivation layer (50) is covered on the second passivation layer (40).

4. The avalanche photodiode according to any one of claims 1 to 3, wherein a silicon nitride dielectric reflective layer (20) and a highly reflective metal layer (10) are sequentially arranged at the bottom of the semi-insulating substrate (1), an N electrode metal contact layer (70) is led out on the N type contact layer (8), a P electrode metal contact layer (60) is led out on the P type contact layer (2), and the P electrode metal contact layer (60) extends to the upper surface of the third passivation layer (50).

5. An avalanche photodiode according to any of claims 2-3, wherein the semi-insulating substrate (1) comprises an InP-doped Fe semi-insulating substrate, the P-type contact layer (2) comprises a P-type InGaAs contact layer, the I-type light absorbing layer (3) comprises an I-type InGaAs light absorbing layer, the P-type electric field control layer (4) comprises a P-type inaias electric field control layer, the I-type multiplication layer (5) comprises an I-type inaias multiplication layer, the N-type electric field control layer (6) comprises an N-type inaias electric field control layer, the I-type edge electric field buffer layer (7) comprises an I-type InP edge electric field buffer layer, the N-type contact layer (8) comprises an N-type InGaAs contact layer, the first passivation layer (30) comprises a CdS passivation layer, the second passivation layer (40) comprises a BCB passivation layer, and the third passivation layer (50) comprises a SiN antireflective passivation layer.

6. The avalanche photodiode according to claim 5 wherein said P-type InGaAs contact layer has a doping concentration of 1e19cm ^-3 Thickness is 0.5 μm; the doping concentration of the I type InGaAs light absorption layer is less than 5e15cm ^-3 A thickness in the range of 0.4 to 0.6 μm; the doping concentration of the P-type InAlAs electric field control layer is 1e18cm ^-3 A thickness in the range of 0.32 to 0.35 μm; the doping concentration of the I-type InAlAs multiplication layer is less than 5e15cm ^-3 A thickness in the range of 0.2 to 0.3 μm; the doping concentration of the N-type InAlAs electric field control layer is 1e18cm ^-3 Thickness of (a)In the range of 0.32 to 0.35 μm; the doping concentration of the I-type InP fringe electric field buffer layer is less than 5e15cm ^-3 A thickness in the range of 1 to 1.5 μm; the doping concentration of the N-type InGaAs contact layer is less than 1e19cm ^-3 The thickness was 0.15. Mu.m.

7. A method of fabricating an avalanche photodiode, comprising:

a P-type contact layer (2), an I-type light absorption layer (3), a P-type electric field control layer (4), an I-type multiplication layer (5), an N-type electric field control layer (6), an I-type edge electric field buffer layer (7) and an N-type contact layer (8) are sequentially stacked on a semi-insulating substrate (1) in a molecular beam weather epitaxial deposition mode;

forming an annular N-type contact layer (8) through a photoetching and corrosion process, and forming a first step, a second step and a third step of the cylinder platform through the photoetching and corrosion process under the condition of not removing photoresist;

forming a first passivation layer (30), a second passivation layer (40) and a third passivation layer (50) under the photoresist removal condition by means of photoetching, chemical plating process, passivation process, low-temperature plasma enhanced chemical vapor deposition and etching process, and exposing the P-type contact layer (2) and the N-type contact layer (8);

forming a P electrode metal contact layer (60) and an N electrode metal contact layer (70) by adopting an electron beam evaporation and stripping process;

forming a silicon nitride medium reflecting layer (20) and a high-reflection metal layer (10) through heat treatment, thinning and polishing and an enhanced plasma vapor deposition mode and an electron beam evaporation process;

cleaving the wafer to form 300X300 μm ² Avalanche photodiode chip of (c).

8. The method for manufacturing an avalanche photodiode according to claim 7, wherein the forming the annular N-type contact layer (8) by photolithography and etching process, and forming the first step, the second step, and the third step of the cylindrical mesa by photolithography and etching process without photoresist removal, specifically comprises:

forming an annular N-type contact layer (8) through photoetching and corrosion processes;

forming a first step through photoetching and corrosion processes, specifically: etching an I-type edge electric field buffer layer (7), an N-type electric field control layer (6), an I-type multiplication layer (5), a P-type electric field control layer (4), an I-type light absorption layer (3) and a P-type contact layer (2) by using a solution with hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1 by using photoresist as a masking film, and finally stopping in a semi-insulating substrate (1) to form a first step;

the photoresist is not removed, and a second step is formed continuously through photoetching and corrosion processes, specifically: etching the I-type edge electric field buffer layer (7), the N-type electric field control layer (6), the I-type multiplication layer (5), the P-type electric field control layer (4) and the I-type light absorption layer (3) by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1 by using photoresist as a masking film, and finally stopping at the P-type contact layer (2) to form a second step;

the photoresist is not removed, and a third step is formed continuously through photoetching and corrosion processes, and the method is as follows: and (3) using the photoresist as a masking film, corroding the I-type edge electric field buffer layer (7), the N-type electric field control layer (6), the I-type multiplication layer (5) and the P-type electric field control layer (4) by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1, and finally stopping in the I-type light absorption layer (3) to form a third step.

9. The method for manufacturing the avalanche photodiode according to claim 7, wherein forming the first passivation layer (30), the second passivation layer (40), the third passivation layer (50) and exposing the P-type contact layer (2) and the N-type contact layer (8) by photolithography, a chemical plating process, a passivation process, a low temperature plasma enhanced chemical vapor deposition process and an etching process under photoresist stripping comprises:

photoresist is removed, and a first passivation layer (30) is formed through photoetching and chemical plating processes, specifically: firstly, covering the whole surface of an epitaxial wafer with photoresist through a photoetching process, and leaking out the side wall of a cylindrical table; then placing in ammonium sulfide solution for 40-60min, and then placing in cadmium sulfate solution; drying, removing photoresist, and finally forming a CdS passivation layer of 10-20nm on the side wall;

forming a second passivation layer (40) by a photolithography and passivation process, in particular: spin-coating photosensitive BCB on the surface of an epitaxial wafer, covering the surface of the epitaxial wafer on the side wall and the periphery of a cylinder table through a photoetching process, and passivating for 2 hours in a nitrogen atmosphere at 250 ℃ to form a BCB passivation layer;

forming a third passivation layer (50) by means of low temperature plasma enhanced chemical vapor deposition, in particular: deposition by means of low temperature plasma enhanced chemical vapor depositionA silicon nitride dielectric layer with the thickness to form a SiN anti-reflection passivation layer;

exposing the P-type contact layer (2) and the N-type contact layer (8) through photoetching and etching processes.

10. The method for manufacturing the avalanche photodiode according to claim 7, wherein the forming the silicon nitride dielectric reflective layer (20) and the high-reflection metal layer (10) by heat treatment, thinning and polishing, enhanced plasma vapor deposition and electron beam evaporation specifically comprises:

the epitaxial wafer is subjected to heat treatment for 1 to 3 minutes at the temperature of 300 to 360 ℃;

thinning and polishing the epitaxial wafer to 150 μm, and depositing on the polished surface of the epitaxial wafer by using an enhanced plasma vapor deposition modeA silicon nitride dielectric reflective layer (20) of a thickness;

forming a Ti/Pt/Au high-reflection metal layer (10) on the silicon nitride medium reflection layer (20) by adopting an electron beam evaporation process, wherein the thickness of Ti isPt thickness is +.>Au thickness of +.>