CN117097350B - LDPC code decoding realization method, device, equipment and medium - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to a method, a device, equipment and a medium for realizing LDPC code decoding, wherein the method comprises the following steps: rearranging the scheduling sequence of the base matrix according to the row weights of the base matrix and the number of the punching variable nodes; and carrying out layered decoding by adopting the rearranged base matrix. The invention can optimize the decoding performance under the condition that the complexity is not improved.
Description
Technical Field
The present invention relates to the field of wireless communications technologies, and in particular, to a method, an apparatus, a device, and a medium for implementing decoding of an LDPC code.
Background
The LDPC decoding algorithm is update decoded based on message passing on Tanner graph, as shown in fig. 1, wherein,Is the channel initial received message, and represents the credibility of the j-th codeword c j with a value of 1. q ji (1) is a variable message transmitted by variable node v j to check node z i, which represents variable node v j based on other check nodes and channel initial information/>The check node z i is declared to be c j =1 trustworthiness. r ij (1) is a check message transmitted by the check node z i to the variable node v j, which represents the confidence that the check node z i claims to v j that c j =1 according to the current state of other variable nodes satisfies the check equation represented by the check node z i.
The information is converted into a logarithmic domain, and then: channel initial informationInformation transmitted from check node to variable node/>Information of variable node transmitted to check node/>Decision information of variable node/>
Decoding according to a Layer scheduling scheme (using a hierarchical minimum sum decoding algorithm), wherein a check matrix of an LDPC code is divided into a plurality of layers according to rows, the hierarchical decoding is sequentially updated according to the layers, variable node information is updated immediately after the check node processing of each Layer is completed, the variable node information updated in the previous Layer can be used when the check node processing of the next Layer is completed, and when the update of all the Layer check nodes is completed, one iteration is completed, specifically:
(1) Initializing: initializing the information of all variable nodes and the information transmitted to the variable nodes by the check nodes, namely:
(2) And (3) iteration processing: calculate variable node information L (l,k)(qj of the first iteration, the k-th layer) and check information L (l)(rij of the first iteration), specifically:
And (5) updating in a layering way: And (3) judging: k is the last layer, if L (l,k)(qj) < 0, then c j =1, otherwise c j =0.
(3) And stopping iteration, if Hc T =0 or the maximum iteration number is reached, ending the iteration, otherwise, continuing the iteration.
The decoding update sequence is as follows: for the base matrix BG1, the scheduling update is performed in the order of the 1 st row to 46 th row of the matrix during decoding, and for the base matrix BG2, the scheduling update is performed in the order of the 1 st row to 42 th row of the matrix during decoding. In the hierarchical decoding process, the base matrix is updated from top to bottom, so that the decoding performance is limited.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method, a device, equipment and a medium for realizing LDPC code decoding, which can optimize decoding performance under the condition that complexity is not improved.
The technical scheme adopted for solving the technical problems is as follows: the method for realizing LDPC code decoding comprises the following steps:
rearranging the scheduling sequence of the base matrix according to the row weights of the base matrix and the number of the punching variable nodes;
And carrying out layered decoding by adopting the rearranged base matrix.
When the scheduling sequence of the base matrix is rearranged according to the row weights of the base matrix and the number of the punching variable nodes, the rows of the base matrix are divided into different sets according to the punching number, the sets are ordered according to the punching number from low to high, and the rows in the sets are arranged according to the row weights from low to high.
The rearrangement of the scheduling sequence of the base matrix according to the row weight of the base matrix and the number of the punching variable nodes specifically comprises the following steps:
classifying the rows of the base matrix according to the number of the row punching variable nodes;
the method comprises the steps of marking a set of lines with the number of the perforation variable nodes being 0 as a set R0, marking a set of lines with the number of the perforation variable nodes being 1 as a set R1, and marking a set of lines with the number of the perforation variable nodes being 2 as a set R2;
The rows in the set R0, the set R1 and the set R2 are arranged from low to high according to row weights, so that a new set R0', a set R1' and a set R2' are obtained;
and sequentially arranging the set R0', the set R1' and the set R2' to obtain a rearranged base matrix.
The layered decoding by adopting the rearranged base matrix specifically comprises the following steps:
Initializing the information of all variable nodes and the information transmitted to the variable nodes by the check nodes;
In one iteration, variable node information and verification information of the iteration are updated according to the layer sequence of the rearranged base matrix;
when the last layer is updated, making a decision to obtain a decision bit sequence;
If Hc T =0, h is the check matrix, c is the decision bit sequence, stopping iteration, outputting the decision bit as the decoding result, otherwise continuing iteration until the maximum iteration times.
The technical scheme adopted for solving the technical problems is as follows: there is provided an LDPC code decoding implementing apparatus including:
The rearrangement module is used for rearranging the scheduling sequence of the base matrix according to the row weights of the base matrix and the number of the punching variable nodes;
and the decoding module is used for carrying out layered decoding by adopting the rearranged base matrix.
When the rearrangement module rearranges the scheduling sequence of the base matrix, the rows of the base matrix are divided into different sets according to the punching quantity, the sets are ordered from low to high according to the punching quantity, and the rows in the sets are arranged from low to high according to the row weight
The rearrangement module comprises:
the classifying unit is used for classifying the rows of the base matrix according to the number of the row punching variable nodes;
a marking unit, configured to mark a set of rows with a number of perforation variable nodes of 0 as a set R0, a set of rows with a number of perforation variable nodes of 1 as a set R1, and a set of rows with a number of perforation variable nodes of 2 as a set R2;
The sorting unit is used for arranging the rows in the set R0, the set R1 and the set R2 from low to high according to row weights to obtain a new set R0', a set R1' and a set R2';
The arrangement unit is used for arranging the set R0', the set R1' and the set R2' in sequence to obtain a rearranged base matrix.
The coding module includes:
the initialization unit is used for initializing the information of all the variable nodes and the information transmitted to the variable nodes by the check nodes;
the iteration unit is used for updating variable node information and verification information of the iteration according to the layer sequence of the rearranged base matrix in the iteration;
The judging unit is used for judging after the last layer is updated to obtain a judging bit sequence;
And the termination judging unit is used for terminating iteration when Hc T =0, H is a check matrix, c is a judgment bit sequence, outputting judgment bits as a decoding result, and continuing iteration until the maximum iteration times are reached.
The technical scheme adopted for solving the technical problems is as follows: there is provided an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above LDPC code decoding implementation method when executing the computer program.
The technical scheme adopted for solving the technical problems is as follows: there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the LDPC code decoding implementation method described above.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention rearranges the base matrix in advance according to the row weight of the base matrix and the number of the punching variable nodes before decoding, and decodes based on the rearranged base matrix, so that the decoding performance can be effectively improved, the convergence is quickened, and the decoding performance gain of about 0.2dB can be obtained under the configuration of 5g nr BG1 through simulation.
Drawings
FIG. 1 is an LDPC decoding tanner graph;
FIG. 2 is a flowchart of a method for implementing LDPC code decoding according to a first embodiment of the present invention;
fig. 3 is a flowchart of a base matrix rearrangement process according to a first embodiment of the present invention;
Fig. 4 is a schematic diagram of the rearranged base matrix BG 1;
fig. 5 is a schematic diagram of the rearranged base matrix BG 2.
Detailed Description
The application will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present application and are not intended to limit the scope of the present application. Furthermore, it should be understood that various changes and modifications can be made by one skilled in the art after reading the teachings of the present application, and such equivalents are intended to fall within the scope of the application as defined in the appended claims.
A first embodiment of the present invention relates to a method for implementing decoding of an LDPC code, as shown in fig. 2, including the steps of:
and step 1, rearranging the scheduling sequence of the base matrix according to the row weights of the base matrix and the number of the punching variable nodes.
In the check matrix, when the row weight is lower, the variable nodes connected with check nodes of the row are fewer, so that the reliability of corresponding variable information is higher, and therefore, the row with lower row weight can be updated preferentially in layered decoding, and the variable information with high reliability can be obtained preferentially and transmitted to other nodes connected with the variable information earlier.
According to the 5g nr rate matching strategy, the variable nodes corresponding to the first two columns in the base matrix are punctured, so that the LLR of the two columns of variables is initialized to 0 in the decoding process. If one check node is connected with one punching variable node, in the decoding updating, the variable information of the punching variable node is not 0, and the information of other connected variable nodes is 0, if one check node is connected with two punching variable nodes, the information of the variable nodes connected with the check node is 0, and in essence, the updating of the row has no effect on decoding. Therefore, the row with less punching is preferentially selected, the information of the punching position can be updated as soon as possible, and the situation that the variable information is 0 in the follow-up process is avoided.
Therefore, in this step, when the scheduling sequence of the base matrix is rearranged, the row with the lower row weight is adjusted to the front, and the row with the larger number of the variable nodes is adjusted to the rear. As shown in fig. 3, the method comprises the following steps:
classifying the rows of the base matrix according to the number of the row punching variable nodes;
the method comprises the steps of marking a set of lines with the number of the perforation variable nodes being 0 as a set R0, marking a set of lines with the number of the perforation variable nodes being 1 as a set R1, and marking a set of lines with the number of the perforation variable nodes being 2 as a set R2;
The rows in the set R0, the set R1 and the set R2 are arranged from low to high according to row weights, so that a new set R0', a set R1' and a set R2' are obtained;
and sequentially arranging the set R0', the set R1' and the set R2' to obtain a rearranged base matrix.
The reason for the rearrangement in the above manner is that the fewer the variable nodes in the first two columns are, the lower the row weight is, so that the principle that the row weight is arranged from low to high is ensured while the arrangement of the punching number from low to high is also satisfied as much as possible.
Fig. 4 and 5 show schematic diagrams after rearrangement of the base matrix BG1 and the base matrix BG2, respectively.
And step 2, performing layered decoding by adopting the rearranged base matrix. The method specifically comprises the following steps:
Initializing the information of all variable nodes and the information transmitted to the variable nodes by the check nodes;
In one iteration, variable node information and verification information of the iteration are updated according to the layer sequence of the rearranged base matrix;
when the last layer is updated, making a decision to obtain a decision bit sequence;
If Hc T =0, h is the check matrix, c is the decision bit sequence, stopping iteration, outputting the decision bit as the decoding result, otherwise continuing iteration until the maximum iteration times.
It is not difficult to find that the invention rearranges the base matrix in advance according to the row weight of the base matrix and the number of the variable nodes of punching before decoding, and decodes based on the rearranged base matrix, so that the decoding performance can be effectively improved, the convergence is quickened, and the decoding performance gain of about 0.2dB can be obtained under the configuration of 5g nr BG1 through simulation.
A second embodiment of the present invention relates to an LDPC code decoding implementation apparatus, including:
The rearrangement module is used for rearranging the scheduling sequence of the base matrix according to the row weights of the base matrix and the number of the punching variable nodes;
and the decoding module is used for carrying out layered decoding by adopting the rearranged base matrix.
When the rearrangement module rearranges the scheduling sequence of the base matrix, the rows of the base matrix are divided into different sets according to the punching quantity, the sets are ordered from low to high according to the punching quantity, and the rows in the sets are arranged from low to high according to the weight of the rows.
The rearrangement module comprises:
the classifying unit is used for classifying the rows of the base matrix according to the number of the row punching variable nodes;
a marking unit, configured to mark a set of rows with a number of perforation variable nodes of 0 as a set R0, a set of rows with a number of perforation variable nodes of 1 as a set R1, and a set of rows with a number of perforation variable nodes of 2 as a set R2;
The sorting unit is used for arranging the rows in the set R0, the set R1 and the set R2 from low to high according to row weights to obtain a new set R0', a set R1' and a set R2';
The arrangement unit is used for arranging the set R0', the set R1' and the set R2' in sequence to obtain a rearranged base matrix.
The coding module includes:
the initialization unit is used for initializing the information of all the variable nodes and the information transmitted to the variable nodes by the check nodes;
the iteration unit is used for updating variable node information and verification information of the iteration according to the layer sequence of the rearranged base matrix in the iteration;
A decision unit for obtaining a decision bit sequence;
And the termination judging unit is used for terminating iteration when Hc T =0, H is a check matrix, c is a judgment bit sequence, outputting judgment bits as a decoding result, and continuing iteration until the maximum iteration times are reached.
A third embodiment of the present invention relates to an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the LDPC code decoding implementation method of the first embodiment when executing the computer program.
A fourth embodiment of the present invention relates to a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the LDPC code decoding implementation method of the first embodiment.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The scheme in the embodiment of the invention can be realized by adopting various computer languages, such as object-oriented programming language Java, an transliteration script language JavaScript and the like.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (6)
1. An implementation method for decoding LDPC codes is characterized by comprising the following steps:
the scheduling sequence of the base matrix is rearranged according to the row weight of the base matrix and the number of the punching variable nodes, when the base matrix is rearranged, the rows of the base matrix are divided into different sets according to the punching number, the sets are ordered according to the punching number from low to high, and the inside of each set is arranged according to the row weight from low to high, and the method specifically comprises the following steps:
classifying the rows of the base matrix according to the number of the row punching variable nodes;
the method comprises the steps of marking a set of lines with the number of the perforation variable nodes being 0 as a set R0, marking a set of lines with the number of the perforation variable nodes being 1 as a set R1, and marking a set of lines with the number of the perforation variable nodes being 2 as a set R2;
The rows in the set R0, the set R1 and the set R2 are arranged from low to high according to row weights, so that a new set R0', a set R1' and a set R2' are obtained;
sequentially arranging the set R0', the set R1' and the set R2' to obtain a rearranged base matrix;
And carrying out layered decoding by adopting the rearranged base matrix.
2. The method for implementing LDPC code decoding according to claim 1, wherein the performing layered decoding using the rearranged base matrix specifically includes:
Initializing the information of all variable nodes and the information transmitted to the variable nodes by the check nodes;
In one iteration, variable node information and verification information of the iteration are updated according to the layer sequence of the rearranged base matrix;
when the last layer is updated, making a decision to obtain a decision bit sequence;
If Hc T =0, h is the check matrix, c is the decision bit sequence, stopping iteration, outputting the decision bit as the decoding result, otherwise continuing iteration until the maximum iteration times.
3. An apparatus for implementing decoding of an LDPC code, comprising:
The rearrangement module is used for rearranging the scheduling sequence of the base matrix according to the row weights of the base matrix and the number of the punching variable nodes, dividing the rows of the base matrix into different sets according to the punching number during rearrangement, sequencing the sets from low to high according to the punching number, and arranging the inner parts of the sets from low to high according to the row weights; the rearrangement module comprises:
the classifying unit is used for classifying the rows of the base matrix according to the number of the row punching variable nodes;
a marking unit, configured to mark a set of rows with a number of perforation variable nodes of 0 as a set R0, a set of rows with a number of perforation variable nodes of 1 as a set R1, and a set of rows with a number of perforation variable nodes of 2 as a set R2;
The sorting unit is used for arranging the rows in the set R0, the set R1 and the set R2 from low to high according to row weights to obtain a new set R0', a set R1' and a set R2';
The arrangement unit is used for arranging the set R0', the set R1' and the set R2' in sequence to obtain a rearranged base matrix;
and the decoding module is used for carrying out layered decoding by adopting the rearranged base matrix.
4. The apparatus for implementing LDPC code decoding according to claim 3, wherein the decoding module comprises:
the initialization unit is used for initializing the information of all the variable nodes and the information transmitted to the variable nodes by the check nodes;
the iteration unit is used for updating variable node information and verification information of the iteration according to the layer sequence of the rearranged base matrix in the iteration;
the judging unit is used for obtaining a judging bit sequence after the last layer is updated;
And the termination judging unit is used for terminating iteration when Hc T =0, H is a check matrix, c is a judgment bit sequence, outputting judgment bits as a decoding result, and continuing iteration until the maximum iteration times are reached.
5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the LDPC code decoding implementation method according to any of claims 1-2 when the computer program is executed.
6. A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the LDPC code decoding implementation method according to any of claims 1-2.
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