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CN116991359A - Booth multiplier, hybrid Booth multiplier and operation method - Google Patents

Booth multiplier, hybrid Booth multiplier and operation method Download PDF

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Publication number
CN116991359A
CN116991359A CN202311244047.8A CN202311244047A CN116991359A CN 116991359 A CN116991359 A CN 116991359A CN 202311244047 A CN202311244047 A CN 202311244047A CN 116991359 A CN116991359 A CN 116991359A
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partial
multiplier
partial product
module
multiplicand
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CN116991359B (en
Inventor
朱世凯
藏晨光
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Shanghai Weijing Technology Co ltd
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Shanghai Weijing Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Pure & Applied Mathematics (AREA)
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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention discloses a Booth multiplier, a hybrid Booth multiplier and an operation method, wherein the Booth multiplier comprises: the coding module is used for coding the multiplier based on a Booth algorithm to obtain a coding signal; the partial product generating module is used for processing the multiplicand according to the coding signal to generate a plurality of partial products and a plurality of sign correction bits; the partial product accumulation module is used for calculating the sum of the sign bits of the partial product according to the sign bits of the partial product; the partial accumulation adding module is also used for selecting a corresponding calculation mode according to an external input signal; the partial accumulation adding module is also used for revising the sign bit of the partial product according to the calculation mode and a plurality of sign revising bits; and the partial accumulation and addition module is also used for executing accumulation operation on a plurality of partial products according to the calculation mode and combining the sum of sign bits of the revised partial products to obtain the product result of the multiplier and the multiplicand.

Description

Booth multiplier, hybrid Booth multiplier and operation method
Technical Field
The invention relates to the field of design of multiplication units, in particular to a Booth multiplier.
Background
The multiplier is a basic component for completing multiplication of two signals, is widely applied to the communication field of digital signal processing, is an important component part of a neural network accelerator, has the running speed, the area, the time sequence and the power consumption which are critical to the performance of hardware, can perform low-precision operation through the traditional multiplier, and can perform mixed-precision operation after splicing the traditional multiplier. In the operation of a conventional multiplier, a large number of adders are required, for example: the calculation process of solving the partial product needs to perform inversion, shift and one addition on the multiplicand, and one addition needs an extra adder. In order to avoid excessive adders causing large circuit area and power consumption, and to avoid adders limiting circuit critical paths, it is desirable to minimize the use of adders in conventional multipliers without losing accuracy.
Disclosure of Invention
In order to solve the technical problems, the invention provides a Booth multiplier, a hybrid Booth multiplier and an operation method.
Specifically, the technical scheme of the invention is as follows:
in a first aspect, the present invention provides a Booth multiplier, comprising:
the encoding module is used for encoding the multiplier based on a Booth algorithm to obtain a corresponding encoded signal, and transmitting the encoded signal to the partial product generating module;
The partial product generating module is connected with the encoding module and is used for processing the multiplicand according to the encoding signal to generate a plurality of partial products and a plurality of symbol correction bits, and transmitting the partial products and the symbol correction bits to the partial accumulation adding module;
the partial product accumulation module is connected with the partial product generation module and is used for calculating the sum of the sign bits of the partial product according to the sign bits of a plurality of partial products;
the part accumulation module is also used for selecting a corresponding calculation mode according to an external input signal;
the partial accumulation adding module is further used for selecting an input carry signal of a carry port of the Booth multiplier according to the calculation mode and a plurality of sign correction bits; revising sign bits of the partial product according to the calculation mode and the input carry signal;
the partial accumulation adding module is further configured to perform an accumulation operation on a plurality of partial products according to the calculation mode, and combine the modified sum of sign bits of the partial products to obtain a product result of the multiplier and the multiplicand.
The implementation method encodes the input multiplicand through an encoding module; the partial product generating module decodes and generates partial product and symbol correction bits, the symbol correction bits represent the positive and negative of the coding result, and an adder required by adding one calculation to the partial product by the partial product generating module is saved; the partial product accumulation module is used for accumulating and summing the partial products to obtain partial sums and calculating the sums of sign bits of the partial products; the partial product accumulation module also selects whether the sign bit needs to be corrected by inputting a carry signal or not through a control signal, so that the Booth multiplier can finish partial product accumulation and sign bit expansion calculation under different calculation modes, and finally a product result is solved.
In some implementations of Booth multipliers,
the partial product generating module is further configured to shift and/or invert the multiplicand according to the encoded signal, so as to obtain the partial product;
the partial product generating module is further configured to set a symbol correction bit corresponding to the encoded signal according to whether the encoded signal is positive or negative.
The implementation method provides that the partial product generating module only carries out shift and inverse operation on the partial product, and the generated sign correction bits for positive and negative correction are input to the partial accumulation adding module for correction, so that the adding 1 operation is realized by accumulating sign correction signals in the partial accumulation adding module, and an adder is saved.
In some implementations of Booth multipliers,
and the partial product accumulation module is used for inverting the sign bit of the partial product, substituting the inverted sign bit of the partial product and the summation calculation formula into a sign bit expansion formula, and calculating to obtain the sum of the sign bits of the partial product.
The implementation method uses the partial accumulation adding module to invert the sign bit of the partial product and then operate, thereby saving the number of adders in the adder array.
In some implementations of Booth multipliers,
The external input signal includes: an externally input carry control signal and an externally input sign bit control signal;
the partial accumulation adding module is further configured to input the sign correction bit of the previous Booth multiplier to a carry port of the current Booth multiplier as an input carry signal when the sign bit control signal is at a low potential;
the partial accumulation adding module is further configured to input the sign correction bit of the current Booth multiplier to a carry port of the current Booth multiplier when the sign bit control signal is at a high potential.
According to the implementation method, whether the sign bit is corrected according to the input carry signal is controlled and selected through an external input signal, so that different calculation modes of the sign bit are controlled by the Booth multiplier under different calculation modes.
In some implementations of Booth multipliers,
the partial accumulation adding module is further used for calculating the high bit of the multiplicand when the carry control signal is at a low potential; and when the carry control signal is at a high potential, calculating the low order of the multiplicand.
In some implementations of Booth multipliers,
the computing mode includes: a low precision mode of operation between the multiplicand and the multiplier, a hybrid precision mode of operation between the multiplicand and the multiplier; the mixed precision operation mode comprises the following steps: an operation between a low order of the multiplicand and a low order of the multiplier, an operation between a high order of the multiplicand and a high order of the multiplier, an operation between a low order of the multiplicand and a high order of the multiplier.
In a second aspect, the present invention provides a hybrid Booth multiplier, comprising two Booth multipliers according to the previous implementation method, namely a first Booth multiplier and a second Booth multiplier,
the first Booth multiplier includes: the device comprises a first coding module, a first partial product generating module and a first partial accumulating and adding module; the second Booth multiplier includes: the second coding module, the second partial product generating module and the second partial product accumulating module;
the first partial accumulation adding module inputs low level to the sign bit of a first partial product according to an external input signal, directly performs accumulation operation on the first partial product to obtain an output carry signal and a first partial sum, and provides the output carry signal and the first partial sum for the second Booth multiplier; the first partial product is a partial product result between the multiplier and the low order bits of the multiplicand;
the second Booth multiplier is connected with the first Booth multiplier, performs correction operation on sign bits of a second partial product according to an external input signal, and performs accumulation operation on the second partial product to obtain a second partial sum; the second partial product is a partial product result between the multiplier and the high order bits of the multiplicand;
And the second part accumulation adding module obtains the product result of the multiplier and the multiplicand according to the first part sum and the second part sum.
The implementation method can realize multiplication calculation of multiplying n bits by 2n bits through combination of the first Booth multiplier and the second Booth multiplier, wherein n is determined by the calculation capability of a single Booth multiplier.
In a third aspect, the present invention provides a hybrid Booth multiplier, including four Booth multipliers of the foregoing embodiments, that is, a first Booth multiplier, a second Booth multiplier, a third Booth multiplier, a fourth Booth multiplier, and an adder;
a first partial accumulation module in the first Booth multiplier for calculating a first partial product between the low order of the multiplier and the low order of the multiplicand; a second partial accumulation module in the second Booth multiplier for calculating a second partial product between the high order of the multiplier and the low order of the multiplicand; a third partial accumulation module in the third Booth multiplier for calculating a third partial product between the low order of the multiplier and the high order of the multiplicand; a fourth partial accumulation module in the fourth Booth multiplier for calculating a fourth partial product between the high order of the multiplier and the high order of the multiplicand;
Summing the first partial product, the second partial product, the third partial product and the fourth partial product respectively through the first partial product accumulation and addition module, the second partial product accumulation module, the third partial product accumulation module and the fourth partial product accumulation and addition module to obtain a first partial sum, a second partial sum, a third partial sum and a fourth partial sum;
the first part accumulation adding module outputs a first product result in the first part sum and provides a first part to be operated in the first part sum to the second part accumulation adding module; the second partial product accumulation module outputs a second product result in the second partial sum and provides a second part to be operated of the second partial sum to the third partial product accumulation module and the adder; the third partial product accumulation module providing the third partial sum to the adder; the adder provides a third part to be operated according to the second part sum, the third part sum and the fourth part accumulation adding module and outputs a third multiplication result; the fourth partial product accumulation module outputs a fourth product result according to the third part to be operated and the fourth partial sum;
And obtaining the product result of the multiplier and the multiplicand by splicing the first product result, the second product result, the third product result and the fourth product result.
According to the implementation method, multiplication calculation of 2n bits by 2n bits can be realized through the first Booth multiplier, the second Booth multiplier, the third Booth multiplier and the fourth Booth multiplier, and n is determined by the calculation capability of a single Booth multiplier.
In a fourth aspect, the present invention provides a method for operating a Booth multiplier, including:
encoding the multiplier based on a Booth algorithm to obtain a corresponding encoded signal;
processing the multiplicand according to the coding signal to generate a plurality of partial products and a plurality of sign correction bits;
calculating to obtain the sum of the sign bits of the partial product according to the sign bits of the partial product;
selecting a corresponding calculation mode according to an external input signal;
selecting an input carry signal of a carry port of a Booth multiplier according to the calculation mode and a plurality of sign correction bits; revising sign bits of the partial product according to the calculation mode and the input carry signal;
and according to the calculation mode, performing accumulation operation on a plurality of partial products, and combining the sum of sign bits of the corrected partial products to obtain a product result of the multiplier and the multiplicand.
The implementation method only carries out shift operation and inversion operation on the partial product by generating the symbol correction bit, and selects whether the symbol bit needs to be corrected by inputting a carry signal or not by a control signal, so that the Booth multiplier completes partial product accumulation and symbol bit calculation under different calculation modes, and finally solves the product result.
In some implementations of the method for operating a Booth multiplier, the selecting a corresponding calculation mode according to an external input signal includes:
the external input signal includes: an externally input carry control signal and an externally input sign bit control signal;
when the carry control signal is at a low potential, calculating the high order of the multiplicand;
when the carry control signal is at a high potential, calculating the low order of the multiplicand;
when the sign bit control signal is of low potential, the sign correction bit of the last Booth multiplier is used as an input carry signal to be input to a carry port of the current Booth multiplier;
when the sign bit control signal is in a high potential, the sign correction bit of the current Booth multiplier is input to a carry port of the current Booth multiplier;
Selecting a corresponding calculation mode according to the carry control signal and the sign bit control signal; the computing mode includes: a low precision mode of operation between the multiplicand and the multiplier, a hybrid precision mode of operation between the multiplicand and the multiplier; the mixed precision operation mode comprises the following steps: an operation between a low order of the multiplicand and a low order of the multiplier, an operation between a high order of the multiplicand and a high order of the multiplier, an operation between a low order of the multiplicand and a high order of the multiplier.
In some implementations of the method for operating a Booth multiplier, the calculating, according to the sign bits of the partial product, a sum of sign bits of the partial product includes:
inverting the sign bit of the partial product;
substituting the sign bit of the partial product after the inversion and the summation calculation formula into a sign bit expansion formula, and calculating to obtain the sum of the sign bits of the partial product.
Compared with the prior art, the invention has at least one of the following beneficial effects:
1. the invention encodes the input multiplicand through the encoding module; the partial product generating module decodes and generates partial product and symbol correction bits, the symbol correction bits represent the positive and negative of the coding result, and an adder required by adding one calculation to the partial product by the partial product generating module is saved; the partial product accumulation module is used for accumulating and summing the partial products to obtain partial sums and calculating the sums of sign bits of the partial products; the partial product accumulation module also selects whether the sign bit needs to be corrected by inputting a carry signal or not through a control signal, so that the Booth multiplier can finish partial product accumulation and sign bit expansion calculation under different calculation modes, and finally a product result is solved.
2. The partial product generating module only carries out shifting and inverting operations on the partial product, and the generated sign correction bits for correcting the positive and negative signs are input into the partial accumulation adding module for correction, so that the adding 1 operation is realized by accumulating sign correction signals in the partial accumulation adding module, and an adder is saved.
3. According to the invention, whether the sign bit is corrected according to the input carry signal is controlled and selected through the external input signal, so that different calculation modes of the sign bit are controlled by the Booth multiplier under different calculation modes.
4. Compared with the traditional splicing scheme, the invention saves the adder, reduces the whole circuit area on the premise of not reducing the operation precision, optimizes the time sequence and greatly improves the performance of the multiplier by executing the accumulation of the mixed precision operation part sum through the part accumulation and addition module.
Drawings
The above features, technical features, advantages and implementation of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a block diagram of a Booth multiplier system according to the present invention;
FIG. 2 is a circuit diagram of a coding module of a Booth multiplier according to the present invention;
FIG. 3 is a circuit diagram of a partial product generation module of a Booth multiplier according to the present invention;
FIG. 4 is a circuit diagram of a partial accumulation adder module of a Booth multiplier according to the present invention;
FIG. 5 is a block diagram of a hybrid Booth multiplier according to the present invention;
FIG. 6 is a block diagram of a hybrid Booth multiplier according to the present invention;
FIG. 7 is a prior art symbol bit expansion diagram;
FIG. 8 is a symbol bit expansion diagram provided by the present invention;
fig. 9 is a flowchart of an operation method of a Booth multiplier provided by the present invention.
Reference numerals illustrate: 10- -an encoding module; 20—a partial product generation module; 30- -partial accumulation Add Module.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In one embodiment, referring to fig. 1 and 2 of the specification, the present application provides a Booth multiplier, including:
the encoding module 10 is configured to encode the multiplier based on a Booth algorithm to obtain a corresponding encoded signal, and transmit the encoded signal to the partial product generating module 20. A Booth multiplier is a fast and efficient multiplier that can calculate the product of two binary numbers in a short time.
The encoding module 10 encodes the multiplier by adopting a conventional Booth algorithm, encodes the 9-bit multiplier B by a base-4 Booth algorithm, can obtain five groups of encoding results, defines the 9-bit multiplier b= { B8, B7..b 1, B0}, supplements the lower bit of the multiplier B with b_1, and if 9-bit multiplication operation is being performed for the supplementary bit b_1, both the multiplier and the multiplicand are 9 bits, the supplementary bit b_1 is the lowest bit of the multiplier B, and b_1 is 0; if a mixed-precision multiplication is performed, the following steps are performed: when the 18-bit multiplication operation is carried out, the multiplier and the multiplicand are 18 bits, the multiplier B is divided into the high order of the multiplier B and the low order of the multiplier B, the high order of the multiplier B is the first 9 bits of the multiplier B, the low order of the multiplier B is the last 9 bits of the multiplier B, for the multiplier for calculating the high order of the multiplier B, the high order of the multiplier B is supplemented with B8 as b_1, and the low order of the multiplier B is supplemented with b_1 as 0;
and performing overlapping access per 3 bits on the multiplier B, such as: { b1, b0, b_1}, { b3, b2, b1}, the obtained data has eight cases of {000, 001, 010, 011, 100, 101, 110, 111}, and the obtained data is encoded, and the encoding result is thatI is a non-negative integer, b_1 is taken as +.>Inputting; when i=4, since the input is 9 bits, the most significant bit needs to be extended, will +. >As->Inputting, wherein the obtained coding result can be 0, +1, +2, -1, -2; the corresponding coding signal consists of a NEG signal, an X1 signal and an X2 signal; the NEG signal represents positive and negative coding results, and when the coding results are positive, the NEG signal is output as low level 0, and when the coding results are negative, the NEG signal is output as high level 1; the X1 signal represents whether the coding result is 1, when the coding result isWhen the signal is 1 or-1, the output X1 signal is high level 1; the X2 signal represents whether the encoding result is 2, and when the encoding result is 2 or-2, the output X2 signal is high level "1". The corresponding relation between the data of the multiplier B and the coding result and the coding signal is shown in the following table I:
list one
In addition, fig. 2 of the specification also provides an implementation circuit of the encoding module 10, which is implemented based on an and circuit, an or circuit and an not circuit.
The partial product generating module 20 is connected to the encoding module 10, and is configured to process the multiplicand according to the encoded signal, generate a plurality of partial products and a plurality of sign correction bits, and transmit the plurality of partial products and the plurality of sign correction bits to the partial product accumulating module 30.
Specifically, the lowest bit of the multiplicand a is complemented by a_1, and for the complemented bit a_1, the partial product generation module 20 performs 9-bit multiplication operation, where the complemented bit a_1 is 0; if the mixed precision multiplication is performed, a multiplier for performing high-order calculation of the multiplicand A is performed, the complementary bit a_1 is a8, and a multiplier for performing low-order calculation of the multiplicand A is performed, and a_1 is 0; the partial product generating module 20 processes the multiplicand a according to the encoded signal of the multiplier B provided by the encoding module 10 to obtain a partial product.
The partial product accumulation module 30 is connected to the partial product generation module 20, and is configured to calculate a sum of sign bits of the partial product according to sign bits of the partial product. The partial product accumulation module 30 expands and sums the sign bits by the adders in the adder array to obtain the sum of the sign bits of the partial product.
A partial product accumulation module 30, configured to select a corresponding calculation mode according to an external input signal; the calculation mode includes: a low-precision operation mode between the multiplicand and the multiplier, and a mixed-precision operation mode between the multiplicand and the multiplier; the mixed precision operation mode includes: an operation between the low order of the multiplicand and the low order of the multiplier, an operation between the high order of the multiplicand and the high order of the multiplier, and an operation between the low order of the multiplicand and the high order of the multiplier. The low-precision operation mode is a mode in which a single Booth multiplier outputs an operation result, and the mixed-precision operation mode is a mode in which a plurality of Booth multipliers mutually splice operation results.
The partial product accumulation module 30 invokes the Booth multiplier to execute different calculation modes through an external input signal, and can select the Booth multiplier to execute mixed precision operation or low precision operation.
The partial accumulation adding module 30 is further configured to select an input carry signal of the carry port of the Booth multiplier according to the calculation mode and the plurality of sign correction bits; the sign bit of the partial product is revised according to the calculation mode and the input carry signal. For example: when the calculation mode of the current Booth multiplier is the operation between the low order of the multiplicand and the high order of the multiplier, the partial product accumulation module 30 uses the sign correction bit obtained by the current Booth multiplier as the input carry signal of the next Booth multiplier, wherein the calculation mode of the next Booth multiplier is the operation between the high order of the multiplicand and the high order of the multiplier, and the sign bit of the partial product calculated by the next Booth multiplier can be corrected by the carry signal.
The partial accumulation and addition module 30 is further configured to perform an accumulation operation on the plurality of partial products according to the calculation mode, and combine the sum of sign bits of the revised partial products to obtain a product result of the multiplier and the multiplicand. For example: when the low-precision operation mode is executed, after the expansion calculation of the sign bit is completed, the sign bit of the partial product is not required to be corrected, and the partial product is directly accumulated, so that the product result of the multiplier and the multiplicand can be obtained.
The input multiplicand is encoded by the encoding module 10 in this embodiment; the partial product generating module 20 decodes to generate partial product and symbol correction bits, and the symbol correction bits represent the positive and negative of the coding result, so that the adder required by adding one calculation to the partial product by the partial product generating module 20 is saved; the partial product accumulation module 30 is configured to accumulate and sum the partial products to obtain a partial sum, and calculate a sum of sign bits of the partial products; the partial accumulation and addition module 30 also selects whether the sign bit of the partial product needs to be corrected by inputting a carry signal through a control signal, so that the Booth multiplier finishes partial product accumulation and sign bit expansion calculation in different calculation modes, and finally solves the product result.
This embodiment provides a Booth multiplier based on the previous embodiment, referring to fig. 3 of the specification, including:
the partial product generating module 20 is further configured to shift and/or invert the multiplicand according to the encoded signal to obtain a partial product; the correspondence between the encoding result and the partial product is as follows: when the input multiplier B coding result is 0, namely the X1 signal is 0, the X2 signal is 0, and the NEG signal is 0, the partial product result is 0; when the coding result of the input multiplier B is 1, namely the X1 signal is 1, the X2 signal is 0, and the NEG signal is 0, the partial product result is A; when the coding result of the input multiplier B is 2, namely the X1 signal is 0, the X2 signal is 1, and the NEG signal is 0, the partial product result is the shift of A; when the coding result of the input multiplier B is-1, namely the X1 signal is 1, the X2 signal is 0, and the NEG signal is 1, the partial product result is the inverse of A; when the coding result of the input multiplier B is-2, namely the X1 signal is 0, the X2 signal is 1, and the NEG signal is 1, the partial product result is the shift of A to be inverted.
The partial product generating module 20 is further configured to set a symbol correction bit corresponding to the encoded signal according to whether the encoded signal is positive or negative. For example: when the coding result is positive, the symbol correction bit amend [ i ] is 0, when the coding result is negative, the symbol correction bit amend [ i ] is 1, and i is a positive integer.
The present embodiment provides logic for the partial product generation module 20 to obtain the partial product and sign correction bits based on the encoding result. When using a conventional Booth multiplier to calculate, the partial product is obtained by inverting the multiplicand, and/or shifting, and/or adding one, and an additional adder is needed in the calculation of adding one, but in this embodiment, the sign correction bit amend [ i ] represents positive and negative, and the sign correction bit amend [ i ] is sent to the partial product accumulation module 30, so that the calculation process of inverting the multiplicand is carried out in the partial product accumulation module 30, and the adder needed by the addition operation is saved. The partial product generating module 20 in this embodiment may be a partial product generating circuit formed by a plurality of data selectors and inverting circuits shown in fig. 3.
This embodiment provides a Booth multiplier based on the previous embodiment, referring to fig. 7 and 8 of the specification,
The partial product accumulation module 30 inverts the sign bit of the partial product, substitutes the inverted sign bit of the partial product and the sum calculation formula into the sign bit expansion formula, and calculates the sum of the sign bits of the partial product.
The sign bit expansion formula in the prior art can be adopted for expanding the sign bit; the sign bit expansion formula is as follows:
；
where SIGN is the sum of the SIGN bits of the partial products, s0 is the SIGN bit of the first partial product, s1 is the SIGN bit of the second partial product, s2 is the SIGN bit of the third partial product, s3 is the SIGN bit of the fourth partial product, and s4 is the SIGN bit of the fifth partial product; the sign bit expansion formula can expand sign bits of partial products, and at this time, the partial products include: a first partial product, a second partial product, a third partial product, and a fourth partial product.
The present embodiment sums the calculated formulas by inverting the sign bits of the partial product:the method comprises the steps of carrying out a first treatment on the surface of the The sign bit of the partial product is taken as the trans: />And the above sign bit expansion formula is carried in.
Obtaining a sign bit expansion formula after inverting the sign bit:
where sj is the inverse of the sign bit of the jth partial product.
Fig. 7 in the specification is a sign bit expansion algorithm a, the sign bit expansion algorithm a is an expansion method corresponding to a sign bit expansion formula, fig. 8 in the specification is a sign bit expansion algorithm B, and the sign bit expansion algorithm B is an expansion method corresponding to the sign bit expansion formula after inverting the sign bit; it can be seen from fig. 7 and 8 of the specification that the number of adders in the adder array in the partial product accumulation module 30 of fig. 4 of the specification can be reduced by performing the inverse processing on the sign bit. In FIG. 7, P00-P09 are several bits of the first partial product, P09 is the highest bit of the first partial product, i.e. the sign bit s0 of the first partial product, and P09 is the inverse of the sign bit P09 of the first partial product in FIG. 8; in fig. 7, P10-P19, P20-P29, P30-P39, and P40-P49 are bits of the second partial product, bits of the third partial product, bits of the fourth partial product, and bits of the fifth partial product in this order.
The present embodiment provides a Booth multiplier based on the previous embodiment,
the external input signal includes: an externally input carry control signal and an externally input sign bit control signal.
The partial accumulation and addition module 30 is further configured to input the sign correction bit of the last Booth multiplier to the carry port of the current Booth multiplier as an input carry signal when the sign bit control signal is at a low potential.
The partial accumulation and addition module 30 is further configured to input the sign correction bit of the current Booth multiplier to the carry port of the current Booth multiplier when the sign bit control signal is at a high potential.
In this embodiment, when the sign bit control signal is at a low level, it represents that sign bit correction is required, that is, the Booth multiplier is performing low-precision operation or performing high-order operation of the multiplicand in the mixed-precision operation, and the low level is in a low-voltage state, that is, 0; when the sign bit control signal is high potential, the sign bit control signal represents low level input to the sign bit without correcting the sign bit, namely, the Booth multiplier performs low-level operation of a multiplicand in the mixed precision operation; the high level is a state where the voltage is high, i.e., 1.
The present embodiment provides a Booth multiplier based on the previous embodiment,
The partial accumulation adding module 30 is further configured to operate on the high order bits of the multiplicand when the carry control signal is at a low potential; at this time, the carry input port of the partial accumulation adding module 30 where the high order of the multiplicand is located receives the carry signal outputted from the partial accumulation adding module 30 where the low order of the multiplicand is located, which means that the mixed precision operation is being performed, and when the carry control signal is at the high level, which means that the mixed precision operation is being performed, the low order of the multiplicand is being performed; or, a low-precision operation is being performed.
The embodiment provides control logic of a carry control signal, and selection of a calculation mode of the Booth multiplier can be realized by combining the carry control signal with the sign bit extension signal in the previous embodiment; by selecting a proper calculation mode for a plurality of Booth multipliers, a plurality of Booth multipliers can be spliced to realize mixed precision operation. The partial product accumulation module 30 may be implemented by a partial product accumulation circuit shown in fig. 4, where the partial product accumulation circuit is composed of a plurality of inverters, a plurality of half-adders, and a plurality of data selectors, ppn [ m ] is a value of an mth bit of an nth partial product, in [ k ] is a symbol correction signal generated by a symbol correction bit, ctrl signal is an external input signal, cin is a carry signal, the carry signal is obtained according to the symbol correction bit or is output by a partial product accumulation module 30 of a previous stage, prod [ q ] is a q bit of a partial sum, and Count [ n ] is a symbol bit of the nth partial product, where m, n, k, p, q are non-negative positive integers.
In one embodiment, the present invention provides a hybrid Booth multiplier, including a Booth multiplier described in any one of the foregoing embodiments, that is, a first Booth multiplier and a second Booth multiplier, to implement n-bit by 2 n-bit hybrid precision multiplication calculation, where the computing power of a single Booth multiplier, that is, the size of n, can be changed by modifying the number of encoders in the encoding modules in the first Booth multiplier and the second Booth multiplier, the number of partial product generators in the partial product generating module, and the number of adder arrays in the partial accumulation adding module.
The first Booth multiplier includes: the device comprises a first coding module, a first partial product generating module and a first partial accumulating and adding module; a second Booth multiplier comprising: the device comprises a second coding module, a second partial product generating module and a second partial product accumulating module.
The first encoding module and the second encoding module encode the n-bit multiplier according to the method of the foregoing embodiment, and provide the n-bit multiplier to the partial product generating module.
The first partial accumulation adding module inputs a low level to the sign bit of the first partial product according to an external input signal, directly performs accumulation operation on the first partial product to obtain an output carry signal and a first partial sum, and provides the output carry signal COUT and the first partial sum prodL for the second Booth multiplier; the first partial product is the partial product of the product between the low order bits of the multiplier and the multiplicand.
The second Booth multiplier is connected with the first Booth multiplier, receives a carry output signal COUT provided by the first partial accumulation and addition module according to an external input signal, performs correction operation on sign bits of the second partial product, and performs accumulation operation on the second partial product to obtain a second part and prodH; the second partial product is the partial product of the product between the high order of the multiplier and the multiplicand.
And the second part accumulation adding module is used for obtaining a product result of the multiplier and the multiplicand according to the first part and the prodL, the second part and the prodH.
In this embodiment, multiplication calculation of n bits multiplied by 2n bits can be implemented by combining the first Booth multiplier and the second Booth multiplier, where the Booth multiplier has an adder therein, whose number is ceil (n/2) ×1, where the ceil function is an upward rounding function; for example: referring to fig. 5 of the specification, the hybrid Booth multiplier can implement 9-bit and 18-bit hybrid precision multiplication, for a first partial accumulation module of the operational multiplier B and the multiplicand low bit AL, the input carry of the lowest bit of 5 x 10 full adders is connected with the sign correction bits am0 to am4, and for a second partial accumulation module of the operational multiplier B and the multiplicand high bit AH, the input carry of the lowest bit of 5 x 10 full adders is connected with the output carry of the first partial accumulation module. The partial product accumulation module for calculating the AL is directly accumulated by controlling the partial accumulation module through an external input signal without considering symbol bit optimization, and the partial accumulation module for calculating the AH is required to process the symbol bit. The partial product accumulation module is used for executing accumulation of the mixed precision operation part sum, compared with the traditional splicing scheme, the adder is saved, the whole circuit area is reduced on the premise of not reducing the operation precision, the time sequence is optimized, and the performance of the multiplier is greatly improved.
In one embodiment, the present invention provides a hybrid Booth multiplier, including a Booth multiplier described in any one of the foregoing embodiments, that is, a first Booth multiplier, a second Booth multiplier, a third Booth multiplier, a fourth Booth multiplier, and an adder; to realize the mixed precision multiplication of 18 bits by 18 bits, the multiplication of 2n bits by 2n bits can also be realized by modifying the number of encoders in the encoding module, the number of partial product generators in the partial product generation module, and the number of adder arrays in the partial accumulation addition module in the Booth multiplier, wherein n is determined by the calculation capability of a single Booth multiplier;
a first partial accumulation module in the first Booth multiplier for calculating a first partial product between the low bit BL of the multiplier and the low bit AL of the multiplicand; a second partial accumulation adding module in the second Booth multiplier for calculating a second partial product between the high bit BH of the multiplier and the low bit AL of the multiplicand; a third partial accumulation adding module in the third Booth multiplier for calculating a third partial product between the low bit BL of the multiplier and the high bit AH of the multiplicand; a fourth partial accumulation module in the fourth Booth multiplier for calculating a fourth partial product between the high bit BH of the multiplier and the high bit AH of the multiplicand;
The first partial sum, the second partial sum, the third partial sum and the fourth partial sum are obtained by respectively summing the first partial product, the second partial product, the third partial product and the fourth partial product through a first partial product accumulation module, a second partial product accumulation module, a third partial product accumulation module and a fourth partial product accumulation module;
the first partial product accumulation module outputs a first product result prod0 in the first partial sum and provides a first part to be operated in the first partial sum to the second partial product accumulation module; the second partial product accumulation module outputs a second product result prod2 in the second partial sum, and provides a second part to be operated of the second partial sum for the third partial accumulation and addition module and the adder; the third partial product accumulation module provides a third partial sum to the adder; the adder provides a third part to be operated according to the second part sum, the third part sum and the fourth part accumulation adding module and outputs a third multiplication result prod1; the fourth partial product accumulation module outputs a fourth product result prod3 according to the third part to be operated and the fourth part sum;
and obtaining the product result of the multiplier and the multiplicand by splicing the first product result, the second product result, the third product result and the fourth product result.
In this embodiment, multiplication calculation of multiplying 2n bits by 2n bits can be implemented through the first Booth multiplier, the second Booth multiplier, the third Booth multiplier, and the fourth Booth multiplier, for example: referring to fig. 6 of the specification, the hybrid Booth multiplier can implement 18-bit and 18-bit hybrid precision multiplication, for a partial accumulation adding module (i.e. partial accumulation adding module for calculating al×bl and al×bh) involving the low-order AL of the multiplicand, the input carry of the lowest order of the 5×10 full adders is connected with sign correction bits am0 to am4, and for the partial accumulation adding module involving the high-order AH of the multiplicand, the input carry of the lowest order of the 5×10 full adders is connected with the output carry of the corresponding al×bl and the output carry of al×bh; the partial product addition module for the low order AL of the multiplicand is not required to consider sign bit optimization, and the partial product addition module for the high order AH of the multiplicand is required to process sign bits. The partial product accumulation module is used for accumulating the partial sums of the mixed precision operation, compared with the traditional splicing scheme (the scheme that the traditional multiplier supports the mixed precision operation, the multiplier and the multiplicand are usually required to be divided into a lower order and a higher order, and are respectively combined and input into four multipliers to obtain the partial sums, then the shifting and summing operation is carried out, and the summing operation usually requires four adders to be consumed), the adder is saved; on the premise of not reducing the operation precision, the whole circuit area is reduced, the time sequence is optimized, and the performance of the multiplier is greatly improved.
In one embodiment, referring to fig. 9 of the specification, the present invention provides a method for operating a Booth multiplier, including:
s110, the multiplier is encoded based on a Booth algorithm, and a corresponding encoded signal is obtained.
S120, processing the multiplicand according to the coded signal to generate a plurality of partial products and a plurality of sign correction bits.
S130, calculating the sum of the sign bits of the partial product according to the sign bits of the partial product.
S140, selecting a corresponding calculation mode according to an external input signal.
S150, selecting an input carry signal of a carry port of the Booth multiplier according to the calculation mode and a plurality of sign correction bits; and revising sign bits of the partial product according to the calculation mode and the input carry signal.
S160, according to the calculation mode, performing accumulation operation on a plurality of partial products, and combining the sum of sign bits of the revised partial products to obtain a product result of the multiplier and the multiplicand.
In the embodiment, the partial product is only subjected to shift operation and inversion operation by generating the symbol correction bit, and is in different calculation modes by an external input signal, so that the Booth multiplier can complete partial product accumulation and symbol bit calculation in different calculation modes, and finally the product result is solved.
The present embodiment provides a method for operating a Booth multiplier based on the foregoing embodiment, and step S130 includes:
the external input signal includes: an externally input carry control signal and an externally input sign bit control signal;
when the carry control signal is at a low potential, calculating the high bit of the multiplicand;
when the carry control signal is at a high potential, calculating the low bit of the multiplicand;
when the sign bit control signal is at a low potential, the sign correction bit of the last Booth multiplier is used as an input carry signal and is input to a carry port of the current Booth multiplier;
when the sign bit control signal is in a high potential, the sign correction bit of the current Booth multiplier is input to a carry port of the current Booth multiplier;
selecting a corresponding calculation mode according to the carry control signal and the sign bit control signal; the calculation mode includes: a low-precision operation mode between the multiplicand and the multiplier, and a mixed-precision operation mode between the multiplicand and the multiplier; the mixed precision operation mode includes: an operation between the low order of the multiplicand and the low order of the multiplier, an operation between the high order of the multiplicand and the high order of the multiplier, and an operation between the low order of the multiplicand and the high order of the multiplier.
The present embodiment provides a calculation mode in which an external input signal controls a Booth multiplier, for example: a Booth multiplier is controlled by a 2-bit ctrl signal, a carry control signal is used for controlling carry, a carry is controlled by ctrl [0], and a sign control signal is used for controlling sign calculation; when the ctrl signal is "00", the high-order AH representing the multiplicand participates in the operation, i.e., the Booth multiplier is calculating AH BL or AH BH; when the ctrl signal is "01", it represents that low-precision multiplication is being performed; when ctrl signal "11" is present, the lower AL representing the multiplicand participates in the operation, i.e., the Booth multiplier is calculating AL BH or AL BL.
The present embodiment provides a method for operating a Booth multiplier based on the foregoing embodiment, and step S130 includes:
inverting the sign bit of the partial product;
substituting the sign bit of the partial product after the inversion and the summation calculation into a sign bit expansion formula, and calculating to obtain the sum of the sign bits of the partial product. The sign bit expansion formula can be adopted for expanding the sign bit; the sign bit expansion formula is as follows:
；
where SIGN is the SIGN of the partial sum, s0 is the SIGN of the first partial product, s1 is the SIGN of the second partial product, s2 is the SIGN of the third partial product, s3 is the SIGN of the fourth partial product, s4 is the SIGN of the fifth partial product; the sign bit expansion formula may calculate the sum of sign bits of partial products, where the partial products include: a first partial product, a second partial product, a third partial product, and a fourth partial product.
The present embodiment sums the calculated formulas by inverting the sign bits of the partial product:the method comprises the steps of carrying out a first treatment on the surface of the The sign bit of the partial product is taken as the trans: />And the above sign bit expansion formula is carried in.
Obtaining a sign bit expansion formula after inverting the sign bit:
where sj is the inverse of the sign bit of the jth partial product.
Through the sign bit expansion formula after inverting the sign bit, the sign bit can be processed in an inverting way, and the number of adders in the adder array can be reduced.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (11)

1. A Booth multiplier, comprising:
the encoding module is used for encoding the multiplier based on a Booth algorithm to obtain a corresponding encoded signal, and transmitting the encoded signal to the partial product generating module;
the partial product generating module is connected with the encoding module and is used for processing the multiplicand according to the encoding signal to generate a plurality of partial products and a plurality of symbol correction bits, and transmitting the partial products and the symbol correction bits to the partial accumulation adding module;
The partial product accumulation module is connected with the partial product generation module and is used for calculating the sum of the sign bits of the partial product according to the sign bits of a plurality of partial products;
the part accumulation module is also used for selecting a corresponding calculation mode according to an external input signal;
the partial accumulation adding module is further used for selecting an input carry signal of a carry port of the Booth multiplier according to the calculation mode and a plurality of sign correction bits; revising sign bits of the partial product according to the calculation mode and the input carry signal;
the partial accumulation adding module is further configured to perform an accumulation operation on a plurality of partial products according to the calculation mode, and combine the modified sum of sign bits of the partial products to obtain a product result of the multiplier and the multiplicand.
2. A Booth multiplier as claimed in claim 1, wherein,
the partial product generating module is further configured to shift and/or invert the multiplicand according to the encoded signal, so as to obtain the partial product;
the partial product generating module is further configured to set a symbol correction bit corresponding to the encoded signal according to whether the encoded signal is positive or negative.
3. A Booth multiplier as claimed in claim 1, wherein,
and the partial product accumulation module is used for inverting the sign bit of the partial product, substituting the inverted sign bit of the partial product and the summation calculation formula into a sign bit expansion formula, and calculating to obtain the sum of the sign bits of the partial product.
4. A Booth multiplier as claimed in claim 1, wherein,
the external input signal includes: an externally input carry control signal and an externally input sign bit control signal;
the partial accumulation adding module is further configured to input the sign correction bit of the previous Booth multiplier to a carry port of the current Booth multiplier as an input carry signal when the sign bit control signal is at a low potential;
the partial accumulation adding module is further configured to input the sign correction bit of the current Booth multiplier to a carry port of the current Booth multiplier when the sign bit control signal is at a high potential.
5. A Booth multiplier as claimed in claim 4, wherein,
the partial accumulation adding module is further used for calculating the high bit of the multiplicand when the carry control signal is at a low potential; and when the carry control signal is at a high potential, calculating the low order of the multiplicand.
6. A Booth multiplier as claimed in claim 1, wherein,
the computing mode includes: a low precision mode of operation between the multiplicand and the multiplier, a hybrid precision mode of operation between the multiplicand and the multiplier; the mixed precision operation mode comprises the following steps: an operation between a low order of the multiplicand and a low order of the multiplier, an operation between a high order of the multiplicand and a high order of the multiplier, an operation between a low order of the multiplicand and a high order of the multiplier.
7. Hybrid Booth multiplier, characterized by comprising one Booth multiplier according to any of claims 1 to 6, namely a first Booth multiplier and a second Booth multiplier,
the first Booth multiplier includes: the device comprises a first coding module, a first partial product generating module and a first partial accumulating and adding module; the second Booth multiplier includes: the second coding module, the second partial product generating module and the second partial product accumulating module;
the first partial accumulation adding module inputs low level to the sign bit of a first partial product according to an external input signal, directly performs accumulation operation on the first partial product to obtain an output carry signal and a first partial sum, and provides the output carry signal and the first partial sum for the second Booth multiplier; the first partial product is a partial product result between the multiplier and the low order bits of the multiplicand;
The second Booth multiplier is connected with the first Booth multiplier, performs correction operation on sign bits of a second partial product according to an external input signal, and performs accumulation operation on the second partial product to obtain a second partial sum; the second partial product is a partial product result between the multiplier and the high order bits of the multiplicand;
and the second part accumulation adding module obtains the product result of the multiplier and the multiplicand according to the first part sum and the second part sum.
8. A hybrid Booth multiplier, comprising four Booth multipliers according to any one of claims 1 to 6, namely a first Booth multiplier, a second Booth multiplier, a third Booth multiplier, a fourth Booth multiplier, and an adder;
a first partial accumulation module in the first Booth multiplier for calculating a first partial product between the low order of the multiplier and the low order of the multiplicand; a second partial accumulation module in the second Booth multiplier for calculating a second partial product between the high order of the multiplier and the low order of the multiplicand; a third partial accumulation module in the third Booth multiplier for calculating a third partial product between the low order of the multiplier and the high order of the multiplicand; a fourth partial accumulation module in the fourth Booth multiplier for calculating a fourth partial product between the high order of the multiplier and the high order of the multiplicand;
Summing the first partial product, the second partial product, the third partial product and the fourth partial product respectively through the first partial product accumulation and addition module, the second partial product accumulation module, the third partial product accumulation module and the fourth partial product accumulation and addition module to obtain a first partial sum, a second partial sum, a third partial sum and a fourth partial sum;
the first part accumulation adding module outputs a first product result in the first part sum and provides a first part to be operated in the first part sum to the second part accumulation adding module; the second partial product accumulation module outputs a second product result in the second partial sum and provides a second part to be operated of the second partial sum to the third partial product accumulation module and the adder; the third partial product accumulation module providing the third partial sum to the adder; the adder provides a third part to be operated according to the second part sum, the third part sum and the fourth part accumulation adding module and outputs a third multiplication result; the fourth partial product accumulation module outputs a fourth product result according to the third part to be operated and the fourth partial sum;
And obtaining the product result of the multiplier and the multiplicand by splicing the first product result, the second product result, the third product result and the fourth product result.
9. A method of operating a Booth multiplier, comprising:
encoding the multiplier based on a Booth algorithm to obtain a corresponding encoded signal;
processing the multiplicand according to the coding signal to generate a plurality of partial products and a plurality of sign correction bits;
calculating to obtain the sum of the sign bits of the partial product according to the sign bits of the partial product;
selecting a corresponding calculation mode according to an external input signal;
selecting an input carry signal of a carry port of a Booth multiplier according to the calculation mode and a plurality of sign correction bits; revising sign bits of the partial product according to the calculation mode and the input carry signal;
and according to the calculation mode, performing accumulation operation on a plurality of partial products, and combining the sum of sign bits of the corrected partial products to obtain a product result of the multiplier and the multiplicand.
10. The method of claim 9, wherein selecting the corresponding calculation mode according to the external input signal comprises:
The external input signal includes: an externally input carry control signal and an externally input sign bit control signal;
when the carry control signal is at a low potential, calculating the high order of the multiplicand;
when the carry control signal is at a high potential, calculating the low order of the multiplicand;
when the sign bit control signal is of low potential, the sign correction bit of the last Booth multiplier is used as an input carry signal to be input to a carry port of the current Booth multiplier;
when the sign bit control signal is in a high potential, the sign correction bit of the current Booth multiplier is input to a carry port of the current Booth multiplier;
selecting a corresponding calculation mode according to the carry control signal and the sign bit control signal; the computing mode includes: a low precision mode of operation between the multiplicand and the multiplier, a hybrid precision mode of operation between the multiplicand and the multiplier; the mixed precision operation mode comprises the following steps: an operation between a low order of the multiplicand and a low order of the multiplier, an operation between a high order of the multiplicand and a high order of the multiplier, an operation between a low order of the multiplicand and a high order of the multiplier.
11. The method of claim 9, wherein the calculating the sum of the sign bits of the partial product according to the sign bits of the partial product comprises:
inverting the sign bit of the partial product;
substituting the sign bit of the partial product after the inversion and the summation calculation formula into a sign bit expansion formula, and calculating to obtain the sum of the sign bits of the partial product.
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