CN116995155A - Monitoring method for annealing uniformity of chip - Google Patents
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- CN116995155A CN116995155A CN202311108539.4A CN202311108539A CN116995155A CN 116995155 A CN116995155 A CN 116995155A CN 202311108539 A CN202311108539 A CN 202311108539A CN 116995155 A CN116995155 A CN 116995155A
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- 238000000137 annealing Methods 0.000 title claims abstract description 137
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000012544 monitoring process Methods 0.000 title claims abstract description 48
- 235000012431 wafers Nutrition 0.000 claims abstract description 131
- 238000001514 detection method Methods 0.000 claims abstract description 10
- 238000000429 assembly Methods 0.000 claims abstract description 9
- 230000000712 assembly Effects 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims description 34
- 230000000694 effects Effects 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 17
- 230000008569 process Effects 0.000 description 11
- 239000007789 gas Substances 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 229910002704 AlGaN Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- UOSXPFXWANTMIZ-UHFFFAOYSA-N cyclopenta-1,3-diene;magnesium Chemical compound [Mg].C1C=CC=C1.C1C=CC=C1 UOSXPFXWANTMIZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The invention provides a method for monitoring annealing uniformity of a chip, which comprises the following steps: firstly, providing a plurality of wafers, forming a plurality of epitaxial light-emitting layers on each wafer, secondly, forming an N-type contact assembly on each epitaxial light-emitting layer corresponding to each wafer, annealing the N-type contact assembly, thirdly, forming a P-type contact assembly on each epitaxial light-emitting layer in each wafer, annealing the P-type contact assembly, thirdly, forming an electrode assembly on each epitaxial light-emitting layer in each wafer to obtain a plurality of chip structures, and finally, detecting voltages of the areas of each chip structure corresponding to the electrode assemblies in the wafers, and monitoring annealing uniformity of each wafer in different areas according to detection results; the method can monitor the annealing effect of each wafer in the whole area more effectively, and further can improve the production yield of the chip structure effectively.
Description
Technical Field
The invention relates to the field of semiconductor photoelectricity, in particular to a method for monitoring annealing uniformity of a chip.
Background
The rapid thermal annealing process (Rapid Thermal Annealing, RTA) has important applications in the modern semiconductor industry that can be raised very rapidly and for a short duration at a target temperature to thermally anneal a semiconductor chip, the rapid temperature rise process and short duration being effective to repair lattice defects, activate impurities and diffuse metals, thereby forming good ohmic contacts.
Because the means for monitoring the temperature in the rapid annealing furnace is single, the temperature of each area of the wafer is set to be a fixed value, when the rapid thermal annealing process is carried out, the wafer can respond differently to the temperature of different areas of the rapid thermal annealing process, and only partial position measurement voltage data of the wafer (generally only 2 edge positions and 1 center position are selected on each wafer for voltage measurement) can not be effectively monitored on the annealing effect of different areas of the whole annealing furnace and the annealing effect of the whole wafer surface, so that the annealing effect difference among batches of the previous process is overlarge, and the wafer treated by the rapid thermal annealing process has the phenomenon that only partial areas can be normally used, thereby influencing the production efficiency and the chip yield.
Therefore, a method for monitoring the annealing uniformity of the chip is needed to solve the above technical problems.
Disclosure of Invention
The invention aims to provide a method for monitoring the annealing uniformity of a chip, which is used for solving the technical problem that the existing method for monitoring the annealing uniformity of the chip cannot effectively monitor the annealing effect of an entire wafer.
In order to solve the technical problems, the invention provides a method for monitoring the annealing uniformity of a chip, which comprises the following steps:
s10, providing a plurality of wafers, and forming a plurality of epitaxial light-emitting layers on each wafer;
s20, forming an N-type contact assembly on each epitaxial light-emitting layer corresponding to each wafer, and annealing the N-type contact assemblies;
s30, forming a P-type contact assembly on each epitaxial light-emitting layer in each wafer, and annealing the P-type contact assemblies;
s40, forming an electrode assembly on each epitaxial light-emitting layer in each wafer to obtain a plurality of chip structures;
and S50, detecting the voltage of the area of each chip structure corresponding to the electrode assembly in the wafer, and monitoring the annealing uniformity of each wafer in different areas according to the detection result.
Preferably, in the step S10, the epitaxial light emitting layer includes an N-type semiconductor layer, a quantum well active layer, and a P-type semiconductor layer, which are sequentially stacked, the N-type semiconductor layer has a stepped structure, and an area of the N-type semiconductor layer is larger than an area of the quantum well active layer.
Preferably, the step S20 specifically includes:
s201, forming an N-type contact assembly at a step-shaped structure of each N-type semiconductor layer corresponding to each wafer, wherein the N-type contact assembly comprises a first ohmic contact layer and a second ohmic contact layer which are arranged at intervals;
and S202, respectively annealing the first ohmic contact layer and the second ohmic contact layer.
Preferably, in the annealing treatment step of step S202, the annealing temperature is 900 ℃, the annealing time is 75S, and the annealing atmosphere is N 2 The gas flow rate of the atmosphere was 9sccm.
Preferably, the step S30 specifically includes:
s301, forming a P-type contact assembly on each corresponding P-type semiconductor layer in each wafer, wherein the P-type contact assembly comprises a third ohmic contact layer and a fourth ohmic contact layer which are arranged at intervals;
and S302, respectively annealing the third ohmic contact layer and the fourth ohmic contact layer.
Preferably, in the annealing treatment step of S302, the annealing temperature is 600 ℃, the annealing time is 180S, and the annealing atmosphere is N 2 With O 2 In the mixed atmosphere of (2), N in the annealing atmosphere 2 Is introduced into the flow of gasIn an amount of 5sccm, O in an annealing atmosphere 2 The gas inlet flow rate of (2) was 1sccm.
Preferably, the step S40 specifically includes:
s401, forming a first N-type electrode on the first ohmic contact layer and forming a second N-type electrode on the second ohmic contact layer;
s402, forming a first P-type electrode on the third ohmic contact layer, and forming a second P-type electrode on the fourth ohmic contact layer.
Preferably, the step S50 specifically includes:
s501, in each chip structure of each wafer, the voltage between the first P-type electrode and the second P-type electrode is recorded as V1, and the V1 is compared with a standard voltage value to monitor the annealing uniformity of each wafer in different areas.
Preferably, the step S50 specifically includes:
s501, in each chip structure of each wafer, the voltage between the first N-type electrode and the second N-type electrode is recorded as V2, and the V2 is compared with a standard voltage value to monitor the annealing uniformity of each wafer in different areas.
Preferably, the step S50 specifically includes:
s501, in each chip structure of each wafer, any one of the voltage between the first N-type electrode and the first P-type electrode and the voltage between the second N-type electrode and the second P-type electrode is recorded as V3, and the V3 is compared with a standard voltage value to monitor the annealing uniformity of each wafer in different areas.
The beneficial effects of the invention are as follows: different from the condition of the prior art, the invention provides a method for monitoring the annealing uniformity of a chip, which comprises the following steps: firstly, providing a plurality of wafers, forming a plurality of epitaxial light-emitting layers on each wafer, secondly, forming an N-type contact assembly on each epitaxial light-emitting layer corresponding to each wafer, annealing the N-type contact assembly, thirdly, forming a P-type contact assembly on each epitaxial light-emitting layer in each wafer, annealing the P-type contact assembly, thirdly, forming an electrode assembly on each epitaxial light-emitting layer in each wafer to obtain a plurality of chip structures, and finally, detecting voltages of the areas of each chip structure corresponding to the electrode assemblies in the wafers, and monitoring annealing uniformity of each wafer in different areas according to detection results; according to the method, after each chip structure in the wafers is annealed twice, the voltage detection is carried out on the area of each chip structure corresponding to the electrode assembly in the wafers, and compared with the existing monitoring method for the annealing uniformity of the chips, the voltage detection is only carried out on three points in each wafer, and the annealing effect of each wafer in the whole area can be monitored more effectively, so that the production yield of the chip structures can be improved effectively.
Drawings
FIG. 1 is a flowchart of a method for monitoring the annealing uniformity of a chip according to an embodiment of the present invention;
fig. 2A to fig. 2E are schematic structural diagrams of a method for monitoring annealing uniformity of a chip according to an embodiment of the invention;
FIG. 3 is a schematic diagram of marking a plurality of wafers in a method for monitoring the uniformity of annealing a chip according to an embodiment of the present invention;
FIG. 4 is a graph showing the V2 voltage data of each wafer in FIG. 3 over all regions.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
The invention provides a method for monitoring the annealing uniformity of a chip, which comprises the following embodiments and the combination of the following embodiments.
Referring to fig. 1 and fig. 2A to fig. 2E, fig. 1 is a flowchart of a method for monitoring annealing uniformity of a chip according to an embodiment of the present invention; fig. 2A to fig. 2E are schematic structural diagrams of a method for monitoring annealing uniformity of a chip according to an embodiment of the invention; the method for monitoring the annealing uniformity of the chip comprises the following steps.
S10, a plurality of wafers 100 are provided, and a plurality of epitaxial light emitting layers 20 are formed on each wafer 100.
Specifically, the step S10 further includes:
firstly, providing a plurality of wafers 100, wherein the wafers 100 are made of silicon; thereafter, the plurality of wafers 100 are transferred to a MOCVD (metal organic chemical vapor deposition) apparatus of the model Veeco K465i for sequentially epitaxially growing an N-type semiconductor layer 201, a quantum well active layer 202 and a P-type semiconductor layer 203, wherein a high purity H is employed 2 Or high purity N 2 Or high purity H 2 And high purity N 2 High purity NH using the mixed gas of (2) as carrier gas 3 Trimethylgallium (TMGa) as the source of N, silane (SiH) 4 ) Trimethylaluminum (TMAL) as an aluminum source, magnesium dicyclopentadiene (CP 2 Mg) is used as a P-type dopant, and the pressure of a reaction cavity in the MOCVD equipment is controlled to be 20-100 torr.
Then, the N-type semiconductor layer 201, the quantum well active layer 202 and the P-type semiconductor layer 203 are etched by a photolithography process, so that the N-type semiconductor layer 201 has a step structure, the area of the N-type semiconductor layer 201 is larger than that of the quantum well active layer 202, the area of the quantum well active layer 202 is equal to that of the P-type semiconductor layer 203, and at this time, the N-type semiconductor layer 201, the quantum well active layer 202 and the P-type semiconductor layer 203 form the epitaxial light-emitting layer 20, as shown in fig. 2A.
Specifically, the material of the N-type semiconductor layer 201 is an Si-doped AlGaN material, and the growth temperature of the N-type semiconductor layer 201 is between 900 ℃ and 1200 ℃; the material of the P-type semiconductor layer 203 is an Mg-doped AlGaN material, and the growth temperature of the P-type semiconductor layer 203 is between 700 ℃ and 1100 ℃.
Specifically, the quantum well active layer 202 includes at least one potential well layer and at least two composite barrier layers alternately arranged, each potential well layer being interposed between two adjacent composite barrier layers, the growth temperature of the quantum well active layer 202 being between 900 degrees celsius and 1200 degrees celsius;
wherein the potential well layer is made of Al x1 Ga y1 The relationship between N, x1 and y1 is: 15% < x1 < 70%, and x1+y1=1; the material of the barrier layer is Al x2 Ga y2 The relationship between N, x2 and y2 is: 30% < x2 < 95%, and x2+y2=1.
S20, forming an N-type contact assembly 21 on each epitaxial light-emitting layer 20 corresponding to each wafer 100, and annealing the N-type contact assembly 21;
specifically, S20 further includes:
s201, forming N-type contact elements 21 at the step-like structure of each N-type semiconductor layer 201 corresponding to each wafer 100, where the N-type contact elements 21 include a first ohmic contact layer 211 and a second ohmic contact layer 212 disposed at intervals;
s202, annealing the first ohmic contact layer 211 and the second ohmic contact layer 212 in an annealing furnace, respectively, is performed as shown in fig. 2B.
Preferably, in the annealing treatment step of step S202, the annealing temperature is 900 ℃, the annealing time is 75S, and the annealing atmosphere is N 2 The gas flow rate of the atmosphere was 9sccm.
Specifically, the materials of the first ohmic contact layer 211 and the second ohmic contact layer 212 each include at least one of Cr, al, ti, au, pt, ni.
S30, forming a P-type contact assembly 22 on each epitaxial light-emitting layer 20 in each wafer 100, and annealing the P-type contact assembly 22.
Specifically, S30 further includes:
s301, forming a P-type contact element 22 on each corresponding P-type semiconductor layer 203 in each wafer 100, wherein the P-type contact element 22 comprises a third ohmic contact layer 221 and a fourth ohmic contact layer 222 which are arranged at intervals;
s302, annealing the third ohmic contact layer 221 and the fourth ohmic contact layer 222 in an annealing furnace, respectively, as shown in fig. 2C.
Preferably, in the annealing treatment step of S302, the annealing temperature is 600 ℃, the annealing time is 180S, and the annealing atmosphere is N 2 With O 2 In the mixed atmosphere of (2), N in the annealing atmosphere 2 The gas inlet flow rate of (2) is 5sccm, O in annealing atmosphere 2 The gas inlet flow rate of (2) was 1sccm.
Specifically, the materials of the third ohmic contact layer 221 and the fourth ohmic contact layer 222 are metal oxides such as ITO. In this case, since the P-type contact element 22 and the N-type contact element 21 are made of different materials, different annealing conditions need to be designed.
S40, an electrode assembly 23 is formed on each epitaxial light emitting layer 20 in each wafer 100to obtain a plurality of chip structures 200.
Specifically, S40 further includes:
s401, forming a first N-type electrode 231 on the first ohmic contact layer 211 and a second N-type electrode 232 on the second ohmic contact layer 212;
s402, a first P-type electrode 233 is formed on the third ohmic contact layer 221, and a second P-type electrode 234 is formed on the fourth ohmic contact layer 222, as shown in fig. 2D.
In the embodiment of the present invention, the electrode assembly 23 is a multi-layered composite metal material containing aluminum; the P-type contact members 22, the N-type contact members 21, and the electrode members 23 may be of any number and shape, and may be regularly or irregularly arranged. Preferably, the P-type contact elements 22 are in a circular pattern and the N-type contact elements 21 are in a square pattern, which is designed to facilitate distinguishing the P-type contact elements 22 from the N-type contact elements 21.
S50, detecting the voltage of the area of each chip structure 200 corresponding to the electrode assembly 23 in the wafer 100, and monitoring the annealing uniformity of each wafer 100 in different areas according to the detection result.
Specifically, S50 further includes:
in the first embodiment, in each chip structure 200 of each wafer 100, the voltage between the first P-type electrode 233 and the second P-type electrode 234 is denoted as V1, and V1 is compared with a standard voltage value to monitor the annealing uniformity of each wafer 100 in different regions.
In a second embodiment, in each chip structure 200 of each wafer 100, the voltage between the first N-type electrode 231 and the second N-type electrode 232 is denoted as V2, and V2 is compared with a standard voltage value to monitor the annealing uniformity of each wafer 100 in different regions.
In the third embodiment, in each chip structure 200 of each wafer 100, any one of the voltages between the first N-type electrode 231 and the first P-type electrode 233, and the voltage between the second N-type electrode 232 and the second P-type electrode 234 is denoted as V3, and V3 is compared with a standard voltage value to monitor the annealing uniformity of each wafer 100 in different regions.
Further, the measured wafer 100 may remove the electrode assembly 23 with the metal material on the top surface, and deposit the corresponding electrode assembly 23 for monitoring after annealing when necessary, so as to achieve the purpose of recycling.
The effect of the foregoing method for monitoring the uniformity of annealing of a chip is described by way of specific examples and comparative examples.
Example 1
The specific steps of the method for monitoring the annealing uniformity of the chip in this embodiment 1 are as follows:
s10, a plurality of wafers 100 are provided, and a plurality of epitaxial light emitting layers 20 are formed on each wafer 100.
The material of the N-type semiconductor layer 201 is an Si-doped AlGaN material, and the material of the P-type semiconductor layer 203 is an Mg-doped AlGaN material; the quantum well active layer 202 comprises at least one potential well layer and at least two composite barrier layers which are alternately arranged, wherein each potential well layer is inserted between two adjacent composite barrier layers, and the material of the potential well layer is Al x1 Ga y1 N, and x1 is 0.5, y1 is 0.5; the material of the barrier layer is Al x2 Ga y2 N, and x2 is 0.65, y2 is 0.35.
S20, forming N-type contact assemblies 21 at the step-shaped structures of each N-type semiconductor layer 201 corresponding to each wafer 100, wherein the N-type contact assemblies 21 comprise first ohmic contact layers 211 and second ohmic contact layers 212 which are arranged at intervals; then, annealing the first ohmic contact layer 211 and the second ohmic contact layer 212 in an annealing furnace at the same timeThe temperature is 900 ℃, the annealing time is 75s, and the annealing atmosphere is N 2 The gas flow rate of the atmosphere was 9sccm. Specifically, the material of the first ohmic contact layer 211 and the second ohmic contact layer 212 is Cr.
S30, forming a P-type contact assembly 22 on each corresponding P-type semiconductor layer 203 in each wafer 100, wherein the P-type contact assembly 22 comprises a third ohmic contact layer 221 and a fourth ohmic contact layer 222 which are arranged at intervals; then annealing the third ohmic contact layer 221 and the fourth ohmic contact layer 222 in an annealing furnace at 600 ℃ for 180s under N 2 With O 2 In the mixed atmosphere of (2), N in the annealing atmosphere 2 The gas inlet flow rate of (2) is 5sccm, O in annealing atmosphere 2 The gas inlet flow rate of (2) was 1sccm.
Specifically, the materials of the third ohmic contact layer 221 and the fourth ohmic contact layer 222 are ITO.
S40, forming a first N-type electrode 231 on the first ohmic contact layer 211 and a second N-type electrode 232 on the second ohmic contact layer 212; meanwhile, a first P-type electrode 233 is formed on the third ohmic contact layer 221, and a second P-type electrode 234 is formed on the fourth ohmic contact layer 222, and the electrode assembly 23 is aluminum.
S50, in each chip structure 200 of each wafer 100, voltage data between the first N-type electrode 231 and the second N-type electrode 232 are obtained by an MPI tester (high-low temperature 8 inch semiautomatic high-pressure bench) and recorded as V2, and then the V2 and a standard voltage value (0.8+/-0.2V) are compared in image distribution software to monitor the annealing uniformity of each wafer 100 in different areas; wherein the standard voltage value is determined according to the chip structure 200 and the chip fabrication process).
Specifically, referring to fig. 3 and fig. 4, fig. 3 is a schematic diagram illustrating a marking of a plurality of wafers 100 in the method for monitoring the uniformity of annealing chips according to the embodiment of the invention; fig. 4 is a diagram of V2 voltage data for each wafer 100 of fig. 3 in all regions.
As can be seen from fig. 4, the V2 value of the left near half area (A1, A2, A3, A4) of the first, fifth, ninth, and thirteenth wafers ranges from 1.1V to 2.7V, which is higher than the standard voltage value (0.8±0.2V); the V2 value of the right near half area (B1, B2, B3, B4) of the fourth wafer, the eighth wafer, the tenth wafer and the sixteenth wafer ranges from 1.1V to 2.7V, and is higher than the standard voltage value (0.8+/-0.2V); the V2 value of the near half area (C1, C2) of the upper edge of the second wafer and the third wafer ranges from 1.1V to 2.4V, and is higher than the standard voltage value (0.8+/-0.2V); the V2 value of the near small half areas (D1, D2) near the lower edge of the fourteenth wafer and the fifteenth wafer ranges from 1.3V to 2.3V, and is higher than the standard voltage value (0.8+/-0.2V); the V2 value ranges of the whole areas of the sixth wafer, the seventh wafer, the tenth wafer and the eleventh wafer are all within the standard voltage value range (0.8±0.2V), and it can be proved that the uniformity of the annealing effect of the wafers in the middle area is better. This example demonstrates that all positional data can be more efficiently obtained and monitored for analysis, thereby improving annealing uniformity by improving annealing conditions and the like.
Comparative example 1
The specific steps of the method for monitoring the annealing uniformity of the chip in this comparative example 1 are substantially the same as those of the method for monitoring the annealing uniformity of the chip in example 1 of the present invention, except that:
s40, forming a first N-type electrode 231 on the first ohmic contact layer 211 corresponding to the first, second and third mark points in each wafer 100, and forming a second N-type electrode 232 on the second ohmic contact layer 212 corresponding to the first, second and third mark points in each wafer 100; meanwhile, a first P-type electrode 233 is formed on the third ohmic contact layer 221 corresponding to the first, second and third mark points in each wafer 100, and a second P-type electrode 234 is formed on the fourth ohmic contact layer 222 corresponding to the first, second and third mark points in each wafer 100, and the electrode assembly 23 is a multi-layered composite metal material including aluminum.
S50, in the chip structure 200 corresponding to the first mark point (point m1 in fig. 4), the second mark point (point m2 in fig. 4) and the third mark point (point m3 in fig. 4) in each wafer 100, the voltage values of 48 mark points in total of the 16 sets of wafers are compared with the standard voltage values (0.8±0.2V) to monitor the annealing uniformity of each wafer 100 in different areas, as shown in the following table 1:
TABLE 1
Specifically, as can be seen from table 1, the V2 value of the first mark point in the first wafer is 1.484V, which is higher than the standard voltage value (0.8±0.2V); the V2 value of the third mark point in the fourth wafer is 1.621V, which is higher than the standard voltage value (0.8+/-0.2V); the V2 value of the first mark point in the fifth wafer is 1.481V, the V2 value of the second mark point is 1.452V, and the V2 value is higher than the standard voltage value (0.8+/-0.2V); the V2 value of the third mark point in the eighth wafer is 1.383V, which is higher than the standard voltage value (0.8+/-0.2V); the V2 value of the first mark point in the ninth wafer is 1.611V, the V2 value of the second mark point is 1.147V, and the V2 value is higher than the standard voltage value (0.8+/-0.2V); the V2 value of the second mark point in the twelfth wafer is 1.172V, the V2 value of the third mark point is 1.617V, and the standard voltage value (0.8+/-0.2V) is higher than the standard voltage value; the V2 value of the first mark point in the thirteenth wafer is 1.776V, which is higher than the standard voltage value (0.8+/-0.2V); the V2 value of the third mark point in the sixteenth wafer is 1.562V, which is higher than the standard voltage value (0.8±0.2V).
In summary, it can be seen from table 1 that the voltages at the edge positions of the plurality of wafers 100 on the left and right sides are higher during annealing, but the data only include three 16 groups of points, 48 data points, and the variations of all annealing positions cannot be accurately analyzed, so that all position data cannot be effectively obtained, and the annealing uniformity of the data cannot be monitored and analyzed. In this embodiment 1, voltage data between the first N-type electrode 231 and the second N-type electrode 232 is obtained by an MPI tester (high-low temperature 8 inch semiautomatic high-pressure bench) and recorded as V2 (as shown in fig. 3 and 4, all position data on the 16 sets of wafers 100 are tested on each wafer 100), and analyzed by an image distribution software, and then the obtained V2 voltage data (fig. 4) can be more effectively obtained at all positions than comparative example 1, so that different annealing conditions of different regions can be clearly seen to perform monitoring analysis, thereby improving annealing uniformity by improving annealing conditions and the like.
In summary, the method for monitoring the annealing uniformity of the chip provided by the invention has the following advantages:
the method for monitoring the annealing uniformity of the chip can effectively monitor the thermal annealing states of the wafers 100 at different positions under different processes, and monitor the whole area of the wafers 100 instead of local areas;
the method for monitoring the annealing uniformity of the chip can simply, conveniently and quickly judge whether the annealing process is normal or not;
the method for monitoring the annealing uniformity of the chip can monitor the voltage change caused by different materials, structures, electrodes and the like, and reduce the risk of electronic failure caused by such factors;
the method for monitoring the annealing uniformity of the chip can be used for monitoring the wafer 100 for reuse, and reduces the process cost.
In summary, unlike the prior art, the invention provides a method for monitoring the annealing uniformity of a chip, which comprises the following steps: firstly, providing a plurality of wafers 100, forming a plurality of epitaxial light emitting layers 20 on each wafer 100, secondly, forming an N-type contact element 21 on each epitaxial light emitting layer 20 corresponding to each wafer 100, annealing the N-type contact element 21, thirdly, forming a P-type contact element 22 on each epitaxial light emitting layer 20 in each wafer 100, annealing the P-type contact element 22, thirdly, forming an electrode assembly 23 on each epitaxial light emitting layer 20 in each wafer 100to obtain a plurality of chip structures 200, and finally, detecting voltages on the areas of each chip structure 200 corresponding to the electrode assemblies 23 in the wafers 100, and monitoring annealing uniformity of each wafer 100 in different areas according to detection results; according to the method, after each chip structure 200 in the wafers 100 is annealed twice, the voltage detection is performed on the area of each chip structure 200 corresponding to the electrode assembly 23 in the wafers 100, and compared with the existing monitoring method for the annealing uniformity of the chips, the method only performs voltage detection on three points in each wafer 100, and the method can monitor the annealing effect of each wafer 100 in the whole area more effectively, so that the production yield of the chip structures 200 can be improved effectively.
It should be noted that, the foregoing embodiments all belong to the same inventive concept, and the descriptions of the embodiments have emphasis, and where the descriptions of the individual embodiments are not exhaustive, reference may be made to the descriptions of the other embodiments.
The foregoing examples merely illustrate embodiments of the invention and are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method for monitoring annealing uniformity of a chip, the method comprising:
s10, providing a plurality of wafers, and forming a plurality of epitaxial light-emitting layers on each wafer;
s20, forming an N-type contact assembly on each epitaxial light-emitting layer corresponding to each wafer, and annealing the N-type contact assemblies;
s30, forming a P-type contact assembly on each epitaxial light-emitting layer in each wafer, and annealing the P-type contact assemblies;
s40, forming an electrode assembly on each epitaxial light-emitting layer in each wafer to obtain a plurality of chip structures;
and S50, detecting the voltage of the area of each chip structure corresponding to the electrode assembly in the wafer, and monitoring the annealing uniformity of each wafer in different areas according to the detection result.
2. The method according to claim 1, wherein in the step S10, the epitaxial light emitting layer includes an N-type semiconductor layer, a quantum well active layer, and a P-type semiconductor layer, which are sequentially stacked, the N-type semiconductor layer has a step structure, and an area of the N-type semiconductor layer is larger than an area of the quantum well active layer.
3. The method for monitoring the annealing uniformity of a chip according to claim 2, wherein the step S20 specifically comprises:
s201, forming an N-type contact assembly at a step-shaped structure of each corresponding N-type semiconductor layer in each wafer, wherein the N-type contact assembly comprises a first ohmic contact layer and a second ohmic contact layer which are arranged at intervals;
and S202, respectively carrying out the annealing treatment on the first ohmic contact layer and the second ohmic contact layer.
4. The method for monitoring annealing uniformity of a chip according to claim 3, wherein in said annealing treatment step of S202, the annealing temperature is 900 ℃, the annealing time is 75 seconds, and the annealing atmosphere is N 2 And atmosphere, wherein the gas inlet flow rate of the annealing atmosphere is 9sccm.
5. The method for monitoring annealing uniformity of a chip according to claim 3, wherein said step S30 specifically comprises:
s301, forming a P-type contact assembly on each corresponding P-type semiconductor layer in each wafer, wherein the P-type contact assembly comprises a third ohmic contact layer and a fourth ohmic contact layer which are arranged at intervals;
and S302, respectively carrying out the annealing treatment on the third ohmic contact layer and the fourth ohmic contact layer.
6. The method for monitoring annealing uniformity of a chip according to claim 5, whereinIn the annealing treatment step of S302, the annealing temperature is 600 ℃, the annealing time is 180S, and the annealing atmosphere is N 2 With O 2 In the annealing atmosphere, N in the annealing atmosphere 2 Is 5sccm, O in the annealing atmosphere 2 The gas inlet flow rate of (2) was 1sccm.
7. The method for monitoring annealing uniformity of a chip according to claim 5, wherein said step S40 specifically comprises:
s401, forming a first N-type electrode on the first ohmic contact layer and forming a second N-type electrode on the second ohmic contact layer;
s402, forming a first P-type electrode on the third ohmic contact layer, and forming a second P-type electrode on the fourth ohmic contact layer.
8. The method for monitoring annealing uniformity of a chip according to claim 7, wherein said step S50 specifically comprises:
s501, in each chip structure of each wafer, the voltage between the first P-type electrode and the second P-type electrode is recorded as V1, and the V1 is compared with a standard voltage value to monitor the annealing uniformity of each wafer in different areas.
9. The method for monitoring annealing uniformity of a chip according to claim 7, wherein said step S50 specifically comprises:
s501, in each chip structure of each wafer, the voltage between the first N-type electrode and the second N-type electrode is recorded as V2, and the V2 is compared with a standard voltage value to monitor the annealing uniformity of each wafer in different areas.
10. The method for monitoring annealing uniformity of a chip according to claim 7, wherein said step S50 specifically comprises:
s501, in each chip structure of each wafer, recording any one of the voltage between the first N-type electrode and the first P-type electrode and the voltage between the second N-type electrode and the second P-type electrode as V3, and comparing the V3 with a standard voltage value to monitor the annealing uniformity of each wafer in different areas.
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