CN116994628B - Flash memory particle grading method, controller and medium based on offset read voltage - Google Patents
Flash memory particle grading method, controller and medium based on offset read voltage Download PDFInfo
- Publication number
- CN116994628B CN116994628B CN202310801744.2A CN202310801744A CN116994628B CN 116994628 B CN116994628 B CN 116994628B CN 202310801744 A CN202310801744 A CN 202310801744A CN 116994628 B CN116994628 B CN 116994628B
- Authority
- CN
- China
- Prior art keywords
- type
- blocks
- read voltage
- flash memory
- page
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002245 particle Substances 0.000 title claims abstract description 144
- 238000000034 method Methods 0.000 title claims abstract description 66
- 238000012360 testing method Methods 0.000 claims abstract description 88
- 230000002950 deficient Effects 0.000 claims abstract description 39
- 239000008187 granular material Substances 0.000 claims description 18
- 238000004590 computer program Methods 0.000 claims description 7
- 230000004044 response Effects 0.000 abstract description 11
- 238000004904 shortening Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000007405 data analysis Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/06—Acceleration testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses a flash memory particle grading method, a controller and a medium based on offset read voltage, wherein the method comprises the steps of obtaining test data of flash memory particles under a plurality of test scenes, obtaining two groups of offset read voltage parameter groups according to the test data, reading the flash memory particles according to the two groups of offset read voltage parameter groups corresponding to the current scene, marking a plurality of blocks as a first type of blocks, a second type of blocks and a third type of blocks according to a reading result, determining the flash memory particles as good products, inferior products or defective products according to the number of the first type of blocks, the second type of blocks and the third type of blocks in the plurality of blocks, further effectively shortening the test time, improving the test efficiency and the response speed of the particles, improving the grading precision, and enabling finally screened flash memory particle products to have better consistency so as to meet the grading requirements of high-performance particles in the current high-response speed application environments such as mobile phones.
Description
Technical Field
The invention relates to the technical field of flash memory particle classification, in particular to a flash memory particle classification method based on offset read voltage, a controller and a medium.
Background
Currently, some manufacturers use flash memory particle grading methods to read data depending on offset read voltage parameters (also called retry parameters) provided by the manufacturers, and grade the data based on the read results, wherein the offset read voltage parameters provided by the manufacturers are obtained through various tests, the parameters are more effective to corresponding particles under specific use conditions, under normal conditions, the manufacturers provide several groups to tens of groups of offset voltage parameters for users to read the flash memory particles, and when one group of all retry parameter groups provided by the original manufacturer can be successfully read, the data in the flash memory particles can be corrected and read;
however, this scheme has the following problems that, assuming that the original manufacturer provides 30 sets of offset read voltage parameters, if two particles exist, one of the two sets of parameters is only needed to correct data, and the other one of the two sets of parameters is needed to correct data, according to the existing scheme, the two sets of parameters are classified into the same class, and since the former particle can directly read according to the parameters, the latter particle needs to try the 29 sets of offset voltage parameters before the former particle can correctly read the data, so that the performance and response speed of the former particle are obviously superior to those of the latter particle, which results in poor consistency of the classification result obtained by the classification scheme, so that the classification result cannot effectively determine to process high-performance particles from a plurality of flash memory particles, and cannot well meet the classification requirements of the high-performance particles, for example, the requirements of a high-response-speed application environment (such as a mobile phone) are required; meanwhile, the latter particle needs to try the previous 29 groups of offset voltage parameters to correctly read the data, which also indicates that the parameters provided by the former factory may not be suitable for all test scenes, wherein invalid parameters which only waste test time exist, so that a great amount of time still can be consumed when the particle is read, and the response speed is influenced.
Disclosure of Invention
The embodiment of the invention provides a flash memory particle grading method, a controller and a computer storage medium based on offset read voltage, which can at least ensure that flash memory particles are graded through two offset read voltage parameter groups, so that the testing time is shortened, the testing efficiency and the response speed of the particles are improved, and the grading requirement of high-performance particles is met through finer grading good products, defective products or defective products of the particles, wherein the good products are particles which meet the high-performance requirement correspondingly.
In a first aspect, an embodiment of the present invention provides a flash memory granule classification method based on offset read voltage, where the method includes:
obtaining test data of flash memory particles in a plurality of test scenes, wherein the test scenes comprise high-temperature writing and high-temperature reading, high-temperature writing and low-temperature reading, low-temperature writing and low-temperature reading and low-temperature writing and high-temperature reading;
obtaining a plurality of first offset read voltage parameter sets and second offset read voltage parameter sets corresponding to the test scene according to the test data;
determining a current scene from a plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particle according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the current scene, and marking the plurality of blocks as a first type block, a second type block and a third type block according to a reading result;
And determining the flash memory particles as good products, defective products or defective products according to the numbers of the first type of blocks, the second type of blocks and the third type of blocks in the plurality of blocks.
In some embodiments, marking the plurality of blocks as a first type of block, a second type of block, and a third type of block based on the read results includes:
marking a plurality of pages as a first type page, a second type page and a third type page according to whether target data are obtained when the plurality of pages in the plurality of blocks are read;
the plurality of blocks are marked as first, second and third type blocks according to the number of the first, second and third type pages in the plurality of blocks.
In some embodiments, the marking the plurality of pages as the first type of page, the second type of page, and the third type of page according to whether the target data is obtained when the plurality of pages in the plurality of blocks are read includes:
under the condition that target data is obtained by reading a target page according to the first offset read voltage parameter set, marking the target page as a first type page;
when the target page is read according to the first offset read voltage parameter set and the target data is not obtained, marking the target page as a second type page;
And marking the target page as a third type page under the condition that target data is not obtained by reading the target page according to the first offset read voltage parameter set and the second offset read voltage parameter set.
In some embodiments, the marking the plurality of blocks as the first type of block, the second type of block, and the third type of block according to the number of the first type of page, the second type of page, and the third type of page in the plurality of blocks includes:
marking the target block as a first type block under the condition that a plurality of pages in the target block are all the first type pages;
marking a target block as a second type block if a plurality of pages in the target block include the second type page and do not include the third type page;
in the case where the plurality of pages in the target block includes the third class of pages, the target block is marked as a third class of blocks.
In some embodiments, determining the flash memory granule as good, bad, or bad according to the number of the first, second, and third types of blocks in the plurality of blocks includes:
under the condition that the plurality of blocks are all the first type of blocks, determining the flash memory particles as good products;
determining the flash memory grain as a defective product in the case that a plurality of blocks include the second type of blocks and do not include the third type of blocks;
And determining the flash memory particles as defective products in the case that the plurality of blocks comprise the third class of blocks.
In some embodiments, in a case that the current scene is high temperature writing and high temperature reading, after marking the plurality of blocks as the first type of blocks, the second type of blocks and the third type of blocks according to the reading result, the method further includes:
controlling the current scene temperature under the condition that the flash memory particles do not comprise the third type of blocks, so as to sequentially switch the current scene into high-temperature writing low-temperature reading, low-temperature writing low-temperature reading and low-temperature writing high-temperature reading;
reading a plurality of pages in the first type blocks and the second type blocks of the flash memory particles according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the switched current scene, and marking the first type blocks and the second type blocks as first type blocks, second type blocks and third type blocks according to a reading result;
after the high-temperature writing and high-temperature reading, the high-temperature writing and low-temperature reading, the low-temperature writing and low-temperature reading and the low-temperature writing and high-temperature reading are all performed, determining the flash memory particles as good products, defective products or defective products according to the number of the first type of blocks, the second type of blocks and the third type of blocks in the plurality of blocks.
In some embodiments, the first offset read voltage parameter set includes one offset read voltage parameter, the second offset read voltage parameter set includes two offset read voltage parameters, the offset read voltage parameters are used to determine a read voltage when the flash memory particle is read, and the first offset read voltage parameter set and the second offset read voltage parameter set are both used to determine that the flash memory particle is read under a corresponding test scenario to obtain target data.
In some embodiments, the flash memory particle is a TLC particle, the types of pages of the TLC particle include LSB page, CSB page, and MSB page, and obtaining a plurality of first offset read voltage parameter sets and second offset read voltage parameter sets corresponding to the test scenario according to the test data, including:
and obtaining a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to a plurality of types of pages in a plurality of test scenes according to the test data, so that after determining a current scene from the plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particles according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the types of the plurality of pages in the current scene.
In a second aspect, an embodiment of the present invention provides a controller, including a memory, a processor, and a computer program stored on the memory and capable of running on the processor, where the processor implements the flash memory particle classification method based on offset read voltage according to any one of the embodiments of the first aspect when the processor executes the computer program.
In a third aspect, an embodiment of the present invention provides a computer readable storage medium storing computer executable instructions for performing the flash memory grain classification method based on offset read voltage according to any one of the embodiments of the first aspect.
The invention has at least the following beneficial effects: the invention provides a flash memory particle grading method based on offset reading voltage, which comprises the steps of obtaining test data of flash memory particles under a plurality of test scenes, wherein the test scenes comprise high-temperature writing and high-temperature reading, high-temperature writing and low-temperature reading, low-temperature writing and low-temperature reading and low-temperature writing and high-temperature reading; obtaining a plurality of first offset read voltage parameter sets and second offset read voltage parameter sets corresponding to the test scene according to the test data; determining a current scene from a plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particle according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the current scene, and marking the plurality of blocks as a first type block, a second type block and a third type block according to a reading result; according to the quantity of the first type blocks, the second type blocks and the third type blocks in the blocks, the flash memory particles are determined to be good products, defective products or defective products, wherein the flash memory particles are classified by analyzing test data to obtain two most effective offset read voltage parameter sets, and the test time is effectively shortened, the test efficiency and the response speed of the particles are improved, and the classification precision is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
FIG. 1 is a flow chart of flash memory grain classification based on offset read voltage according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a read voltage according to another embodiment of the present invention;
FIG. 3 is a flowchart of marking a plurality of blocks as a first type of block, a second type of block, and a third type of block according to a read result according to another embodiment of the present invention;
FIG. 4 is a flow chart for marking a plurality of pages as a first type of page, a second type of page, and a third type of page according to another embodiment of the present invention;
FIG. 5 is a flow chart of marking a plurality of blocks as a first type of block, a second type of block, and a third type of block according to another embodiment of the present invention;
FIG. 6 is a flow chart of determining flash memory particles as good, bad or bad according to another embodiment of the present invention;
FIG. 7 is a flow chart of performing high temperature writing/low temperature reading, low temperature writing/low temperature reading or low temperature writing/high temperature reading according to another embodiment of the present invention;
FIG. 8 is a flowchart of another embodiment of the present invention;
FIG. 9 is a flowchart of another embodiment of the present invention;
fig. 10 is a schematic diagram of a controller according to another embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In some embodiments, although functional block division is performed in a system diagram, logical order is shown in a flowchart, in some cases, steps shown or described may be performed in a different order than block division in a system, or in a flowchart. The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
Furthermore, unless explicitly specified and limited otherwise, the term "coupled/connected" is to be interpreted broadly, as for example, being either fixedly coupled or movably coupled, being either detachably coupled or not detachably coupled, or being integrally coupled; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium.
In the description of the embodiments of the present invention, the descriptions of the terms "one embodiment/implementation," "another embodiment/implementation," or "certain embodiments/implementations," "the above embodiments/implementations," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or examples is included in at least two embodiments or implementations of the present disclosure. In the present disclosure, schematic representations of the above terms do not necessarily refer to the same illustrative embodiment or implementation. It should be noted that although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different from that in the flowchart.
At present, some manufacturers use flash memory particle grading methods to read data by relying on offset read voltage parameters (also called retry parameters) provided by the manufacturers, and grade based on the read results, the offset read voltage parameters provided by the manufacturers are obtained through various tests, the parameters are more effective for corresponding particles under specific use conditions, the manufacturers normally provide several groups to tens of groups of offset voltage parameters for users to read the flash memory particles, when one group of all retry parameters provided by the original manufacturer can be successfully read, the problem that the data in the flash memory particles can be corrected and read is relatively high is solved, however, the scheme has the following problems that the original manufacturer provides 30 groups of offset read voltage parameters, if two particles exist, one particle only needs one group of parameters to correct the data, and the other particle needs to use 30 groups of parameters to correct the data, according to the existing scheme, the former particle can be directly read according to the parameters, the latter particle needs the previous 29 groups of offset voltage parameters to read the data, so that the data in the flash memory particles can be corrected, the performance of the former particle and the last particle can not respond to the correct data, for example, the high performance of the grading method can not respond to the requirements of the high performance of the mobile phone, and the high performance of the grading method can not respond to the requirements of the high-grade of the particles, if the grading requirements are met, the requirements are met, and the requirements of the grading requirements are high, and the performance of the grading is poor is better can not be better; meanwhile, the latter particle needs to try the previous 29 groups of offset voltage parameters to correctly read the data, which also indicates that the parameters provided by the former factory may not be suitable for all test scenes, wherein invalid parameters which only waste test time exist, so that a great amount of time still can be consumed when the particle is read, and the response speed is influenced.
In order to solve at least the above problems, the present invention provides a flash memory granule grading method based on offset read voltage, by acquiring test data of flash memory granules under a plurality of test scenarios, wherein the test scenarios include high temperature writing and high temperature reading, high temperature writing and low temperature reading, low temperature writing and low temperature reading and low temperature writing and high temperature reading; obtaining a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to a plurality of test scenes according to the test data; determining a current scene from a plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particle according to a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to the current scene, and marking the plurality of blocks as a first type block, a second type block and a third type block according to a reading result; according to the method, the flash memory particles are determined to be good, inferior or defective according to the number of first, second and third blocks in the blocks, wherein the flash memory particles are classified by the two most effective offset read voltage parameter groups obtained by analyzing test data, and the original parameters of about tens of groups are reduced into the two groups of parameters, so that the test time is effectively shortened, the test efficiency and the response speed of the particles are improved, and the classification precision is improved.
In some embodiments, flash memory is a non-volatile memory technology that can retain data when powered down, and flash memory particles (otherwise referred to as flash chips, flash cells) in the present application are the most basic components that make up flash memory devices, including but not limited to NAND flash memory and NOR flash memory.
In some embodiments, the classification method refers to a method for classifying and controlling quality of products according to characteristics such as performance and quality in the manufacturing process of the products, and the classification method can effectively improve classification precision, thereby helping to ensure that the products reach expected performance standards and improve customer satisfaction.
Embodiments of the present invention are further described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a flowchart of a flash memory granule grading method based on offset read voltage according to an embodiment of the present invention; in some embodiments, a flash memory grain classification method based on offset read voltage at least comprises the following steps:
step S110, test data of flash memory particles under a plurality of test scenes are obtained, wherein the test scenes comprise high-temperature writing and high-temperature reading, high-temperature writing and low-temperature reading, low-temperature writing and low-temperature reading and low-temperature writing and high-temperature reading;
in some embodiments, to cover as many usage scenarios as possible for a user, the test scenario covers four main scenarios, high temperature write high temperature read (HH), high temperature write low temperature read (HL), low temperature write low temperature read (LL), and low temperature write high temperature read (LH), respectively, such comprehensive coverage can ensure performance of the particle in various environments.
Step S120, obtaining a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to a plurality of test scenes according to the test data;
in some embodiments, a series of data analysis operations are required before a particular grading scheme is determined, including collecting and analyzing a large amount of data from various test scenarios, parametric testing includes testing according to parameters provided by the factory, finding the most efficient offset voltage parameters for different page types (LSB, CSB, MSB), and parametric screening the offset voltage parameters, by which two most efficient sets of parameters (a first offset read voltage parameter set and a second offset read voltage parameter set) are screened from the original about tens of parameters, which correspond to good performance of the product, and thereby ensuring consistency of the product to meet the needs of the user.
Step S130, determining a current scene from a plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particle according to a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to the current scene, and marking the plurality of blocks as a first type block, a second type block and a third type block according to a reading result;
In some embodiments, the current scene is switched one by one among high-temperature writing and high-temperature reading, high-temperature writing and low-temperature reading, low-temperature writing and low-temperature reading and low-temperature writing and high-temperature reading until the blocks in the flash memory particles are marked in the four scenes of high-temperature writing and high-temperature reading, high-temperature writing and low-temperature reading, so that the finally screened particles with high performance and high response can adapt to comprehensive testing scenes, and under default, the first scene for reading a plurality of pages in a plurality of blocks of the flash memory particles is the high-temperature writing and high-temperature reading.
And step S140, determining the flash memory particles as good products, defective products or defective products according to the number of the first type of blocks, the second type of blocks and the third type of blocks in the plurality of blocks.
In some embodiments, the structure of the flash memory granule is hierarchical, as follows: a flash memory granule may contain one or more chips (chips); each chip contains a plurality of blocks; each block contains multiple pages (pages).
Referring to fig. 2, fig. 2 is a schematic diagram of a read voltage according to another embodiment of the present invention; in some embodiments, the first offset read voltage parameter set includes an offset read voltage parameter, the second offset read voltage parameter set includes two offset read voltage parameters, the offset read voltage parameters are used to determine the read voltage when reading the flash memory particles, the first offset read voltage parameter set and the second offset read voltage parameter set are both used to determine that reading the flash memory particles obtains the target data in the corresponding test scenario, the offset read voltage parameters are used to set different read voltages when reading the flash memory particles, and setting different read voltages actually changes different threshold voltages, as shown in fig. 2, if the peak a is offset to the right of the line between the ABs, the original voltage is used to read (the voltage of the line position) again, an error occurs, so the read voltage parameters also need to be offset to the right according to the offset read voltage parameters to distinguish the two peaks; specifically, in general, the read voltage is easily biased leftward at high temperature, and the read voltage is easily biased rightward at low Wen Wenshi.
In some embodiments, different read voltages (threshold voltages) may be used to distinguish between different page types, specifically, as shown in fig. 2, the page types include lsb\csb\msb, typically the threshold voltages a and E in fig. 2 are used to distinguish LSB, between threshold voltages a and E, the lower bit is 0, and the other lower bit is 1; similarly, in fig. 2, the threshold voltage B, D, F is used to distinguish CSB, the threshold voltages C and G are used to distinguish MSB, for example 123,3 is the lower bit, 1 is the upper bit, and the arrangement of the peaks can be known by these threshold voltages.
In some embodiments, the flash memory particles are TLC particles, the types of pages of the TLC particles include LSB page, CSB page, and MSB page, and the obtaining the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the plurality of test scenarios according to the test data includes: and obtaining a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to a plurality of types of pages in a plurality of test scenes according to the test data, so that after determining a current scene from the plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particles according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the types of the plurality of pages in the current scene.
In some embodiments, the specific process of obtaining the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the multiple test scenarios according to the test data is as follows, after obtaining the test data, performing data analysis by using Python, for each page type (lsb\csb\msb) of the test data, finding the most effective offset voltage parameter for the page type, and so on, finding a set of parameters (the first offset read voltage parameter set) that can be read for the page type and two sets of parameters (the second offset read voltage parameter set) that need to be used cooperatively to read for the page type, specifically, referring to fig. 2, a and E are parameters effective for LSB; B. d, F is a parameter valid for CSB; C. g is a parameter effective for MSB, and two groups of parameters are screened out through a test, wherein the performance of the block of the flash memory particle which can be read through the first offset read voltage parameter group is better than the performance of the block of the flash memory particle which can be read through the second offset read voltage parameter group, and the performance of the block of the flash memory particle which cannot be read by the first offset read voltage parameter group and the second offset read voltage parameter group is better than the performance of the block of the flash memory particle which cannot be read by the first offset read voltage parameter group and the second offset read voltage parameter group, so that a plurality of blocks can be marked as a first type block, a second type block and a third type block through the rule, and the flash memory particle can be determined as a good product, a defective product or a defective product according to the number of the first type block, the second type block and the third type block in the plurality of blocks, and the good product is the particle meeting the high performance requirement in the current high response speed application environment such as a mobile phone.
In some embodiments, compared with a two-stage classification scheme in the prior art, which only divides products into good products and defective products, the classification scheme for dividing products into good products, defective products and defective products has higher classification precision, so that the finally screened flash memory particle products have better consistency, and the classification requirement of the current high-response-speed application environment such as a mobile phone and the like on high-performance particles is met; and because the invention only uses two groups of offset read voltage parameter groups, compared with the scheme using tens of groups of parameters in the existing scheme, the invention can effectively shorten the test time and improve the test efficiency and the response speed of particles.
Referring to fig. 3, fig. 3 is a flowchart of marking a plurality of blocks as a first type of block, a second type of block and a third type of block according to a read result, and in some embodiments, marking a plurality of blocks as a first type of block, a second type of block and a third type of block according to a read result, at least includes the following steps:
step S310, marking a plurality of pages as a first type page, a second type page and a third type page according to whether target data is obtained when the plurality of pages in a plurality of blocks are read;
in step S320, the plurality of blocks are marked as a first type block, a second type block and a third type block according to the number of the first type page, the second type page and the third type page in the plurality of blocks.
In some embodiments, the present invention reads a plurality of pages in a plurality of blocks by using high-temperature writing and high-temperature reading of two sets of parameters, if the number of error bits of the current page is lower than the maximum number of error bits allowed by the error correction capability, correct target data can be obtained, which indicates that the read data is successful, whereas if the number of error bits of the current page is higher than the maximum number of error bits allowed by the error correction capability, correct target data cannot be obtained, which indicates that the read data is failed, wherein the performance of the page successfully read by the first offset read voltage parameter set is better than the performance of the page successfully read by the second offset read voltage parameter set, and the performance of the page not successfully read by the first offset read voltage parameter set and the second offset read voltage parameter set is better than the performance of the page not successfully read by the first offset read voltage parameter set, and the third type of pages can be further marked as the first type of page, the second type of page and the third type of page, so that the plurality of blocks are marked as the first type of blocks, the second type of blocks and the third type of blocks in the following steps.
FIG. 4 is a flowchart of marking a plurality of pages as a first type page, a second type page and a third type page according to whether target data is obtained when reading the plurality of pages in a plurality of blocks, and the method at least includes the following steps:
Step S410, in the case that the target page is read according to the first offset read voltage parameter set to obtain target data, marking the target page as a first type page;
step S420, marking the target page as a second type page under the condition that the target page is read according to the first offset read voltage parameter set and the target data is not obtained, and the target page is read according to the second offset read voltage parameter set;
in step S430, in the case that the target page is read according to both the first offset read voltage parameter set and the second offset read voltage parameter set without obtaining the target data, the target page is marked as a third type page.
In some embodiments, traversing a plurality of pages in a plurality of blocks, sequentially determining a page to be read currently as a target page, determining a block in which the target page is located as a target block, and performing subsequent operations so that the plurality of pages in the plurality of blocks are marked as a first type page, a second type page and a third type page, so that the flash memory particles are marked as a first type block, a second type block and a third type block for each block in total.
In some embodiments, the classification of the first type of page, the second type of page and the third type of page is to divide the performance of the pages, and since the target page is marked as the first type of page when the target page is read according to the first offset read voltage parameter set to obtain the target data, the reading process of the first type of page has no redundant step of testing according to the invalid parameter, so the read efficiency is the fastest and the performance is the best; under the condition that the target page is read according to the first offset read voltage parameter set and the target data is not obtained, and the target page is read according to the second offset read voltage parameter set, marking the target page as a second type page, wherein the second type page is read only through two tests (the first offset read voltage parameter set and the second offset read voltage parameter set), so that the read efficiency is inferior to that of the first type page, and the performance is suboptimal; under the condition that target data are not obtained by reading target pages according to the first offset read voltage parameter set and the second offset read voltage parameter set, the target pages are marked as third class pages, and the third class pages fail to read according to the current parameter set, so that the performance is worst.
FIG. 5 is a flowchart of marking a plurality of blocks as a first type of block, a second type of block and a third type of block according to another embodiment of the present invention, wherein the marking the plurality of blocks as the first type of block, the second type of block and the third type of block according to the number of pages of the first type, pages of the second type and pages of the third type in the plurality of blocks includes at least the following steps:
step S510, marking the target block as a first type block under the condition that a plurality of pages in the target block are all pages of the first type;
step S520, in the case that the plurality of pages in the target block include the second type page and do not include the third type page, marking the target block as the second type block;
in step S530, in the case that the plurality of pages in the target block include the third type of pages, the target block is marked as the third type of block.
In some embodiments, since the performance of the first type of page, the second type of page, and the third type of page is sequentially weakened, the target block may be marked as a first type of block in a case where the plurality of pages in the target block are all the first type of page, the target block may be marked as a second type of block in a case where the plurality of pages in the target block include the second type of page and the third type of page is not included, the target block may be marked as a third type of block in a case where the plurality of pages in the target block include the third type of page, the performance of the first type of block, the second type of block, and the third type of block may be gradually weakened, and the flash memory particles may be determined as good, bad, or defective in a subsequent step according to the number of the first type of block, the second type of block, and the third type of block in the plurality of blocks.
Fig. 6 is a flowchart of determining flash memory particles as good, bad or bad according to another embodiment of the present invention, wherein the determining flash memory particles as good, bad or bad according to the number of the first, second and third blocks in the plurality of blocks at least includes the following steps:
step S610, determining the flash memory particles as good products under the condition that the blocks are all the first type blocks;
step S620, determining the flash memory particles as inferior products in the case that the plurality of blocks comprise the second type of blocks and do not comprise the third type of blocks;
in step S630, in the case that the plurality of blocks includes the third class block, the flash particles are determined as defective products.
In some embodiments, when testing of all scenes is finally completed, the number of the first type blocks, the second type blocks and the third type blocks can reflect the performance of the flash memory particles, so that the flash memory particles are finally determined to be good, bad or defective according to the number relationship, the classification precision is further improved, and finally screened flash memory particle products have better consistency so as to meet the classification requirement of the current high-response-speed application environment such as a mobile phone and the like on the high-performance particles.
Fig. 7 is a specific flowchart of performing high-temperature writing and low-temperature reading, low-temperature writing and low-temperature reading or low-temperature writing and high-temperature reading according to another embodiment of the present invention, where in the case that the current scene is high-temperature writing and high-temperature reading, after marking a plurality of blocks into a first type of block, a second type of block and a third type of block according to the reading result, at least the following steps are further included:
Step S710, controlling the current scene temperature to sequentially switch the current scene to high-temperature writing low-temperature reading, low-temperature writing low-temperature reading and low-temperature writing high-temperature reading under the condition that the flash memory particles do not comprise the third type of blocks;
step S720, a plurality of pages in a first type block and a second type block of the flash memory particle are read according to a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to the switched current scene, and the first type block and the second type block are marked as a first type block, a second type block and a third type block according to a read result;
step S730, after the high temperature writing and high temperature reading, the high temperature writing and low temperature reading, the low temperature writing and low temperature reading, and the low temperature writing and high temperature reading are all performed, determining the flash memory particles as good products, inferior products or defective products according to the numbers of the first type of blocks, the second type of blocks and the third type of blocks in the plurality of blocks.
It is conceivable that in the case where the flash memory particle includes the third type of block, it is indicated that the flash memory particle is defective, so that it is not necessary to perform detection marking in the subsequent step, thereby saving time consumed for classification and improving classification efficiency.
In some embodiments, it is conceivable that, in order to cover the usage scenario of the user as much as possible as the grading result, after the marking process of writing at high temperature and reading at high temperature, the marking processes of writing at high temperature and reading at low temperature, writing at low temperature and reading at low temperature are sequentially performed, so that the grading result obtained finally has higher precision under different usage environments.
FIG. 8 is a flowchart showing a specific process of performing high temperature writing and high temperature reading according to another embodiment of the present invention, wherein two sets of parameters HH are used, in a current page, if a first set of parameters (a first set of offset read voltage parameters) can be used to read pair data, the block may be marked as 1 (a first type of block), if a part of the page needs to use two sets of parameters (a second set of offset read voltage parameters) to read pair data in addition to one set of parameter reading, the block is marked as 2 (a second type of block), if two sets of blocks incapable of reading pair data exist, the block is marked as 3 (a third type of block), all blocks of the whole particle are all marked as 1, 2 or 3, so far as to complete the test of HH, if all blocks marked as 1 are good, if there is a block marked as 1, and if there is a block marked as 2, the particle is classified as a defective. The block grain with the presence of the mark 3 is classified as defective.
Fig. 9 is another specific flowchart provided in another embodiment of the present invention, after high temperature writing and high temperature reading, the specific processes of high temperature writing and low temperature reading, low temperature writing and low temperature reading and low temperature writing and high temperature reading are as follows, the temperature is reduced to low temperature changing museum, HL test is performed, the result of the previous round of writing in the granule is first read, if the previous round of testing block is marked as 3 (third type block), the round of testing is not needed, only the granules marked as 1 (second type block) and 2 (third type block) are needed to be tested, so as to improve the classification efficiency, the testing process at the later stage is consistent, it is noted that when the defective products are judged at the later stage, the ignored block does not participate in judgment, and when all tests are finally completed, if all scenes are marked as 1, the granule is the defective products if the block marked as 2 is present, the defective products are classified as secondary products if the block marked as 3 is present, and if the block marked as 3 is present, the granule is marked as defective products are classified as defective products, so that the classification result is covered as possible by users.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a controller according to an embodiment of the present invention.
Some embodiments of the present invention provide a controller including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the flash memory particle classification method based on offset read voltage of any of the above embodiments when executing the computer program, for example, performing the method steps S110 to S140 in fig. 1, the method steps S310 to S320 in fig. 3, the method steps S410 to S430 in fig. 4, the method steps S510 to S530 in fig. 5, the method steps S610 to S630 in fig. 6, and the method steps S710 to S730 in fig. 7 described above.
The controller 1000 of the present embodiment includes one or more processors 1010 and a memory 1020, one processor 1010 and one memory 1020 being illustrated in fig. 10.
The processor 1010 and the memory 1020 may be connected by a bus or otherwise, for example in fig. 10.
Memory 1020 is a non-transitory computer readable storage medium that may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, memory 1020 may include high-speed random access memory and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 1020 optionally includes memory 1020 located remotely from processor 1010, which may be connected to controller 1000 via a network, examples of which include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
In some embodiments, the processor executes the computer program to perform the flash memory particle classification method based on offset read voltage according to any one of the above embodiments at preset intervals.
Those skilled in the art will appreciate that the device structure shown in fig. 10 is not limiting of the controller 1000 and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
In the controller 1000 shown in fig. 10, the processor 1010 may be configured to invoke the flash memory granule classification method based on the offset read voltage stored in the memory 1020, thereby implementing the flash memory granule classification method based on the offset read voltage.
Based on the hardware structure of the controller 1000, various embodiments of the flash memory granule grading system based on offset read voltage of the present invention are presented, and at the same time, the non-transient software program and instructions required for implementing the flash memory granule grading method based on offset read voltage of the above embodiments are stored in the memory, and when executed by the processor, the flash memory granule grading method based on offset read voltage of the above embodiments is executed.
In addition, the embodiment of the invention also provides a flash memory particle grading system based on offset read voltage, which comprises the controller and comprises: the threshold value determining module is used for obtaining the code word decoding time of the flash memory particles and determining a page decoding time threshold value according to the code word decoding time; the flash memory reading module is used for reading a plurality of pages in a plurality of blocks of the flash memory particles according to a first writing and reading scene and obtaining a plurality of page reading times so as to mark the page corresponding to the page reading time as a bad page under the condition that the page reading time is greater than a page decoding time threshold value; and the flash memory grading module is used for marking the blocks comprising the bad pages in the blocks as bad blocks and determining flash memory particles as good products, defective products or defective products according to the number of the bad blocks.
In some embodiments, since the offset read voltage based flash memory particle classification system of the embodiment of the present invention has the controller of the above embodiment, and the controller of the above embodiment is capable of executing the offset read voltage based flash memory particle classification method of the above embodiment, specific implementation and technical effects of the offset read voltage based flash memory particle classification system of the embodiment of the present invention may refer to specific implementation and technical effects of the offset read voltage based flash memory particle classification method of any of the above embodiments.
The embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions for performing the above-described flash memory particle grading method based on offset read voltage, for example, the above-described one or more processors may be caused to perform the flash memory particle grading method based on offset read voltage in the above-described method embodiment, and perform the above-described method steps S110 to S140 in fig. 1, the method steps S310 to S320 in fig. 3, the method steps S410 to S430 in fig. 4, the method steps S510 to S530 in fig. 5, the method steps S610 to S630 in fig. 6, and the method steps S710 to S730 in fig. 7.
The above described apparatus embodiments are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network nodes. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer readable storage media (or non-transitory media) and communication media (or transitory media). The term computer-readable storage medium includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer-readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.
Claims (8)
1. A flash memory grain classification method based on offset read voltage, the method comprising:
obtaining test data of flash memory particles in a plurality of test scenes, wherein the test scenes comprise high-temperature writing and high-temperature reading, high-temperature writing and low-temperature reading, low-temperature writing and low-temperature reading and low-temperature writing and high-temperature reading;
obtaining a plurality of first offset read voltage parameter sets and second offset read voltage parameter sets corresponding to the test scene according to the test data;
determining a current scene from a plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particle according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the current scene, and marking the plurality of blocks as a first type block, a second type block and a third type block according to a reading result;
determining the flash memory particles as good products, defective products or defective products according to the number of the first type of blocks, the second type of blocks and the third type of blocks in the plurality of blocks;
Wherein the marking the plurality of blocks as the first type of block, the second type of block and the third type of block according to the reading result includes:
marking a plurality of pages as a first type page, a second type page and a third type page according to whether target data are obtained when the plurality of pages in the plurality of blocks are read;
marking the plurality of blocks as a first type block, a second type block and a third type block according to the number of the first type pages, the second type pages and the third type pages in the plurality of blocks;
the marking the plurality of pages as a first type page, a second type page and a third type page according to whether target data is obtained when the plurality of pages in the plurality of blocks are read, comprising:
under the condition that target data is obtained by reading a target page according to the first offset read voltage parameter set, marking the target page as a first type page;
when the target page is read according to the first offset read voltage parameter set and the target data is not obtained, marking the target page as a second type page;
and marking the target page as a third type page under the condition that target data is not obtained by reading the target page according to the first offset read voltage parameter set and the second offset read voltage parameter set.
2. The offset read voltage based flash memory grain classification method of claim 1, wherein the marking the plurality of blocks as the first type of block, the second type of block, and the third type of block according to the number of the first type of page, the second type of page, and the third type of page in the plurality of blocks comprises:
marking the target block as a first type block under the condition that a plurality of pages in the target block are all the first type pages;
marking a target block as a second type block if a plurality of pages in the target block include the second type page and do not include the third type page;
in the case where the plurality of pages in the target block includes the third class of pages, the target block is marked as a third class of blocks.
3. The offset read voltage based flash memory granule classification method according to claim 1, wherein determining the flash memory granule as good, bad or bad according to the number of the first, second and third kinds of blocks among a plurality of blocks comprises:
under the condition that the plurality of blocks are all the first type of blocks, determining the flash memory particles as good products;
determining the flash memory grain as a defective product in the case that a plurality of blocks include the second type of blocks and do not include the third type of blocks;
And determining the flash memory particles as defective products in the case that the plurality of blocks comprise the third class of blocks.
4. The method for grading flash memory particles based on offset read voltage according to claim 1, wherein, in the case that the current scene is high temperature writing and high temperature reading, after marking the plurality of blocks as the first type of blocks, the second type of blocks and the third type of blocks according to the read result, further comprising:
controlling the current scene temperature under the condition that the flash memory particles do not comprise the third type of blocks, so as to sequentially switch the current scene into high-temperature writing low-temperature reading, low-temperature writing low-temperature reading and low-temperature writing high-temperature reading;
reading a plurality of pages in the first type blocks and the second type blocks of the flash memory particles according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the switched current scene, and marking the first type blocks and the second type blocks as first type blocks, second type blocks and third type blocks according to a reading result;
after the high-temperature writing and high-temperature reading, the high-temperature writing and low-temperature reading, the low-temperature writing and low-temperature reading and the low-temperature writing and high-temperature reading are all performed, determining the flash memory particles as good products, defective products or defective products according to the number of the first type of blocks, the second type of blocks and the third type of blocks in the plurality of blocks.
5. The method of claim 1, wherein the first set of offset read voltage parameters includes one offset read voltage parameter, the second set of offset read voltage parameters includes two offset read voltage parameters, the offset read voltage parameters are used to determine a read voltage when the flash memory particles are read, and the first set of offset read voltage parameters and the second set of offset read voltage parameters are used to determine that the flash memory particles are read under corresponding test scenarios to obtain target data.
6. The method for classifying flash memory particles based on offset read voltage according to claim 1, wherein the flash memory particles are TLC particles, the types of pages of the TLC particles include LSB page, CSB page and MSB page, and obtaining a plurality of first offset read voltage parameter sets and second offset read voltage parameter sets corresponding to the test scenario according to the test data comprises:
and obtaining a first offset read voltage parameter set and a second offset read voltage parameter set corresponding to a plurality of types of pages in a plurality of test scenes according to the test data, so that after determining a current scene from the plurality of test scenes, reading a plurality of pages in a plurality of blocks of the flash memory particles according to the first offset read voltage parameter set and the second offset read voltage parameter set corresponding to the types of the plurality of pages in the current scene.
7. A controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the offset read voltage based flash memory particle classification method of any one of claims 1 to 6 when the computer program is executed.
8. A computer readable storage medium storing computer executable instructions for performing the offset read voltage based flash memory grain classification method of any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310801744.2A CN116994628B (en) | 2023-06-30 | 2023-06-30 | Flash memory particle grading method, controller and medium based on offset read voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310801744.2A CN116994628B (en) | 2023-06-30 | 2023-06-30 | Flash memory particle grading method, controller and medium based on offset read voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116994628A CN116994628A (en) | 2023-11-03 |
| CN116994628B true CN116994628B (en) | 2024-04-12 |
Family
ID=88531067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310801744.2A Active CN116994628B (en) | 2023-06-30 | 2023-06-30 | Flash memory particle grading method, controller and medium based on offset read voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116994628B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118351925A (en) * | 2024-04-24 | 2024-07-16 | 深圳三地一芯电子股份有限公司 | Flash memory pre-classification method, device, equipment and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10242734B1 (en) * | 2017-09-29 | 2019-03-26 | Intel Corporation | Resuming storage die programming after power loss |
| CN110148435A (en) * | 2019-04-16 | 2019-08-20 | 珠海妙存科技有限公司 | A kind of flash memory particle screen selecting stage division |
| WO2021035555A1 (en) * | 2019-08-27 | 2021-03-04 | 华为技术有限公司 | Data storage method and apparatus for solid state disk and solid state disk (ssd) |
| CN112506427A (en) * | 2020-11-27 | 2021-03-16 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for reducing power consumption of solid state disk |
| CN114360619A (en) * | 2021-12-31 | 2022-04-15 | 深圳宏芯宇电子股份有限公司 | Test method, test device, terminal and storage medium |
| CN114639436A (en) * | 2022-03-10 | 2022-06-17 | 山东大学 | Flash memory chip data reading method |
| CN115148263A (en) * | 2022-07-05 | 2022-10-04 | 英韧科技(上海)有限公司 | Method for searching common optimal read voltage of multiple particles and storage system |
| CN115705914A (en) * | 2021-08-16 | 2023-02-17 | 深圳市江波龙电子股份有限公司 | Method and device for detecting bad block of flash memory and computer storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8009471B2 (en) * | 2009-12-15 | 2011-08-30 | Seagate Technology Llc | Low-wear writing in a solid state memory device |
-
2023
- 2023-06-30 CN CN202310801744.2A patent/CN116994628B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10242734B1 (en) * | 2017-09-29 | 2019-03-26 | Intel Corporation | Resuming storage die programming after power loss |
| CN110148435A (en) * | 2019-04-16 | 2019-08-20 | 珠海妙存科技有限公司 | A kind of flash memory particle screen selecting stage division |
| WO2021035555A1 (en) * | 2019-08-27 | 2021-03-04 | 华为技术有限公司 | Data storage method and apparatus for solid state disk and solid state disk (ssd) |
| CN112506427A (en) * | 2020-11-27 | 2021-03-16 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for reducing power consumption of solid state disk |
| CN115705914A (en) * | 2021-08-16 | 2023-02-17 | 深圳市江波龙电子股份有限公司 | Method and device for detecting bad block of flash memory and computer storage medium |
| CN114360619A (en) * | 2021-12-31 | 2022-04-15 | 深圳宏芯宇电子股份有限公司 | Test method, test device, terminal and storage medium |
| CN114639436A (en) * | 2022-03-10 | 2022-06-17 | 山东大学 | Flash memory chip data reading method |
| CN115148263A (en) * | 2022-07-05 | 2022-10-04 | 英韧科技(上海)有限公司 | Method for searching common optimal read voltage of multiple particles and storage system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116994628A (en) | 2023-11-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108052414B (en) | Method and system for improving working temperature range of SSD | |
| CN110148435B (en) | Flash memory particle screening and grading method | |
| WO2009050703A2 (en) | Data storage in analog memory cell arrays having erase failures | |
| CN112068772B (en) | Data storage method, data storage device and storage device | |
| CN116994628B (en) | Flash memory particle grading method, controller and medium based on offset read voltage | |
| US10482978B2 (en) | Read voltage optimization method, memory storage device and memory control circuit unit | |
| CN104360957A (en) | Method for maintaining flash memory wear leveling | |
| CN106205731A (en) | Information processing method and storage device | |
| US20100318874A1 (en) | Electronic memory device and method for error correcting thereof | |
| CN116994631B (en) | ECC-based flash memory particle multiple screening method, controller and medium | |
| US10871909B2 (en) | Block management method, memory control circuit unit and apparatus using mapping tables and block recognition machine learning with block parameters as training data | |
| CN116994632B (en) | Flash memory particle grading method, system, controller and medium based on reading time | |
| CN114327258A (en) | Solid state disk processing method, system, equipment and computer storage medium | |
| CN107577440B (en) | Method for prolonging service life of memory | |
| US20100131808A1 (en) | Method For Testing Memory | |
| CN114446379A (en) | Ranking memory devices based on performance metrics for various timing margin parameter settings | |
| CN116884469B (en) | Flash memory performance detection method, device, equipment and medium | |
| US20120159280A1 (en) | Method for controlling nonvolatile memory apparatus | |
| US11875868B2 (en) | Quick reliability scan for memory device | |
| CN110444244A (en) | Store the test device of equipment read error error correcting capability | |
| US11238950B1 (en) | Reliability health prediction by high-stress seasoning of memory devices | |
| CN110364197B (en) | Decoding method and storage controller | |
| CN113625947A (en) | Data error correction method, device and equipment and computer readable storage medium | |
| CN114974387B (en) | Flash memory test method and device based on solid state disk main control chip and solid state disk | |
| CN114360630B (en) | Batch test method and system for SSD (solid State disk) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |