CN116955230A - System on chip and method of operation thereof - Google Patents

Abstract

A system on a chip and a method of operating the same are provided. The system-on-chip includes: a plurality of memory controllers connected to the plurality of memory devices, respectively; a plurality of logic circuits, each logic circuit configured to perform data processing operations using at least one of the plurality of memory controllers; a bus connection interface configured to select a first hash function from a plurality of hash functions based on a first address region corresponding to a first address received from a first logic circuit of the plurality of logic circuits, obtain a hashed first address by applying the first hash function to the first address, and connect at least one of the plurality of memory controllers to the first logic circuit using a first access method corresponding to the hashed first address.

Description

System on chip and method of operation thereof

Cross Reference to Related Applications

The present application claims the benefit of priority from korean patent application No.10-2021-0157091 filed at 11/15/2021 and korean patent application No.10-2022-0026911 filed at 3/2022, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to a system on a chip (SoC), and more particularly, to a SoC including a plurality of Intellectual Property (IPs) and supporting a plurality of IPs to access a plurality of memory devices and a method of operating the same.

Each of the plurality of IPs may include circuitry to perform a particular function and may have a design that includes a trade secret.

Background

With the gradual integration of computers, communications, broadcasting, etc., the demand for Application Specific Integrated Circuit (ASIC) technology and Application Specific Standard Product (ASSP) technology is decreasing, while the demand for SoC technology is increasing. In addition, the increasing demand for lightweight, compact, and high-performance Information Technology (IT) devices is also a factor in the increasing demand for SoC technology.

SoC is a form in which functional blocks (e.g., IP) having various functions are implemented on a single chip according to the development of semiconductor process technology. IP requires access to a plurality of memory devices connected to the SoC to perform data processing operations.

The SoC may support access of the IP to multiple memory devices by using a single hash function, however this does not reflect the data access characteristics of each IP, resulting in unnecessary power consumption and inefficient memory access.

Disclosure of Invention

One or more example embodiments provide a system on a chip (SoC) configured to minimize unnecessary power consumption by supporting access of a plurality of Intellectual Property (IPs) to a plurality of memory devices using a plurality of hash functions and to make memory access efficient, and a method of operating the same.

According to an aspect of an example embodiment, a system on a chip includes: a plurality of memory controllers connected to the plurality of memory devices, respectively; a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to perform data processing operations using at least one of the plurality of memory controllers; and a bus connection interface configured to select a first hash function among the plurality of hash functions based on a first address region received from the plurality of logic circuits corresponding to the first address received by the first logic circuit, obtain a hashed first address by applying the first hash function to the first address, and connect at least one of the plurality of memory controllers to the first logic circuit using a first access method corresponding to the hashed first address.

According to an aspect of an example embodiment, a method of operation of a system on a chip includes: identifying an address area corresponding to an address output from the logic circuit from among the plurality of address areas; selecting a hash function corresponding to the address area from a plurality of hash functions; applying a hash function to the address to obtain a hashed address; and connecting the logic circuit to at least one of the plurality of memory controllers using an access method corresponding to the hashed address.

According to an aspect of an example embodiment, a system on a chip includes: a plurality of memory controllers connected to the plurality of memory devices, respectively; a plurality of bus connection interfaces respectively connected with the plurality of memory controllers; and a first logic circuit configured to select any one of a plurality of first hash functions based on a first address region corresponding to the first address, apply the selected first hash function to the first address to obtain a hashed first address, and connect with at least one of the plurality of bus connection interfaces using a first access method corresponding to the hashed first address.

Drawings

The above and other aspects and features will be more clearly understood from the following description of example embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating a memory system according to an example embodiment;

FIG. 2 is a flowchart illustrating a method of operating a system on a chip (SoC) in accordance with an example embodiment;

FIGS. 3A and 3B are detailed block diagrams of a hash function and port selection circuit according to example embodiments;

FIG. 4 is a detailed block diagram of a memory system according to an example embodiment;

fig. 5A is a flowchart illustrating a method of operating the SoC of fig. 4 according to an example embodiment, and fig. 5B is a diagram illustrating an operation of the SoC of fig. 4 according to fig. 5A according to an example embodiment;

Fig. 6 is a flowchart illustrating a method of operation of the SoC of fig. 4, according to an example embodiment;

fig. 7 is a flowchart illustrating an operation method of the first Intellectual Property (IP) and the second IP of fig. 4 according to an example embodiment;

fig. 8 is a flowchart illustrating a method of operation of a SoC according to an example embodiment;

fig. 9 is a block diagram illustrating a power management method of a SoC according to an example embodiment;

FIG. 10 is a block diagram illustrating a memory system according to an example embodiment;

FIG. 11A is a block diagram illustrating a memory system according to an example embodiment, and FIG. 11B is a block diagram illustrating an arrangement of the memory system of FIG. 11A according to an example embodiment;

fig. 12 and 13 are diagrams illustrating an electronic system according to example embodiments; and

fig. 14 is a block diagram illustrating a SoC according to an example embodiment.

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. When a statement such as "at least one of" follows a list of elements, the statement modifies the entire list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b and c" is understood to include a alone, b alone, c alone, both a and b, both a and c, both b and c, or all of a and b and c.

FIG. 1 is a block diagram illustrating a memory system 10 according to an example embodiment.

Referring to fig. 1, a memory system 10 may include a system on chip (SoC) 100 and first through kth Memory Devices (MDs) 140_1 through 140—k (where k is an integer greater than or equal to 1). In addition, the SoC 100 may include first to nth Intellectual Property (IP) 110_1 to 110—n (where n is an integer greater than or equal to 1), a Bus Connection Unit (BCU) 120 (i.e., a bus or bus connection interface), and first to kth memory controllers 130_1 to 130—k. For example, IP may be a logic circuit including a circuit that performs a specific function, and it may have a design including a trade secret.

In example embodiments, the first to kth MDs 140_1 to 140—k may be implemented as volatile memory devices. For example, the first to kth MDs 140_1 to 140—k may be implemented as any one of a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a double rate synchronous dynamic random access memory (DDR SDRAM), a low power consumption double rate synchronous dynamic random access memory (LPDDR SDRAM), a graphic double rate synchronous dynamic random access memory (GDDR SDRAM), a second generation double rate synchronous dynamic random access memory, a third generation double rate synchronous dynamic random access memory, and a fourth generation double rate synchronous dynamic random access memory. In addition, the first to kth MDs 140_1 to 140—k may also be implemented as nonvolatile memory devices.

In example embodiments, the first through nth IPs 110_1 through 110—n may include any one and any combination of a Central Processing Unit (CPU), a Graphic Processor (GPU), an embedded neural Network Processor (NPU), a Vision Processing Unit (VPU), a Digital Signal Processor (DSP), and an Image Signal Processor (ISP). However, this is merely an example and example embodiments are not limited in this respect. For example, the first through nth IPs 110_1 through 110—n may be functional blocks designed for specific operations of the SoC 100 or functional blocks designed to improve performance of the SoC 100.

The first through nth IPs 110_1 through 110—n may perform data processing operations, and the data processing operations require memory accesses for writing data and reading data. Thus, in example embodiments, the BCU 120 may support the first through nth IPs 110_1 through 110—n to be connected with the first through kth memory controllers 130_1 through 130—k. Further, the first to nth IPs 110_1 to 110—n may perform data processing operations independently of each other, and the BCU 120 may control connections between the first to nth IPs 110_n and the first to kth memory controllers 130_1 to 130—k in parallel or sequentially.

In an example embodiment, the BCU 120 may include first to kth ports P1 to Pk, a hash function and port selection circuit 121, and a plurality of hash functions 122. The first to kth ports P1 to Pk may be connected to the first to kth memory controllers 130_1 to 130_k, respectively. In an example embodiment, the hash function and port selection circuit 121 may be implemented as hardware or software executed by a processing circuit. Further, the plurality of hash functions 122 may be stored in one or more nonvolatile memories included in the SoC 100 and read by the hash function and port selection circuit 121. In some example embodiments, the plurality of hash functions 122 may be pre-designed and stored in non-volatile memory, and the plurality of hash functions 122 may be variable.

The plurality of hash functions 122 may be functions for converting addresses output from the first through nth IPs 110_1 through 110—n into fixed-length data. In an example embodiment, the plurality of hash functions 122 may correspond to a plurality of address regions, respectively. For example, a first hash function may correspond to a first address region and a second hash function may correspond to a second address region. Further, in the example embodiment, a plurality of hash functions 122 may be designed such that access methods respectively corresponding to the plurality of hash functions 122 are different from each other. In some example embodiments, a newly designed hash function may be added to the plurality of hash functions 122, or a part of the plurality of hash functions 122 may be modified according to the states of the first through nth IPs 110_1 through 110—n and the states of the first through kth memory controllers 130_1 through 130—k. In the present disclosure, the access method indicates a method of the first to nth IPs 110_1 to 110—n to access the first to kth MDs 140_1 to 140—k, and may be determined according to the accessed MD among the first to kth MDs 140_k and whether or not the interleaving access method is supported. Further, in the present disclosure, the first to nth IPs 110_1 to 110—n accessing the first to kth MDs 140_1 to 140—k may instruct the first to nth IPs 110_n to access the first to kth memory controllers 130_1 to 130—k.

In the following, to assist in understanding the exemplary embodiments, a case where the first IP 110_1 outputs the first address ADDRl for the data processing operation will be assumed, and it will be understood that a similar data processing operation may be applied to the remaining IPs (i.e., the second IP 110_2 to n-th IP 110_n).

In an example embodiment, the hash function and port selection circuit 121 may receive the first address ADDRl output from the first IP 110_1, and it may determine which address region of the plurality of address regions the first address ADDRl belongs to. In the present disclosure, an address area may indicate a range of values of an address. Some of the plurality of address areas may have the same size. For example, the first address area may be set to values of "1" to "1000", the second address area may be set to values of "1001" to "2000", and in this regard, the first address area and the second address area may have the same size. In some example embodiments, some of the plurality of address regions may have different sizes. For example, the first address area may be set to values of "1" to "1000", the second address area may be set to values of "1001" to "5000", and in this regard, the first address area and the second address area may have different sizes.

The hash function and port selection circuit 121 may select a hash function corresponding to an address region to which the first address ADDRl belongs from the plurality of hash functions 122. The hash function and port selection circuit 121 may apply the selected hash function to the first address ADDR1 to generate a hashed first address, and may select at least one of the first port P1 to the kth port Pk based on the hashed first address. For example, the hash function and port selection circuit 121 may operate according to an interleaving access method, and may alternately select at least two of the first to kth ports P1 to Pk based on the hashed first address. For another example, the hash function and port selection circuit 121 may operate according to a sequential access method, and may sequentially select at least one of the first to kth ports P1 to Pk based on the hashed first address. The hash function and port selection circuit 121 may output the first address ADDR1 to at least one selected port SP. In the present disclosure, the operation of selecting the first to kth ports P1 to Pk may indicate or be referred to as the operation of the first to kth memory controllers 130_1 to 130_k.

In example embodiments, each of the first to kth memory controllers 130_1 to 130_k may control memory operations of the memory devices connected thereto in the first to kth MD 140_1 to 140_k by using any one address of the first to nth IPs 110_1 to 110_n transmitted from the BCU 120. For example, the memory operation may include at least one of a write operation and a read operation, and during the write operation, BCU 120 may further receive data as well as an address. In addition, the BCU 120 may also receive a request for a memory operation from at least one of the first through nth IPs 110_1 through 110—n. According to an example embodiment, BCU 120 may output data and the request to match the output with respect to the address. In an example embodiment, the format of the addresses output from the first to nth IPs 110_1 to 110—n may be the same as the format of the physical addresses of the first to kth MDs 140_1 to 140—k.

In an example embodiment, the first through nth IPs 110_1 through 110—n may be classified into a plurality of IP groups, and each of the plurality of IP groups may include IPs having the same or similar data access characteristics. In the present disclosure, the data access characteristic considers an operation method in the data processing operation of the first to nth IPs 110_1 to 110—n or an operation mode of the first to nth IPs 110_1 to 110—n, and may relate to a required memory capacity, a required data read/write speed, or the like. In an example embodiment, the number of hash functions and the combination of hash functions applicable to each of the plurality of IP groups may be different. For example, the plurality of hash functions 122 may all be applied to a first IP group, and at least one particular hash function of the plurality of hash functions 122 (i.e., less than all of the plurality of hash functions 122) may be applied to a second IP group.

In an example embodiment, the master IP may classify the first through nth IPs 110_1 through 110—n into a plurality of IP groups by mapping at least one of the plurality of hash functions 122 to each of the first through nth IPs 110_1 through 110—n. In some example embodiments, the master IP may generate and manage hash-function mapping information indicating mapping relationships between the first through nth IPs 110_1 through 110—n and the plurality of hash functions 122. In some example embodiments, the master IP may be one of the first through nth IPs 110_1 through 110—n. The master IP may execute an operating system of the SoC 100 and perform a conventional operation for classifying a plurality of address areas and applying a plurality of hash functions 122. In an example embodiment, the primary IP may be implemented as a CPU.

In an example embodiment, the SoC 100 may also include a power management integrated circuit. The power management integrated circuit may perform power management on the first to kth memory controllers 130_1 to 130—k based on the hash-function mapping information. Specific example embodiments thereof are described with reference to fig. 8 and 10

According to example embodiments, the SoC 100 may select an access method suitable for the data processing operation of each of the first through nth IPs 110_1 through 110—n by using a plurality of hash functions 122, and thus, unnecessary power consumption of the SoC 100 may be minimized and performance of the SoC 100 may be improved.

Fig. 2 is a flowchart illustrating a method of operating a SoC according to an example embodiment. Referring to fig. 2, the operation of BCU 120 of the SoC is primarily described, and further reference is made to fig. 1 for better understanding. In the following, an example of outputting the first address ADDR1 (fig. 1) from the first IP 110_1 (fig. 1) will be mainly described. However, the example embodiment is not limited thereto, and the BCU 120 may perform similar operations according to other addresses output from other IPs.

Referring to fig. 1 and 2, in operation S100, the BCU 120 may receive a first address ADDR1 from the first IP 110_1. In operation S110, the BCU 120 may determine an address area to which the first address ADDR1 belongs. Specifically, BCU 120 may search an address area including the value of first address ADDR1. In operation S120, the BCU 120 may select a hash function corresponding to the determined address area from the plurality of hash functions 122. In some example embodiments, when the first address ADDR1 belongs to two or more address regions, the BCU 120 may select two or more hash functions. In operation S130, the BCU 120 may hash the first address ADDR1 based on the selected hash function. In operation S140, the BCU 120 may select at least one port from the first to kth ports P1 to Pk based on the hashed first address ADDR1. In operation S150, the BCU 120 may output the first address ADDR1 to the selected at least one port SP. In some example embodiments, the BCU 120 may output the first address ADDR1 to the selected at least one port SP without performing additional processing. In another example embodiment, the BCU 120 may process the first address ADDR1 according to the selected hash function and then output the processed first address ADDR1 to the selected at least one port SP. A specific description thereof is given with reference to fig. 3B.

Fig. 3A and 3B are detailed block diagrams of a hash function and port selection circuit according to example embodiments.

Referring to fig. 3A, the hash function and port selection circuit 121 may include an address area checker 121_1, a multiplexer 121_2, and a demultiplexer 121_3.

In an example embodiment, the address area checker 121_1 may receive an address ADDR including an "a" bit and determine an address area to which the address ADDR belongs. The address area checker 121_1 may generate a first selection signal for selecting any one of the first to mth hash functions 122' (where m is an integer greater than or equal to 2) based on the result of the determination, and provide the first selection signal to the multiplexer 121_2.

In an example embodiment, the multiplexer 121_2 may output a hash address to which a hash function selected from the first to mth hash functions 122' is applied according to the first selection signal. In an example embodiment, the hashed address may include a "B" bit, and "a" may be more than "B". Furthermore, the bit configuration of the hashed address may depend on the number of the first to kth ports P1 to Pk. For example, when the number of the first to kth ports P1 to Pk is 4 (i.e., when k=4), "B" may be "2", so that the hash addresses may represent the first to fourth ports P1 to P4, respectively.

In an example embodiment, the demultiplexer 121_3 may selectively output the address ADDR to at least one of the first to k-th ports P1 to Pk according to the hashed address. For example, the demultiplexer 121_3 may alternately output the address ADDR into the first port P1 and the second port P2 according to the hashed address. For another example, the demultiplexer 121_3 may output the address ADDR to the first port P1 according to the hashed address. For another example, the demultiplexer 121_3 may sequentially select the first port P1 and the second port P2 to output the address ADDR in response to the hashed address.

With further reference to fig. 3B, the hash function and port selection circuit 121' may further include an address processing circuit 121_4 as compared to the hash function and port selection circuit 121 of fig. 3A.

In an example embodiment, the address processing circuit 121_4 may process the address to have a format matching a hash function selected from the first to m-th (where m is an integer greater than or equal to 2) hash functions. For example, the number of bits and bit patterns used in the first through mth hash functions 122' respectively may be different for one address, and thus, additional processing may need to be performed on addresses subjected to different hash functions. In the present disclosure, a bit pattern may indicate a combination of multiple bits. For example, the first hash function may use a total of two bits including a first bit and a third bit among bits included in one address, and the second hash function may use a total of three bits including a second bit, a fourth bit, and a sixth bit among bits included in one address. The address processing circuit 121_4 may process an address according to the bit numbers and bit patterns used in the first to mth hash functions 122'.

However, this is an example, and example embodiments are not limited thereto. For example, the address processing circuit 121_4 may operate on addresses in various ways to support smooth memory access in example embodiments using multiple hash functions 122'.

The remaining configuration and operation of the hash function and port selection circuit 121' in fig. 3B have been described with reference to the hash function and port selection circuit 121 discussed with respect to fig. 3A, and thus a description thereof will be omitted.

Fig. 4 is a block diagram of a memory system 20 according to an example embodiment of the inventive concepts.

Referring to fig. 4, the memory system 20 may include the SoC 200 and the first to fourth memory devices 240_1 to 240_4. The SoC 200 may include first to fourth IPs 210_1 to 210_4, a BCU 220, and first to fourth memory controllers 230_1 to 230_4.

In an example embodiment, the first IP210_1 may be a master IP, and as described above, according to an example embodiment, the first IP210_1 may perform a normal operation to enable memory accesses of the first through fourth IPs 210_1 through 210_4.

In an example embodiment, the BCU 220 determines an address area to which the addresses output from the first to fourth IPs 210_1 to 210_4 belong, selects any one of a plurality of hash functions regarding the result of the determination, and applies the selected hash function to the address, thereby supporting memory accesses of the first to fourth IPs 210_1 to 210_4. Specific example embodiments thereof will be described with further reference to fig. 5A and 5B.

Fig. 5A is a flowchart illustrating an operation method of the SoC 200 of fig. 4, and fig. 5B is a diagram illustrating an operation of the SoC 200 of fig. 4 according to fig. 5A.

Referring to fig. 4 and 5A, in operation S200, the BCU 220 may receive a first address from the first IP 210_1. In operation S210, the BCU 220 may determine whether the first address belongs to the first address area. When the result of operation S210 is no, the BCU 220 may determine whether the first address belongs to the second address area in operation S211. When the result of operation S211 is no, the BCU 220 may determine whether the first address belongs to the third address area in operation S212.

When the result of operation S210 is yes, the BCU 220 may determine to selectively use the first hash function and apply the first hash function to the first address in operation S220. In operation S230, the BCU 220 may interleave the first to fourth ports P1 to P4 to access the first to fourth memory controllers 230_1 to 230_4.

Referring further to fig. 5B, the first to fourth memory controllers 230_1 to 230_4 may control memory operations of the first to fourth memory devices 240_1 to 240_4 based on the first addresses received through the first to fourth ports P1 to P4 using the method of interleaving access in operation S230. That is, the first IP 210_1 may perform memory access by repeatedly accessing the first, third, second and fourth memory devices 240_1, 240_3, 240_2, 240_4 in the order of the first, third, second and fourth memory devices 240_1, 240_3, 240_2, 240_4.

Referring to fig. 5A, when the result of operation S211 is yes, in operation S221, the BCU 220 may determine to selectively use the second hash function and apply the second hash function to the first address. In operation S231, the BCU 220 may interleave the first port P1 and the second port P2 to access the first memory controller 230_1 and the second memory controller 230_2.

Referring back to fig. 5B, the first and second memory controllers 230_1 and 230_2 may control memory operations of the first and second memory devices 240_1 and 240_2 based on the first addresses received through the first and second ports P1 and P2 using the method of interleaving access in operation S231. That is, the first IP 210_1 may perform memory access by repeatedly accessing the first memory device 240_1 and the second memory device 240_2 in the order of the first memory device 240_1 and the second memory device 240_2.

Referring to fig. 5A, when the result of operation S212 is yes, in operation S222, the BCU 220 may determine to selectively use a third hash function and apply the third hash function to the first address. In operation S232, the BCU 220 may sequentially access the first and second memory controllers 230_1 and 230_2 through the first and second ports P1 and P2.

Referring back to fig. 5B, the first and second memory controllers 230_1 and 230_2 may control memory operations of the third and fourth memory devices 240_3 and 240_4 based on the first addresses received through the third and fourth ports P3 and P4 using the method of interleaving access in operation S232. That is, when the first IP 210_1 first accesses the first memory device 240_1 and then uses a certain memory capacity, the first IP 210_1 may sequentially perform memory accesses to the second memory device 240_2.

Referring to fig. 5A, when the result of operation S212 is "no", in operation S233, the BCU 220 may determine to selectively use the fourth hash function and apply the fourth hash function to the first address. In operation S233, the BCU 220 may interleave the third port P3 and the fourth port P4 to access the third and fourth memory controllers 230_3 and 230_4.

Referring back to fig. 5B, the first and second memory controllers 230_1 and 230_2 may control memory operations of the third and fourth memory devices 240_3 and 240_4 based on the first addresses received through the first and second ports P1 and 230 using the method of interleaving access in operation S233. That is, the first IP 210_1 may perform memory access by repeatedly accessing the third memory device 240_3 and the fourth memory device 240_4 in the order of the third memory device 240_3 and the fourth memory device 240_4.

Although an example of accessing a memory through at least two ports is described with reference to fig. 5A and 5B, this is merely one example, and example embodiments are not limited thereto. For example, other example embodiments may be implemented, including example embodiments in which memory access is performed through a single port.

Fig. 6 is a flowchart illustrating a method of operation of the SoC 200 of fig. 4, according to an example embodiment.

Referring to fig. 4 and 6, in operation S300, a master IP (e.g., the first IP 210_1) may determine an operation type of a target IP. The target IP may be any one of the first IP 210_1 to the fourth IP 210_4. In the present disclosure, the operation type of the target IP may be based on a memory capacity, a data read/write request rate, and the like required for a data processing operation of the target IP. When the target IP supports a plurality of operation modes, the operation mode of the target IP may be changed according to the current operation mode. Further, the type of operation of the target IP may represent and may be referred to as the type of data processing operation of the target IP. In operation S310, the first IP 210_1 may map any one of a plurality of hash functions to the target IP based on the operation type of the target IP. The mapped hash function is applied to the address output by the target IP, so that a memory access method suitable for the operation type of the target IP can be provided for the target IP.

According to the operation method of fig. 6, the first IP 210_1 may map at least one hash function to the first to fourth IPs 210_1 to 210_4, respectively, and generate hash function mapping information indicating the mapping result. The hash-function mapping information may be used for power management of the SoC 200, a specific example embodiment of which will be described with reference to fig. 8.

Fig. 7 is a flowchart illustrating an operation method of the first and second IPs 210_1 and 210_2 of fig. 4 according to an example embodiment.

Referring to fig. 7, in operation S400, the first IP 210_1 may determine the type of data processing operation of the second IP 210_2. In an example embodiment, the first IP 210_1 may receive information about the type of the data processing operation from the second IP210_2 to perform operation S400. In operation S410, the first IP 210_1 may select a hash function matching the type determined in operation S400 from among a plurality of hash functions. In operation S420, the first IP 210_1 may generate a virtual address-physical address mapping table for the second IP210_2 based on the selected hash function. In this disclosure, the virtual address-physical address mapping table may be referred to as a mapping table. Operations S410 and S420 may be included in a mapping operation such as operation S310 in fig. 6. In operation S430, the first IP 210_1 may provide the generated mapping table to the second IP 210_2. In operation S440, the second IP210_2 may output the address of the address area corresponding to the hash function selected in operation S410 by using the mapping table. Specifically, the second IP210_2 may first generate a virtual address for memory access, convert the virtual address into a physical address according to a mapping table, and output the physical address. As described above, the mapping table may be directed to the address of the second IP210_2, so that the hash function selected in operation S410 may be applied to the address output from the second IP 210_2.

In some example embodiments, the first IP 210_1 may generate a mapping table corresponding to a type of data processing operation of each of the IPs 210_1, 210_2, 210_3, and 210_4, and may provide the mapping table for each of the IPs 210_1, 210_2, 210_3, and 210_4.

Fig. 8 is a flowchart illustrating a method of operation of an SoC, such as SoC 100 or SoC 200, according to an example embodiment.

Referring to fig. 8, in operation S500, a power management integrated circuit of the SoC may determine hash-function mapping information regarding each of a plurality of IPs. In operation S510, the power management integrated circuit may perform power management based on the hash-function mapping information. In particular, the power management integrated circuit may turn on only memory controllers for some memory accesses and turn off memory controllers that are not used with reference to the hash-function mapping information when only some of the plurality of IPs perform data processing operations, thereby reducing power consumption.

Fig. 9 is a block diagram illustrating a power management method of the SoC 200 according to an example embodiment. In the following, a description redundant from the description given with reference to fig. 4 will be omitted, and a description will be provided based on the example embodiment with reference to fig. 5A and 5B.

Referring to fig. 9, the soc 200 may include first to fourth IPs 210_1 to 210_4, a BCU 220, first to fourth memory controllers 230_1 to 230_4, and a power management integrated circuit.

In an example embodiment, only the second IP may be used to perform data processing operations. In this case, the first, third and fourth IPs 210_1, 210_3 and 210_4 may operate in an idle state in which no data processing operation is performed, and only the second IP210_2 may perform the data processing operation. In some example embodiments, the first IP 210_1, the third IP 210_3, and the fourth IP 210_4 may be in a power-off state.

In an example embodiment, the power management integrated circuit may determine the hash function mapped to the second IP210_2 currently performing the data processing operation by referring to the hash function mapping information. As described with reference to fig. 5A and 5B, when the second hash function is mapped to the second IP210_2, the second IP210_2 may access the first memory controller 230_1 and the second memory controller 230_2 using an interleaving access method. That is, since the second IP210_2 uses only the first and second memory controllers 230_1 and 230_2, the power management integrated circuit may power down the third and fourth memory controllers 230_3 and 230_4.

In addition, the third and fourth memory devices 240_3 and 240_4 may also be powered down under the control of the third and fourth memory controllers 230_3 and 230_4, respectively.

Fig. 10 is a block diagram illustrating a memory system 30 according to an example embodiment.

Referring to fig. 10, the memory system 30 may include the SoC 300 and the first to fourth memory devices 340_1 to 340_4. The SoC 300 may include first to fourth IPs 310_1 to 310_4, first to fourth BCUs 320_1 to 320_4, and first to fourth memory controllers 330_1 to 330_4.

In an example embodiment, the first to fourth IPs 310_1 to 310_4 may be connected with the first to fourth BCUs 320_1 to 320_4, respectively. The first to fourth BCUs 320_1 to 320_4 may be connected to the first to fourth memory devices 340_1 to 340_4, respectively. The first to fourth memory controllers 330_1 to 330_4 may be connected to the first to fourth memory devices 340_1 to 340_4, respectively.

In an example embodiment, the first to fourth IPs 310_1 to 310_4 may include first to fourth hash function groups 311_1 to 311_4, respectively. For example, each of the first through fourth IPs 310_1 through 310_4 may include a nonvolatile memory storing four different hash functions. For example, the first IP310_1 may determine an address region to which an output address of the first IP310_1 belongs, and select any one of the first to fourth hash functions of the first hash function group 311_1 based on the determined address region. The first IP310_1 may generate a hashed address by applying the selected hash function to the address, and select at least one of the first to fourth BCUs 320_1 to 320_4 based on the hashed address. The first IP310_1 may output an address to the selected at least one BCU. In a similar manner to the first IP310_1, the remaining IPs 310_2 to 310_4 may also select at least one of the first BCU320_1 to the fourth BCU 320_4. That is, as compared to the example embodiment of the SoC 100 described with reference to fig. 1, instead of the BCU 120, the SoC 300 shown in fig. 10 may include a plurality of BCUs 320_1 to 320_4, and the plurality of IPs 310_1 to 310_4 may directly select any one of the plurality of hash functions of the respective hash function groups 311_1 to 311_4 and apply the selected hash function to addresses of the plurality of IPs 310_1 to 310_4. As described above, the SoC 300 includes the plurality of BCUs 320_1 to 320_4, and the plurality of BCUs 320_1 to 320_4 are individually configured in the optimal position, thereby reducing the design complexity of the SoC 300. In this case, the plurality of IPs 310_1 to 310_4 can output an address by selecting at least one of the BCUs 320_1 to 320_4 using a plurality of hash functions.

In example embodiments, at least one BCU of the first to fourth BCUs 320_1 to 320_4 receiving an address may transmit the address to the memory controllers 330_1 to 330_4 connected thereto, respectively.

It will be appreciated that the example embodiments described with reference to fig. 1-9 are also applicable to the memory system 30 of fig. 10.

The implementation example of the memory system 30 shown in fig. 10 is only one example, to which example embodiments are not limited, and various structures are applicable.

Fig. 11A is a block diagram illustrating a memory system 40 according to an example embodiment, and fig. 11B is a block diagram illustrating an example of the arrangement of the memory system 40 of fig. 11A.

Referring to fig. 11A, the memory system 40 may include a SoC 400 and first to fourth memory devices 440_1 to 440_4. The SoC 400 may include first to fourth IPs 410_1 to 410_4, first to fourth BCUs 420_1 to 420_4, and first to fourth memory controllers 430_1 to 430_4.

In an example embodiment, each of the hash function groups 411_1 to 411_3 of the first to third IPs 410_3 may include first to fourth hash functions, and the hash function group 411_4' of the fourth IP 410_4 may include a second hash function. The fourth IP 410_4 includes only the second hash function among the first through fourth hash functions, as compared to the other IPs 410_1 through 410_3. In an example embodiment, the fourth IP 410_4 may be set or designed to use only a specific address area (e.g., the second address area), and thus, the fourth IP 410_4 may include only the second hash function. For example, each of the first to fourth IPs 410_1 to 410_4 may include a nonvolatile memory, each of the first to third IPs 410_1 to 410_3 may include a nonvolatile memory storing four hash functions, and the nonvolatile memory of the fourth IP may store only one hash function.

In an example embodiment, each of the first to third IPs 410_1 to 410_3 may be connected with all of the first to fourth BCUs 420_1 to 420_4. Further, as described with reference to fig. 5A and 5B, when the second hash function is applied to the address, since only the first and second memory controllers 430_1 and 430_2 are used, the fourth IP 410_4 may be connected to only the first and second BCUs 420_1 and 420_2.

However, fig. 11A is only an example embodiment, at least one of the first to third IPs 410_1 to 410_3 may use only some of the plurality of hash functions, and the first to third IPs 410_1 to 410_3 may be connected to the BCUs 420_1 to 420_4 in different manners according to the hash functions used by the first to third IPs 410_1 to 410_3.

With further reference to fig. 11B, fourth IP 410_4 may be disposed adjacent to first BCU 420_1 and second BCU 420_2 to which it is connected. Accordingly, the complexity of the internal path of the SoC 400 may be reduced, thereby enabling efficient design of the SoC 400.

Further, in example embodiments, when only the fourth IP 410_4 performs a data processing operation, the third and fourth BCUs 420_3 and 420_4 and the third and fourth memory controllers 430_3 and 430_4 not used for power management may be powered off.

Fig. 12 and 13 are diagrams illustrating an electronic system 1000 according to an example embodiment.

Referring to fig. 12, an electronic system 1000 may include an interface device 1100 (or interface chip), an SoC1200 to which the example embodiment is applied, and a semiconductor chip 1300. In some example embodiments, the SoC1200 may be referred to as a processing device and the semiconductor chip 1300 may be referred to as a memory device. SoC1200 may act as a host or application processor. The SoC1200 may include a system bus into which protocols of a bus standard having a specific standard are applied, and may include various IPs connected to the system bus. The system bus may be the BCU in fig. 1 to 11B.

As a standard specification of the system bus, an Advanced Microcontroller Bus Architecture (AMBA) protocol of an Advanced RISC Machine (ARM) may be applied. The bus types of the AMBA protocol may include advanced high-performance bus (AHB), advanced Peripheral Bus (APB), advanced extensible interface (AXI), AXI4, AXI Coherence Extension (ACE), and the like. In addition, other types of protocols may be used, such as uNet from Sony Inc., open core protocol (Open Core Protocol) of IBM CoreConnect, OCPIP, and so forth.

The example embodiments described with reference to fig. 1 through 11B may be applied to the IP and system bus of the SoC 1200. That is, the IP and system bus may support memory access to the semiconductor chip 1300 by using a plurality of hash functions.

The configuration of the semiconductor chip 1300 is further described with reference to fig. 13. The semiconductor chip 1300 may be a High Bandwidth Memory (HBM) including a plurality of channels CH1 to CH8 having independent interfaces. The semiconductor chip 1300 may include a plurality of wafers, and may include a buffer wafer 1310 and a plurality of memory wafers 1320 stacked on the buffer wafer 1310. For example, the first memory die 1321 may include a first channel CH1 and a third channel CH3, the second memory die 1322 may include a second channel CH2 and a fourth channel CH4, the third memory die 1323 may include a fifth channel CH5 and a seventh channel CH7, and the fourth memory die 1324 may include a sixth channel CH6 and an eighth channel CH8.

The buffer wafer 1310 may be connected to the interface device 1100 by conductors (e.g., bumps or solder balls) formed on the outer surface of the semiconductor chip 1300. The buffer die 1310 may receive commands, addresses, and data from the SoC 1200 through the interface device 1100 and provide the received commands, addresses, and data to at least one of the plurality of memory dies 1320. In addition, buffer die 1310 may provide data output to SoC 1200 from at least one channel of the plurality of memory die 1320 through interface device 1100.

The semiconductor chip 1300 may include a plurality of Through Silicon Vias (TSVs) 1330 through the plurality of memory wafers 1320, respectively. Each of the channels CH1 to CH8 may be divided into a left portion and a right portion. For example, in the fourth memory chip 1324, the sixth channel CH6 may be divided into dummy channels CH6a and CH6b, and the 8 th channel CH8 may be divided into dummy channels CH8a and CH8b. The through-silicon vias 1330 may be disposed between the dummy channels CH6a and CH6b of the sixth channel CH6 and between the dummy channels CH8a and CH8b of the eighth channel CH 8.

The buffer wafer 1310 may include a TSV area 1316, a serializer and deserializer (SERDES) area 1314, and an HBW physical layer interface (i.e., an HBM PHY area 1312). TSV area 1316 is an area where TSVs 1330 communicate with multiple memory die 1320.

The serializer and deserializer region 1314 is a region that provides the serializer and deserializer interface of the electronic component industry association (JEDEC) standard as the SoC 1200 increases in processing throughput and memory bandwidth requirements increase. The serializer and deserializer region 1314 may include a serializer and deserializer transmitter, a serializer and deserializer receiver, and a controller. The serializer and deserializer transmitter includes a parallel-to-serial circuit and a transmitter, and may receive and serialize a received parallel data stream. The serializer and deserializer receiver includes a receiver amplifier, an equalizer, a Clock and Data Recovery (CDR) circuit, and a parallel-to-serial conversion circuit, and may receive and parallelize a received serial data stream. The controller includes error detection circuitry, error correction circuitry, and registers (e.g., first-in-first-out (FIFO) registers).

HBM PHY region 1312 may include physical or electrical hierarchies as well as logical hierarchies provided for signals, frequencies, timing, drive, detailed operating parameters, and functions required for efficient communication between SoC 1200 and semiconductor chip 1300. The HBM PHY region 1312 may perform memory interactions, such as selecting rows and columns corresponding to memory cells, writing data to memory cells, or reading written data. The HBM PHY 1312 region may support the characteristics of the JEDEC standard HBM protocol.

The interface device 1100 may equalize and transmit signals provided from the SoC 1200 to the semiconductor chip 1300, and may equalize and transmit signals provided from the semiconductor chip 1300 to the SoC 1200. The interface device 1100 may interact with the SoC 1200 and the semiconductor chip 1300, and thus may perform data communication between the SoC 1200 and the semiconductor chip 1300.

The semiconductor chip 1300 shown in fig. 13 is an example, and the embodiment is not limited thereto, and other types of memory structures may be implemented.

Fig. 14 is a block diagram illustrating SoC 2000 in accordance with an example embodiment. SoC 2000 may refer to an integrated circuit integrated with components of a computing system or another electronic system. For example, the SoC may be an Application Processor (AP) and may include a processor and components that perform other functions.

Referring to fig. 14, the soc 2000 may include a CPU 2100, a DSP 2200, a GPU2300, an embedded memory 2400, a communication interface 2500, a memory interface 2600, and a system bus 2700. Components of SoC 2000 may communicate with each other over system bus 2700.

The central processor 2100 may process instructions and control the operation of components included in the SoC 2000. For example, the CPU 2100 may drive an operating system and execute an application program using the operating system by processing a series of instructions. DSP 2200 may generate useful data by processing digital signals, such as those provided from communication interface 2500. The GPU2300 may generate data for image output through a display device from image data provided from the embedded memory 2400 or the memory interface 2600, or may encode the image data. The embedded memory 2400 may store data necessary for the operation of the CPU 2100, the DSP 2200, and the GPU 2300. Memory interface 2600 may provide an interface with external memory of SoC 2000, e.g., dynamic Random Access Memory (DRAM), flash memory, etc.

Communication interface 2500 may provide serial communication with outside of SoC 2000. For example, communication interface 2500 may be connected to an ethernet network and may include serializers and deserializers for serial communication.

The example embodiments described with reference to fig. 1 to 11 may be applied to the CPU 2100, the DSP2200, the GPU 2300, the system bus 2700, and the memory interface 2600. In particular, the system bus 2700 may provide suitable memory access for each of the CPU 2100, DSP2200, and GPU 2300 by selectively using multiple hash functions for each address region. Memory interface 2600 may transfer addresses transferred from system bus 2700 to a storage device. Memory interface 2600 may function as the memory controller of fig. 1-11B.

In some example embodiments, each of the components represented by the blocks as shown in fig. 1, 3A, 3B, 4, 7, 9, 10, 11A, 11B, and 12-14 may be implemented as various numbers of hardware, software, and/or firmware structures that perform the various functions described above in accordance with the embodiments. For example, at least one of these components may include various hardware components including digital circuits, programmable or non-programmable logic devices or arrays, application Specific Integrated Circuits (ASICs), transistors, capacitors, logic gates or other circuitry, e.g., memories, processors, logic circuits, look-up tables, etc., using direct circuit structures, which may perform the respective functions under the control of one or more microprocessors or other control devices. Furthermore, at least one of these components may include a module, program, or portion of code containing one or more executable instructions for performing specified logical functions and executed by one or more microprocessors or other control devices. In addition, at least one of these components may also include or be implemented by a processor, such as a CPU, microprocessor, etc. that performs various functions. The functional aspects of the embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements, modules or units represented by the blocks or process steps may employ any number of related art techniques for electronic configuration, signal processing and/or control, data processing, and so forth.

While example embodiments have been particularly shown and described above, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims (20)

1. A system on a chip, comprising:

a plurality of memory controllers connected to the plurality of memory devices, respectively;

a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to perform data processing operations using at least one of the plurality of memory controllers; and

a bus connection interface configured to select a first hash function from a plurality of hash functions based on a first address region corresponding to a first address received from a first logic circuit of the plurality of logic circuits, obtain a hashed first address by applying the first hash function to the first address, and connect at least one of the plurality of memory controllers with the first logic circuit using a first access method corresponding to the hashed first address.

2. The system on a chip of claim 1, wherein the first access method is one of a plurality of access methods, and

Wherein the plurality of access methods respectively correspond to the plurality of hash functions and are different from each other.

3. The system on chip of claim 2, wherein the bus connection interface is further configured to select the first access method from the plurality of access methods based on the first address region and whether an interleaving access method is supported.

4. The system on chip of claim 1, wherein the bus connection interface comprises a plurality of ports respectively connected to the plurality of memory controllers and configured to output the first address to at least one port selected from the plurality of ports according to the first access method.

5. The system on a chip of claim 4, wherein the bus connection interface is configured to process the first address according to the first hash function.

6. The system-on-chip of claim 1, wherein the bus connection interface is configured to select a second hash function from the plurality of hash functions based on a second address region corresponding to a second address received from a second one of the plurality of logic circuits, obtain a hashed second address by applying the second hash function to the second address, and connect at least one of the plurality of memory controllers to the second logic circuit using a second access method corresponding to the hashed second address.

7. The system on a chip of claim 6, wherein the first access method is different from the second access method.

8. The system on a chip of claim 6, wherein a size of the first address region is different from a size of the second address region.

9. The system on chip of claim 1, wherein a master logic circuit of the plurality of logic circuits is configured to map the first hash function to the first logic circuit before the first logic circuit outputs the first address.

10. The system on chip of claim 9, wherein the master logic is configured to identify the first hash function from the plurality of hash functions based on a type of data processing operation the first logic is configured to perform.

11. The system on chip of claim 9, wherein the master logic circuit is configured to generate a virtual address to physical address mapping table and provide the virtual address to physical address mapping table to the first logic circuit, and

wherein the first logic circuit is configured to output the first address corresponding to the first address region based on the virtual address-to-physical address mapping table.

12. The system-on-chip of claim 1, further comprising: a power management integrated circuit configured to control power states of the plurality of memory controllers based on mapping information indicating a relationship between the plurality of logic circuits and the plurality of hash functions.

13. The system-on-chip of claim 1, wherein the plurality of logic circuits are divided into a plurality of logic circuit groups based on data access characteristics, and wherein the bus connection interface is configured to apply a different hash function to each of the plurality of logic circuit groups.

14. A method of operation of a system-on-chip, comprising:

identifying an address area corresponding to an address output from the logic circuit from among the plurality of address areas;

selecting a hash function corresponding to the identified address region from a plurality of hash functions;

applying a hash function to the address to obtain a hashed address; and

the logic circuit is connected to at least one of the plurality of memory controllers using an access method corresponding to the hashed address.

15. The method of operation of claim 14, further comprising: the access method is identified based on the identified address region and whether an interleaving access method is supported.

16. The operation method according to claim 14, wherein the access method is selected from a plurality of access methods, the plurality of access methods respectively corresponding to the plurality of address areas and being different from each other.

17. The method of operation of claim 14, further comprising: controlling a power state of at least one memory controller among the plurality of memory controllers that is not accessed in the access method.

18. A system on a chip, comprising:

a plurality of memory controllers connected to the plurality of memory devices, respectively;

a plurality of bus connection interfaces connected to the plurality of memory controllers, respectively; and

a first logic circuit configured to select any one of a plurality of first hash functions based on a first address region corresponding to a first address, apply the selected first hash function to the first address to obtain a hashed first address, and connect with at least one of the plurality of bus connection interfaces using a first access method corresponding to the hashed first address.

19. The system-on-chip of claim 18, further comprising a second logic circuit configured to select any one of at least one second hash function based on a second address region corresponding to a second address, apply the selected second hash function to the second address to obtain a hashed second address, and connect with at least one of the plurality of bus connection interfaces using a second access method corresponding to the hashed second address.

20. The system on chip of claim 19, wherein one of the at least one second hash function corresponds to one of the plurality of first hash functions.