CN116930312A - Chip detection method and device - Google Patents
Chip detection method and device Download PDFInfo
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- CN116930312A CN116930312A CN202210323227.4A CN202210323227A CN116930312A CN 116930312 A CN116930312 A CN 116930312A CN 202210323227 A CN202210323227 A CN 202210323227A CN 116930312 A CN116930312 A CN 116930312A
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- 238000001514 detection method Methods 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 141
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910003460 diamond Inorganic materials 0.000 claims description 9
- 239000010432 diamond Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000007689 inspection Methods 0.000 claims 2
- 230000008859 change Effects 0.000 abstract description 7
- 238000013461 design Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/72—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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Abstract
The invention discloses a chip detection method and device, and relates to the technical field of chip detection. After the chip to be tested is electrified, test signals are sequentially input to a plurality of input ports of the chip to be tested, meanwhile, test instructions are input to the chip to be tested, when the chip to be tested executes certain test instructions corresponding to a certain input port, the test signals have specific signal flow paths, the signal flow paths are provided with signals, the test signals can influence the magnetic field of the signal flow paths, so that the magnetic field intensity change of the surface of the chip to be tested can be perceived after the chip to be tested is scanned, the circuit structure of the chip to be tested can be drawn through the acquired magnetic field image of the chip to be tested, and if the circuit structure of the chip to be tested is different from the circuit structure of the original chip, the chip to be tested is determined to be tampered or forged, and the tampered or forged chip can be identified.
Description
Technical Field
The invention relates to the technical field of chip detection, in particular to a chip detection method and device.
Background
With the progress of technology, the use amount of chips in many industries is rapidly increased, but the limited chip productivity causes different degrees of chip shortage signs in the industries. Lawless persons attempt to imitate the same functional chip at low cost to gain benefit. The performance indexes of the imitated chips are greatly different from the original chips, and the service life and other indexes of the equipment can be seriously influenced. For chips with certain scale and complexity, the design, verification and manufacturing work is usually completed by cooperation of multiple companies at the upstream and downstream of the whole industry. For example, during the design phase, the number and variety of modules is quite large, often purchased from third parties in addition to autonomous design; most integrated circuit design companies require a custom process to the enterprise of a specialized representative during the manufacturing stage. Therefore, the integrated circuit chip may be tampered maliciously in various links of design and manufacture, and these actions seriously threaten the production and life of society.
In order to ensure normal operation of social production, maintain legal interests of masses, it has important meaning to verify whether the chip is tampered and whether the chip is a counterfeit chip.
Disclosure of Invention
The invention solves the technical problem of how to detect whether the chip is tampered or imitated by providing the chip detection method and the chip detection device.
On one hand, the embodiment of the invention provides the following technical scheme:
a chip detection method, comprising:
scanning the chip to be detected to obtain a magnetic field image of the chip to be detected;
after a chip to be tested is electrified, test signals are sequentially input to a plurality of input ports of the chip to be tested, and when the test signals are input, test instructions corresponding to the input ports connected with the test signals are input to the chip to be tested;
after each time of inputting the test instruction, drawing a circuit structure of the chip to be tested according to the magnetic field image;
if the circuit structure of the chip to be tested is different from that of the original chip, the chip to be tested is determined to be tampered or forged.
Preferably, the inputting test signals to the plurality of input ports of the chip to be tested sequentially includes:
and sequentially inputting the changed test signals to a plurality of input ports.
Preferably, the inputting test signals to the plurality of input ports of the chip to be tested sequentially includes:
and under the condition of controlling the plurality of input ports to be sequentially conducted, inputting the test signals to the conducted input ports.
Preferably, the inputting, to the chip to be tested, a test instruction corresponding to the input port to which the test signal is connected, includes:
and sequentially inputting each test instruction corresponding to the input port connected with the test signal to the chip to be tested.
Preferably, the drawing the circuit structure of the chip to be tested according to the magnetic field image includes:
determining a signal flow path when the chip to be tested executes each test instruction according to the magnetic field image;
and drawing the circuit structure of the chip to be tested according to each signal flow path.
On the other hand, the embodiment of the invention also provides the following technical scheme:
a chip testing device, comprising:
the diamond nitrogen vacancy color center sensor is used for scanning the chip to be detected;
the CMOS camera is used for acquiring the magnetic field image of the chip to be tested;
the signal generator is used for sequentially inputting test signals to a plurality of input ports of the chip to be tested after the chip to be tested is electrified;
the controller is used for inputting a test instruction corresponding to the input port connected with the test signal to the chip to be tested when the test signal is input;
the controller is also used for drawing the circuit structure of the chip to be tested according to the magnetic field image after the test instruction is input each time;
the controller is further configured to determine that the chip to be tested is tampered or counterfeit if the circuit structure of the chip to be tested is different from the circuit structure of the original chip.
Preferably, the signal generator is further configured to:
and sequentially inputting the changed test signals to a plurality of input ports.
Preferably, the signal generator is further configured to:
and under the condition of controlling the plurality of input ports to be sequentially conducted, inputting the test signals to the conducted input ports.
Preferably, the controller is further configured to:
and sequentially inputting each test instruction corresponding to the input port connected with the test signal to the chip to be tested.
Preferably, the controller is further configured to:
determining a signal flow path when the chip to be tested executes each test instruction according to the magnetic field image;
and drawing the circuit structure of the chip to be tested according to each signal flow path.
The one or more technical schemes provided by the invention have at least the following technical effects or advantages:
after the chip to be tested is electrified, test signals are sequentially input to a plurality of input ports of the chip to be tested, meanwhile, test instructions are input to the chip to be tested, when the chip to be tested executes certain test instructions corresponding to a certain input port, the test signals have specific signal flow paths, the signal flow paths are provided with signals, the test signals can influence the magnetic field of the signal flow paths, so that the magnetic field intensity change of the surface of the chip to be tested can be perceived after the chip to be tested is scanned, the circuit structure of the chip to be tested can be drawn through the acquired magnetic field image of the chip to be tested, and if the circuit structure of the chip to be tested is different from the circuit structure of the original chip, the chip to be tested is determined to be tampered or forged, and the tampered or forged chip can be identified.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a chip detection method in an embodiment of the invention;
FIG. 2 is a schematic diagram of a signal flow path magnetic field image in an embodiment of the invention;
fig. 3 is a schematic structural diagram of a chip detection device according to an embodiment of the invention.
Detailed Description
The embodiment of the invention solves the technical problem of how to detect whether the chip is tampered or imitated by providing the chip detection method and the chip detection device.
In order to better understand the technical scheme of the present invention, the following detailed description will refer to the accompanying drawings and specific embodiments.
First, the term "and/or" appearing herein is merely an association relationship describing associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
As shown in fig. 1, the chip detection method of the present embodiment includes:
step S1, scanning a chip to be tested to acquire a magnetic field image of the chip to be tested;
step S2, after the chip to be tested is electrified, test signals are sequentially input to a plurality of input ports of the chip to be tested, and when the test signals are input, test instructions corresponding to the input ports connected with the test signals are input to the chip to be tested;
step S3, after each test instruction is input, drawing a circuit structure of the chip to be tested according to the magnetic field image;
and S4, if the circuit structure of the chip to be detected is different from that of the original chip, determining that the chip to be detected is tampered or forged.
In step S1, after the chip to be tested is scanned, the change of the magnetic field intensity on the surface of the chip to be tested can be perceived, and the chip to be tested can be scanned by the diamond nitrogen vacancy color center sensor. Step S1 runs through the whole process. The magnetic field images of the chip to be tested are different before the chip to be tested is powered on, after the chip to be tested is powered on, before the test signal is input, and after the test signal is input. When the chip to be tested executes a certain test instruction corresponding to a certain input port, a specific signal flow path exists in the test signal, the signal flow path is provided with a signal flow, the test signal can influence the magnetic field of the signal flow path, the magnetic field image of the signal flow path after the input test signal is led in is different from the magnetic field image of the signal flow path before the input test signal, and when the test signal is a changed signal, the magnetic field image of the signal flow path is changed along with the change of the signal.
In step S2, the chip to be tested has a plurality of input ports, each input port is used for a different function, each input port generally has a plurality of functions, but there is also only one function of a certain input port, each function of each input port corresponds to a test instruction, the input port having a plurality of functions corresponds to a plurality of test instructions, and after the test instruction is input to the chip to be tested, the chip to be tested executes the test instruction to realize the corresponding function.
The test signal may be fixed or variable. In this embodiment, a variable test signal, such as a square wave signal, is preferably input, so in step S2, the sequentially inputting test signals to the plurality of input ports of the chip to be tested includes: and sequentially inputting the changed test signals to the plurality of input ports.
Only one input port is connected with a test signal at the same moment, each time the input test instruction is the test instruction corresponding to the input port connected with the test signal, only one test instruction corresponding to the input port connected with the test signal is input at the same moment, and the test signal is input to the next input port after all the test instructions of the current input port are executed. In order to realize that only one input port can be connected with a test signal at the same moment, only one input port can be controlled to be conducted at the same moment, and all input ports are controlled to be conducted in sequence, so that in step S2, the test signal is sequentially input to a plurality of input ports of a chip to be tested, and the method comprises the following steps: under the condition of controlling the plurality of input ports to be sequentially conducted, a test signal is input to the conducted input ports.
For an input port with multiple functions, in order to input only one test instruction at the same time, in step S2, the inputting, to the chip to be tested, a test instruction corresponding to the input port to which the test signal is connected, includes: and sequentially inputting each test instruction corresponding to the input port connected with the test signal to the chip to be tested.
In step S3, the drawing the circuit structure of the chip to be tested according to the magnetic field image includes: determining a signal flow path when the chip to be tested executes each test instruction according to the magnetic field image; and drawing the circuit structure of the chip to be tested according to each signal flow path.
In step S3, if the test signal is fixed, the magnetic field image of the chip to be tested can be continuously acquired before and after the chip to be tested inputs the test signal and executes a certain test instruction, and the position where the magnetic field changes on the chip to be tested before and after the input test signal is distinguished by a large number of magnetic field images, considering that the magnetic field image of the signal flow path after the input test signal is different from the magnetic field image of the signal flow path before the input test signal, and the path formed by all the positions is a signal flow path. In view of the fact that the signal flow paths have small magnetic field changes before and after inputting the test signal if the test signal is fixed, it is difficult to distinguish between them, and the test signal is preferably a changing signal in this embodiment. When a chip to be tested executes a certain test instruction, magnetic field images of the chip to be tested are continuously acquired, the magnetic field of the signal flow path is changed due to the fact that the test signal is changed, the magnetic field of the position outside the signal flow path is not changed, so that the position where the magnetic field on the chip to be tested is always changed can be identified through the continuously acquired magnetic field images, and the signal flow path corresponding to each test instruction is more easily obtained through the path formed by all the positions. Fig. 2 shows a signal flow path obtained according to a magnetic field image when a certain test instruction corresponding to a certain input port is executed.
When the chip to be tested executes one test instruction, a signal flow path can be obtained according to the magnetic field image of the chip to be tested, a plurality of signal flow paths can be obtained after all the test instructions corresponding to the same input port are executed, namely all the signal flow paths of one working area of the chip to be tested are obtained, and therefore all the signal flow paths of all the working areas of the chip to be tested can be obtained after all the test instructions corresponding to all the input ports are executed, and the circuit structure of the chip to be tested is obtained.
In step S4, if the chip to be tested is not tampered or not forged, the chip to be tested is an original chip, and the original chip can be understood as a regular chip of the same type as the chip to be tested.
As can be seen from the foregoing, in this embodiment, after the chip to be tested is powered on, a test signal is sequentially input to a plurality of input ports of the chip to be tested, and a test instruction is input to the chip to be tested at the same time, when the chip to be tested executes a certain test instruction corresponding to a certain input port, the test signal has a specific signal flow path, and a signal flows through the signal flow path, so that the test signal can influence a magnetic field of the signal flow path, after the chip to be tested is scanned, a change of the magnetic field intensity of the surface of the chip to be tested can be perceived, a circuit structure of the chip to be tested can be drawn through an obtained magnetic field image of the chip to be tested, and if the circuit structure of the chip to be tested is different from that of an original chip, the chip to be tested is determined to be tampered or forged, and the tampered or forged chip can be identified.
As shown in fig. 3, this embodiment further provides a chip detection device, including:
the diamond nitrogen vacancy color center sensor is used for scanning the chip to be detected;
the CMOS camera is used for acquiring a magnetic field image of the chip to be tested;
the signal generator is used for sequentially inputting test signals to a plurality of input ports of the chip to be tested after the chip to be tested is electrified;
the controller is used for inputting a test instruction corresponding to an input port connected with the test signal to the chip to be tested when the test signal is input;
the controller is also used for drawing the circuit structure of the chip to be tested according to the magnetic field image after the test instruction is input each time;
the controller is also used for determining that the chip to be detected is tampered or forged if the circuit structure of the chip to be detected is different from that of the original chip.
Wherein, the signal generator is further used for: sequentially inputting a changed test signal to a plurality of input ports; under the condition of controlling the plurality of input ports to be sequentially conducted, a test signal is input to the conducted input ports.
A controller, further configured to: sequentially inputting each test instruction corresponding to the input port connected with the test signal to the chip to be tested; determining a signal flow path when the chip to be tested executes each test instruction according to the magnetic field image; and drawing the circuit structure of the chip to be tested according to each signal flow path.
The diamond nitrogen vacancy colour-centre sensor consists of a diamond substrate with an N-V central skin. The diamond is directly placed on the chip to be tested, and the N-V layer is contacted with the surface of the chip to be tested. 532nm continuous laser is used for carrying out optical addressing on the N-V layer and is uniformly distributed on the N-V layer. A rectangular beam profile is formed using a flat top beam shaping element and a cylindrical lens, incident on the diamond surface at an angle of incidence shallow enough with respect to the top diamond surface to illuminate the entire N-V layer. N-V fluorescence is collected with a low power objective lens, filtered using a long pass filter, and imaged onto a CMOS camera to create a snapshot. The camera with high enough time resolution is selected, so that the magnetic field change in the power-on process of the chip to be tested can be recorded.
In this embodiment, after a chip to be tested is powered on, test signals are sequentially input to a plurality of input ports of the chip to be tested, and test instructions are input to the chip to be tested at the same time, when the chip to be tested executes a certain test instruction corresponding to a certain input port, the test signals have a specific signal flow path, and due to the fact that signals flow through the signal flow path, the test signals can influence the magnetic field of the signal flow path, the change of the magnetic field intensity of the surface of the chip to be tested can be perceived after the chip to be tested is scanned, the circuit structure of the chip to be tested can be drawn through the obtained magnetic field image of the chip to be tested, and if the circuit structure of the chip to be tested is different from the circuit structure of the original chip, the chip to be tested is determined to be tampered or forged, and the tampered or forged chip can be identified.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A chip detection method, comprising:
scanning the chip to be detected to obtain a magnetic field image of the chip to be detected;
after a chip to be tested is electrified, test signals are sequentially input to a plurality of input ports of the chip to be tested, and when the test signals are input, test instructions corresponding to the input ports connected with the test signals are input to the chip to be tested;
after each time of inputting the test instruction, drawing a circuit structure of the chip to be tested according to the magnetic field image;
if the circuit structure of the chip to be tested is different from that of the original chip, the chip to be tested is determined to be tampered or forged.
2. The chip testing method according to claim 1, wherein the sequentially inputting test signals to the plurality of input ports of the chip under test comprises:
and sequentially inputting the changed test signals to a plurality of input ports.
3. The chip testing method according to claim 1, wherein the sequentially inputting test signals to the plurality of input ports of the chip under test comprises:
and under the condition of controlling the plurality of input ports to be sequentially conducted, inputting the test signals to the conducted input ports.
4. The chip testing method according to claim 1, wherein the inputting the test instruction corresponding to the input port to which the test signal is connected to the chip to be tested includes:
and sequentially inputting each test instruction corresponding to the input port connected with the test signal to the chip to be tested.
5. The chip inspection method according to claim 1, wherein the drawing the circuit structure of the chip under test from the magnetic field image includes:
determining a signal flow path when the chip to be tested executes each test instruction according to the magnetic field image;
and drawing the circuit structure of the chip to be tested according to each signal flow path.
6. A chip inspection apparatus, comprising:
the diamond nitrogen vacancy color center sensor is used for scanning the chip to be detected;
the CMOS camera is used for acquiring the magnetic field image of the chip to be tested;
the signal generator is used for sequentially inputting test signals to a plurality of input ports of the chip to be tested after the chip to be tested is electrified;
the controller is used for inputting a test instruction corresponding to the input port connected with the test signal to the chip to be tested when the test signal is input;
the controller is also used for drawing the circuit structure of the chip to be tested according to the magnetic field image after the test instruction is input each time;
the controller is further configured to determine that the chip to be tested is tampered or counterfeit if the circuit structure of the chip to be tested is different from the circuit structure of the original chip.
7. The chip-scale package of claim 6, wherein the signal generator is further configured to:
and sequentially inputting the changed test signals to a plurality of input ports.
8. The chip-scale package of claim 6, wherein the signal generator is further configured to:
and under the condition of controlling the plurality of input ports to be sequentially conducted, inputting the test signals to the conducted input ports.
9. The chip testing device of claim 6, wherein the controller is further configured to:
and sequentially inputting each test instruction corresponding to the input port connected with the test signal to the chip to be tested.
10. The chip testing device of claim 6, wherein the controller is further configured to:
determining a signal flow path when the chip to be tested executes each test instruction according to the magnetic field image;
and drawing the circuit structure of the chip to be tested according to each signal flow path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210323227.4A CN116930312A (en) | 2022-03-30 | 2022-03-30 | Chip detection method and device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210323227.4A CN116930312A (en) | 2022-03-30 | 2022-03-30 | Chip detection method and device |
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| CN116930312A true CN116930312A (en) | 2023-10-24 |
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| CN202210323227.4A Pending CN116930312A (en) | 2022-03-30 | 2022-03-30 | Chip detection method and device |
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