CN116913896A

CN116913896A - Packaging structure and preparation method thereof

Info

Publication number: CN116913896A
Application number: CN202310997316.1A
Authority: CN
Inventors: 王金丽; 张树金; 许嗣拓; 周强
Original assignee: Maxscend Microelectronics Co ltd
Current assignee: Maxscend Microelectronics Co ltd
Priority date: 2023-08-09
Filing date: 2023-08-09
Publication date: 2023-10-20

Abstract

The application relates to a packaging structure and a preparation method thereof, wherein the packaging structure comprises: the wiring structure layer comprises a wiring layer and an isolation medium layer, wherein the wiring structure layer comprises a first surface and a second surface opposite to the first surface; the chip structure comprises a first chip and a second chip, wherein the first chip is attached to the first surface and is connected with the wiring layer; the second chip is attached to the second surface and connected with the wiring layer; the packaging layer covers the isolation layer, the chip structure and the wiring structure layer, and comprises a first packaging layer and a second packaging layer, wherein the first packaging layer covers the first chip and the first surface, and the second packaging layer covers the second chip and the second surface.

Description

Packaging structure and preparation method thereof

Technical Field

The application relates to the technical field of integrated circuits, in particular to a packaging structure and a preparation method thereof.

Background

As integrated circuits become more functional, higher performance and higher integration, and new types of integrated circuits emerge, packaging technology plays an increasingly important role in integrated circuit products, accounting for an increasing proportion of the value of the overall electronic system. Meanwhile, as integrated circuit feature sizes reach the nanometer level, transistors are evolving towards higher densities and higher clock frequencies, and packaging is evolving towards higher densities. However, existing packaging techniques are costly.

Disclosure of Invention

Based on this, it is necessary to provide a packaging structure and a method for manufacturing the same for the high packaging cost in the prior art.

To achieve the above object, in one aspect, the present application provides a package structure, including:

the wiring structure layer comprises a wiring layer and an isolation medium layer, wherein the wiring layer is positioned in the isolation medium layer;

the chip structure comprises a first chip and a second chip, wherein the first chip is attached to the first surface and is connected with the wiring layer; the second chip is attached to the second surface and is connected with the wiring layer;

the packaging layer covers the isolation layer, the chip structure and the wiring structure layer, the packaging layer comprises a first packaging layer and a second packaging layer, the first packaging layer covers the first chip and the first surface, and the second packaging layer covers the second chip and the second surface.

In one embodiment, the package structure includes:

and the welding structure is positioned on the wiring structure layer, connected with the wiring layer and exposed by the packaging layer.

In one embodiment, the solder structure surface is flush with the encapsulation layer surface;

or,

the soldering structure is raised relative to the surface of the encapsulation layer.

In one embodiment, the package structure includes:

and the isolation layer is positioned between the wiring structure layer and the packaging layer and covers at least one first chip and/or at least one second chip, so that the at least one first chip and/or the at least one second chip and the wiring structure layer have cavities.

In one embodiment, the isolation layer comprises:

a first isolation layer located between the first surface and the first encapsulation layer, so that a cavity is formed between the first chip and the first surface;

and/or the number of the groups of groups,

and the second isolation layer is positioned between the second surface and the second packaging layer, so that a cavity is formed between the second chip and the second surface.

The application also provides a preparation method of the packaging structure, which comprises the following steps:

providing a substrate;

forming a wiring structure layer on the substrate, wherein the wiring structure layer comprises a wiring layer and an isolation medium layer, the wiring layer is positioned in the isolation medium layer, the surface of the wiring structure layer, which is far away from the substrate, is a first surface, and the surface of the wiring structure layer, which is close to the substrate, is a second surface;

attaching a first chip to the first surface;

turning over the substrate and the structure formed thereon, and removing the substrate to expose the second surface of the wiring structure layer;

attaching a second chip to the second surface;

and forming a first packaging layer covering the first chip and the first surface, and forming a second packaging layer covering the second chip and the second surface.

In one embodiment, before forming a first encapsulation layer covering the first chip and the first surface and forming a second encapsulation layer covering the second chip and the second surface, the method comprises:

and forming a welding structure on the surface of the wiring structure layer, wherein the height of the welding structure is larger than that of the first chip or the second chip.

In one embodiment, forming a first encapsulation layer covering the first chip and the first surface, forming a second encapsulation layer covering the second chip and the second surface, includes:

forming a first packaging material layer covering the first chip, the first surface and the welding structure; grinding the first packaging material layer to form a first packaging layer, wherein the first packaging layer exposes the welding structure;

and/or the number of the groups of groups,

forming a second packaging material layer covering the second chip, the second surface and the welding structure; and grinding the second packaging material layer to form a second packaging layer, wherein the second packaging layer exposes the welding structure.

forming a first packaging layer covering the first chip, the first surface and the welding structure, wherein the thickness of the first packaging layer is smaller than the height of the welding structure;

and/or the number of the groups of groups,

and forming a second packaging layer covering the second chip, the second surface and the welding structure, wherein the thickness of the second packaging layer is smaller than the height of the welding structure.

and forming an isolation layer on the surface of at least one first chip and/or at least one second chip, so that a cavity is formed between the at least one first chip and/or the at least one second chip and the wiring structure layer.

According to the packaging structure and the preparation method thereof, the first chip is attached to the first surface, the first packaging layer covering the first chip and the first surface is formed, the substrate is turned over, the substrate is removed, the second surface of the wiring structure layer is exposed, the second chip is attached to the second surface, the second packaging layer is formed, and the packaging structure is formed. Therefore, the packaging difficulty is reduced, a large amount of interconnection structure materials can be avoided, the packaging cost is reduced, and the packaging difficulty is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flow chart of a method for manufacturing a package structure according to an embodiment;

FIG. 2 is a schematic diagram of a first package layer according to one embodiment;

FIG. 3 is a schematic diagram of a substrate according to one embodiment after being flipped;

FIG. 4 is a schematic diagram of a solder structure and a second chip provided in one embodiment;

FIG. 5 is a schematic diagram of a second package layer according to an embodiment;

FIG. 6 is a schematic diagram of a second package layer after being polished according to one embodiment;

fig. 7 is a schematic view of a second welding structure provided in another embodiment.

Reference numerals illustrate: 100-a substrate; 200-wiring structure layers; 201-a first surface; 202-a second surface; 210-a wiring layer; 211-connection structure; 220-isolating the dielectric layer; 300-a first chip; 310-a second chip; 400-a first encapsulation layer; 410-a second encapsulation layer; 500-welding the structure; 510-a first welded structure; 520-a second welded structure; 600-isolating layer; 700-cavity.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" another element or layer, it can be directly on, adjacent to, connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, these elements, components, regions, layers should not be limited by these terms. These terms are only used to distinguish one element, component, region or layer from another element, component, region or layer. Thus, a first element, component, region, layer discussed below could be termed a second element, component, region, layer without departing from the teachings of the present application.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

In one embodiment, referring to fig. 1, the present application provides a method for manufacturing a package structure, including the following steps:

step S100: a substrate 100 is provided.

Step S200: the wiring structure layer 200 is formed on the substrate 100, the wiring structure layer 200 includes a wiring layer 210 and an isolation dielectric layer 220, the wiring layer 210 is located in the isolation dielectric layer 220, a surface of the wiring structure layer 200 away from the substrate 100 is a first surface 201, and a surface of the wiring structure layer 200 close to the substrate 100 is a second surface 202.

Step S300: the first chip 300 is mounted on the first surface 201.

Step S400: the substrate 100 and structures formed thereon are flipped over and the substrate 100 is removed exposing the second surface 202 of the wiring structure layer 200.

Step S500: a second chip 310 is mounted on the second surface 202.

Step S800: a first encapsulation layer 400 is formed to cover the first chip 300 and the first surface 201, and a second encapsulation layer 410 is formed to cover the second chip 310 and the second surface 202.

In step S100, referring to fig. 2, the substrate 100 may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof.

In step S200, the wiring structure layer 200 includes a wiring layer 210 and an isolation dielectric layer 220. The wiring layer 210 and the isolation dielectric layer 220 may each include a plurality of layers. As an example, the multi-layered wiring layer 210 and the multi-layered isolation dielectric layer 220 may be alternately formed. Of course, the connection structure 211 may be provided between the adjacent wiring layers 210. As an example, the wiring structure layer 200 may be formed to the substrate 100 using a temporary bonding method. The wiring layer 210 may be formed using a metal wire rearrangement process.

The material of the wiring layer 210 may include cobalt, nickel, titanium, tungsten, tantalum, titanium tantalum, tungsten nitride, copper, aluminum, and other metal materials. The material of the isolation dielectric layer 220 may include a dry film, benzocyclobutene (BCB), polyimide (PI), or other organic material.

The first surface 201 of the wiring structure layer 200 is disposed opposite the second surface 202.

In step S300, the pins of the first chip 300 may be soldered to the wiring layer 210 located on the first surface 201. There may be a plurality of first chips 300, and the plurality of first chips 300 may be soldered to different positions of the wiring layer 210.

In step S400, referring to fig. 3, the substrate 100 and the structures formed thereon are flipped such that the second surface 202 is located at the upper portion and the structures such as the first package layer 400 and the first chip 300 are located at the lower portion.

When removing the substrate 100 by laser, the substrate 100 may be removed by laser, or the substrate 100 may be removed by mechanical polishing or the like. After the substrate 100 is removed, the second surface 202 of the wiring structure layer 200 is exposed.

The order of turning over the substrate 100 and removing the substrate 100 with laser light is not particularly limited in this embodiment. It will be appreciated that the substrate 100 may be flipped over first, and then the substrate 100 may be removed, or the substrate 100 may be removed first, and then the substrate 100 may be flipped over, to form the first package layer 400, the first chip 300, and other structures.

In step S500, referring to fig. 4 and 5, the pins of the second chip 310 are soldered on the wiring layer 210 on the second surface 202. The middle of the second chip 310 and the first chip 300 is a wiring structure layer.

In step S800, the first encapsulation layer 400 covers the first chip 300 and the first surface 201. The material of the first encapsulation layer 400 may include a mixture of epoxy and silicon dioxide, etc. As an example, the first encapsulation layer 400 may be injection-molded.

The second encapsulation layer 410 covers the second chip 310 and the second surface 202. The material of the second encapsulation layer 410 may include a mixture of epoxy and silicon dioxide, or the like. As an example, the second encapsulation layer 410 may also be injection molded.

In the related art, in the step of connecting a plurality of chips to a wiring structure layer during packaging, a first wiring structure layer is generally formed first, and then a first chip layer is formed on the first wiring structure layer. Then, the second wiring structure layer and the second chip layer are continuously formed on the first chip layer, and the like. An interconnection structure layer is prepared on each chip layer to realize interconnection between each layer of chips and adjacent wiring structure layers. Interconnect pillars and dielectric layers are often included in interconnect layers. The height of the interconnection column needs to be higher than that of the chip layer so as to achieve the purpose of connecting two adjacent wiring structure layers of the chip layer. When the interconnection layer is prepared, interconnection columns can be formed first, and then a dielectric material layer with the height larger than that of the interconnection columns is formed. The layer of ground dielectric material exposes the interconnect pillars and forms a dielectric layer. In this process, a large amount of dielectric layer material is consumed. In addition, the thickness of the dielectric layer needs to reach a certain value to achieve the purpose of stably supporting the interconnection column. As an example, when the thickness of the chip is generally greater than 100um, the height of the interconnect pillar needs to be greater than 150um, and the thickness of the dielectric material layer needs to reach 200um.

As the thickness of the chip increases, the height of the interconnect pillars increases, and correspondingly, the material of the dielectric layer from which the interconnect layer is made increases. The cost of interconnecting the pillars and dielectric layer is high. This increases the manufacturing cost of the package structure.

In the above embodiment, the first chip 300 and the second chip 310 are respectively mounted on the first surface 201 and the second surface 202 of the wiring structure layer 200, and the package layers are respectively covered on the surfaces of the first chip 300 and the second chip 310. In the above embodiment, the interconnection column and the dielectric layer with high cost are not needed to be prepared, and only the heights of the first package layer 400 and the second package layer 410 are required to be larger than the heights of the first chip 300 and the second chip 310, so that the package structure can be formed. Moreover, this makes the thickness of the package structure of the present embodiment smaller than that of the package structure in the related art, increasing the integration level of the package structure. The embodiment is applied to the wafer level packaging technology, and does not need to align multiple chip layers, so that the preparation difficulty is reduced.

In addition, since the second surface 202 is a surface close to the substrate 100, the second surface 202 is relatively flat. When the second chip 310 is mounted on the second surface 202, the flat surface can improve the mounting yield.

Meanwhile, by providing the isolation layer 600, the efficiency of preparing the cavity 700 is improved.

In one embodiment, prior to step S800, comprising:

step S700: the solder structure 500 is formed on the wiring structure layer 200, and the height of the solder structure 500 is greater than the height of the first chip 300 or the second chip 310.

In step S700, referring to fig. 4, the wiring structure layer 200 includes a first surface 201 and a second surface 202, and the solder structure 500 may be located on either the first surface 201 or the second surface 202, or the solder structure 500 may be located on both the first surface 201 and the second surface 202.

The solder structure 500 is located on the wiring layer 210 for connecting the wiring layer 210 with other devices. The solder structures 500 may be solder balls or bumps, etc. As an example, while the solder structure 500 may be a solder ball, the material of the solder structure 500 may include tin or a tin-silver alloy, or the like.

In forming the solder structure 500, a laser opening may be performed on the second surface 202, where the opening exposes the wiring layer 210. And then forming a solder structure 500 in the opening.

In the present embodiment, the height of the soldering structure 500 is greater than the height of the first chip 300 or the second chip 310, so that the subsequently formed encapsulation layer may cover only the surface of the chip structure while exposing the surface of the soldering structure 500.

In one embodiment, step S800 includes:

step S810: a first encapsulation material layer is formed covering the first chip 300, the first surface 201 and the solder structure 500.

Step S811: the first packaging material layer is polished to form a first packaging layer 400, and the first packaging layer 400 exposes the soldering structure 500.

And/or, step S820: a second layer of encapsulation material is formed covering the second chip 310, the second surface 202 and the solder structure 500.

Step S821: the second packaging material layer is polished to form a second packaging layer 410, and the second packaging layer 410 exposes the soldering structure 500.

In step S810, the height of the soldering structure 500 may be slightly higher than the first chip 300. When the first packaging material layer is formed, the first packaging material layer covers the solder structure 500, the first chip 300 and the surface of the first surface 201 at the same time.

In step S811, the thickness of the first encapsulation material layer is thinned by grinding or the like so that the solder structure 500 is exposed. At this time, the upper surface of the soldering structure 500 is flush with the upper surface of the thinned first encapsulation layer 400. The exposed solder structures 500 may be connected to other structures. Referring to fig. 6, as an example, the upper surface of the solder structure 500 is polished flat to form a first solder structure 510.

The process steps of step S820 and step S821 are similar to the previous steps, and are not repeated here. It is understood that either or both of the first encapsulation layer 400 and the second encapsulation layer 410 may be formed using the methods described above.

In the above embodiment, when the height of the solder structure 500 is slightly higher than that of the chip structure, the first encapsulation material layer or the second encapsulation material layer is formed to cover the chip structure, the wiring structure layer and the solder structure 500 at the same time. Part of the first packaging material layer or the second packaging material layer is removed by grinding, so that the soldering structure 500 is exposed, and the first packaging material layer or the second packaging material layer still covers the chip structure and the wiring structure layer, thereby forming a first packaging layer 400 and a second packaging layer 410. This allows the solder structure 500 to function as a connection to other devices while the encapsulation layer protects the chip structure and the wiring structure layer.

In another embodiment, step S800 further includes:

step S830: a first encapsulation layer 400 is formed covering the first chip 300, the first surface 201 and the solder structure 500, and the second encapsulation layer 400 has a thickness smaller than the height of the solder structure 500.

And/or, step S831: a second encapsulation layer 410 is formed covering the second chip 310, the second surface 202 and the solder structure 500, the second encapsulation layer 410 having a thickness less than the height of the solder structure 500.

Referring to fig. 7, in step S830 and step S831, the height of the solder structure 500 may be much higher than the height of the second chip 310. When the second encapsulation layer 410 is formed, the second encapsulation layer 410 cannot cover the soldering structure 500, but surrounds the lower portion of the soldering structure 500. At this time, the soldering structure 500 may be directly connected to other devices. As an example, the soldering structure 500 may include a second soldering structure 520, and the height of the second soldering structure 520 is much higher than the height of the second chip 310.

In one embodiment, step S800 is preceded by:

step S600: an isolation layer 600 is formed on the surface of the at least one first chip 300 and/or the at least one second chip 310 such that the at least one first chip 300 and/or the at least one second chip 310 has a cavity 700 between the wiring structure layer 200.

The package structure may be provided with a plurality of first chips 300 and a plurality of second chips 310. The isolation layer 600 covers the at least one first chip 300, or the isolation layer 600 covers the at least one second chip 310. Of course, the isolation layer 600 may cover the plurality of first chips 300 and the plurality of second chips 310 at the same time. At this time, a cavity 700 is formed between the chip structure under the isolation layer 600 and the wiring structure layer 200.

Referring to fig. 2, as an example, in some cases, the chip structure is a surface acoustic wave (Surface Acoustic Wave, SAW) filter chip. Since the SAW filter chip filters by acoustic waves, it is necessary to avoid contact between the SAW filter chip and the wiring structure layer 200. Therefore, the cavity 700 needs to be fabricated by the isolation layer 600 before the SAW filter chip is packaged. Cavity 700 maintains a gap between the SAW filter chip and wiring structure layer 200.

In the related art, when preparing the cavity, the isolation layer is usually prepared at a preset position, then an opening is formed on the isolation layer, and the chip structure is connected with the wiring layer through the opening. In this embodiment, the cavity 700 between the chip structure and the wiring structure layer is obtained by firstly attaching the chip structure on the surface of the wiring structure layer and then forming the isolation layer covering the chip structure. This increases the efficiency of preparing the cavity 700 and reduces the number of process steps.

Further, when a plurality of SAW filter chips are formed on one side of the wiring structure layer 200, a plurality of cavities 700 can be obtained by forming the isolation layer 600 covering the plurality of SAW filter chips at one time.

The material of the isolation layer 600 may include a dry film or the like.

Meanwhile, in step S800, it can be understood that when the isolation layer 600 covers the first chip 300, the first encapsulation layer 400 also covers the isolation layer 600. Also, when the isolation layer 600 covers the second chip 310, the second encapsulation layer 410 also covers the isolation layer 600.

In other cases, the chip structure is a Power Amplifier (PA) chip. At this time, the PA amplifier chip does not require the cavity 700, and thus the power amplifier surface does not require the preparation of the isolation layer 600.

It will be appreciated that when the packaging structure is provided with a SAW filter chip on one side and a PA amplifier chip on the other side, the isolation layer may be formed only on the side provided with the SAW filter chip.

Specifically, the isolation layer 600 includes a first isolation layer and a second isolation layer. The step S600 includes:

step S610: a first isolation layer is formed on the surface of the first chip 300, so that a cavity 700 is formed between the first chip 300 and the first surface 201.

Or comprises:

step S620: a second isolation layer is formed on the surface of the second chip 310, so that a cavity 700 is formed between the second chip 310 and the second surface 202.

It will be appreciated that the encapsulation structure may be provided with a first isolation layer, or the encapsulation structure may be provided with a second isolation layer. The packaging structure can also be provided with a first isolation layer and a second isolation layer at the same time.

Of course, the first chip 300 and the second chip 310 may be SAW filter chips or PA amplifier chips. Meanwhile, the first chip 300 and the second chip 310 in the present embodiment include, but are not limited to, SAW filters and PA amplifier chips, and may include other chips as well.

In another embodiment, when the first chip 300 is a SAW filter chip, the first isolation layer may be formed after the first chip 300 is fabricated, and then step S400 is performed. Also, when the second chip 310 is a SAW filter chip, a second isolation layer is formed after the second chip 310 is fabricated.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.

Based on the same inventive concept, in one embodiment, referring to fig. 5, a package structure is provided, including: wiring structure layer 200, chip structure and package layer.

The wiring structure layer 200 includes a first surface 201 and a second surface 202 opposite the first surface 201.

The wiring structure layer 200 also includes a wiring layer 210 and an isolation dielectric layer 220. The wiring layer 210 and the isolation dielectric layer 220 may each include a plurality of layers. As an example, the multi-layered wiring layer 210 and the multi-layered isolation dielectric layer 220 may be alternately formed. The material of the wiring layer 210 may include cobalt, nickel, titanium, tungsten, tantalum, titanium tantalum, tungsten nitride, copper, aluminum, and other metal materials. The material of the isolation dielectric layer 220 may include a dry film, benzocyclobutene (BCB), polyimide (PI), or other organic material.

The chip structure includes a first chip 300 and a second chip 310.

The first chip 300 is mounted on the first surface 201, and the first chip 300 is connected to the wiring layer 210. The second chip 310 is mounted on the second surface 202, and the second chip 310 is connected to the wiring layer 210.

The encapsulation layer includes a first encapsulation layer 400 and a second encapsulation layer 410. The first encapsulation layer 400 covers the first chip 300 and the first surface 201. The second encapsulation layer 410 covers the second chip 310 and the second surface 202. The material of the first encapsulation layer 400 and the material of the second encapsulation layer 410 may each include a mixture of epoxy and silicon dioxide, etc.

In this embodiment, the first chip 300 and the second chip 310 are disposed on the first surface 201 and the second surface 202 of the wiring structure layer 200, respectively, and then the first chip 300 and the second chip 310 form a package layer to form a package structure. Compared with the conventional technology, the packaging structure in the embodiment has no high-cost interconnection film layer, so that the packaging cost is reduced. Moreover, this makes the thickness of the package structure of the present embodiment smaller than that of the package structure in the related art, increasing the integration level of the package structure.

In one embodiment, the package structure includes a solder structure 500.

Referring to fig. 4, a solder structure 500 is disposed on the wiring structure layer 200 and connected to the wiring layer 211. In other words, the weld 500 may be located on either the first surface 201 or the second surface 202.

To enable the solder structure 500 to be connected to other devices, the encapsulation layer exposes the solder structure 500.

The solder structures 500 may be solder balls or bumps, etc. For example, the material of the solder structure 500 may include tin or a tin-silver alloy, or the like.

Referring to fig. 6, as an example, a welding structure 500 may include a first welding structure 510 and a second welding structure 520. The upper surface of the first solder structure 510 may be relatively flat and flush with the upper surface of the second package layer 410.

Referring to fig. 7, the second solder structure 520 may be raised with respect to the surface of the package layer, i.e., the height of the second solder structure 520 may be much higher than the second package layer 410.

Of course, the first and second welded structures 510 and 520 described above are for illustrative purposes only. It will be appreciated that, in another embodiment, the first solder structure 510 may be raised with respect to the surface of the encapsulation layer, and the upper surface of the second solder structure 520 may be relatively flat.

In one embodiment, a package structure includes: the spacer layer 600.

The isolation layer 600 is located between the wiring structure layer 200 and the encapsulation layer and covers the first chip 300, or the isolation layer 600 covers the first chip second chip 310. Of course, the isolation layer 600 may cover the first chip 300 and the second chip 310 at the same time. The material of the isolation layer 600 may include a dry film or the like.

The cavity 700 is formed between the isolation layer 600 and the first chip 300, and/or the cavity 700 is formed between the isolation layer 600 and the second chip 310.

As an example, the chip structure is a SAW filter chip. The SAW filter filters by acoustic waves, and therefore, needs to avoid contact with the wiring structure layer 200. Cavity 700 maintains a gap between the SAW filter chip and wiring structure layer 200.

It is understood that when the isolation layer 600 covers the first chip 300, the first encapsulation layer 400 also covers the isolation layer 600. Also, when the isolation layer 600 covers the second chip 310, the second encapsulation layer 410 also covers the isolation layer 600.

In one embodiment, referring to fig. 5, the isolation layer 600 includes: the first isolation layer and/or the second isolation layer (not shown).

As previously described, as an example, the first chip 300 is a SAW filter chip, the cavity 700 needs to be provided. At this time, the first isolation layer is located between the first surface 201 and the first encapsulation layer 400, so that the first chip 300 has a cavity 700 between the first surface 201 and the first surface.

Of course, when the first chip 300 is a PA amplifier chip. At this time, the PA amplifier chip does not require the cavity 700, and thus the power amplifier surface does not need to be provided with the first isolation layer.

The SAW filter and PA amplifier chip may be mounted on the first surface 201 at the same time. It is understood that there are a plurality of first chips 300, and the first isolation layer may be located on a portion of the surface of the first chips 300.

The second isolation layer is similar to the first isolation layer and will not be described in detail herein. Of course, the second chip 310 may be a SAW filter chip or a PA amplifier chip.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A package structure, comprising:

2. The package structure of claim 1, wherein the package structure comprises:

3. The package structure of claim 2, wherein the solder structure surface is flush with the package layer surface;

or,

4. The package structure of claim 1, wherein the package structure comprises:

5. The package structure of claim 4, wherein the isolation layer comprises:

and/or the number of the groups of groups,

6. The preparation method of the packaging structure is characterized by comprising the following steps:

providing a substrate;

attaching a first chip to the first surface;

attaching a second chip to the second surface;

7. The method of manufacturing a package structure according to claim 6, wherein forming a first package layer covering the first chip and the first surface, and before forming a second package layer covering the second chip and the second surface, further comprises:

8. The method of manufacturing a package structure according to claim 7, wherein forming a first package layer covering the first chip and the first surface, forming a second package layer covering the second chip and the second surface, comprises:

and/or the number of the groups of groups,

9. The method of manufacturing a package structure according to claim 7, wherein forming a first package layer covering the first chip and the first surface, forming a second package layer covering the second chip and the second surface, comprises:

and/or the number of the groups of groups,

10. The method of manufacturing a package structure according to claim 6, wherein forming a first package layer covering the first chip and the first surface, and before forming a second package layer covering the second chip and the second surface, comprises: