CN116915198A - Logarithmic amplifier adopting differential-to-single-ended transimpedance structure - Google Patents
Logarithmic amplifier adopting differential-to-single-ended transimpedance structure Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention belongs to the field of integrated circuits, and particularly relates to a logarithmic amplifier adopting a differential-to-single-ended transimpedance structure; the differential-to-single-end transimpedance amplifier comprises a main amplifying structure and a differential-to-single-end transimpedance structure; the main amplifying structure comprises 6 cascaded limiting amplifiers, the output of each limiting amplifier is connected with a rectifier, and the output of each rectifier is connected with a differential-to-single-ended trans-impedance output structure; the differential-to-single-end trans-impedance output structure comprises a plurality of resistors and a plurality of NPN tubes; the differential current can be converted into single-ended voltage through the differential-to-single-ended transimpedance output structure.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a logarithmic amplifier adopting a differential-to-single-ended transimpedance structure.
Background
A logarithmic amplifier is a device that compresses the dynamic range instantaneously in relation to the logarithmic relationship of the input and output signals. According to the existing logarithmic amplifier structure and application field, logarithmic amplifiers can be divided into three classes: basic logarithmic amplifier, baseband logarithmic amplifier and demodulation logarithmic amplifier. The invention relates to a large dynamic range logarithmic amplifier, which belongs to a demodulation logarithmic amplifier. The structure of the logarithmic amplifier with large dynamic range is shown in figure 1, and mainly comprises a multi-stage limiting amplifier and rectifiers, wherein the output of each stage limiting amplifier follows one rectifier, the output currents of all rectifiers are summed and then sampled through resistors to obtain an output voltage, and the output voltage and the amplitude of an input signal have approximate logarithmic relation. The multistage amplification post-rectification structure enables the logarithmic amplifier to have piecewise linear characteristics, and has the characteristic of high logarithmic precision in the whole dynamic range after multistage cascade connection, so that the logarithmic amplifier can be used as an independent detection device chip for the fields of signal processing, broadcasting, television, radar, handheld electronic equipment and the like, can also be used as a submodule for the middle video analog front end, and realizes the function of converting a middle video input power signal into a baseband signal.
The function of a logarithmic amplifier can be expressed by the formula:
V OUT to output voltage V IN For input signal amplitude, V Y Is logarithmic slope, V X Is the intercept ofA voltage. The input-output response of a typical logarithmic amplifier is shown in fig. 2, where the output voltage is linear with the input power, and the larger the input signal amplitude, the higher the output voltage.
When the input signal amplitude V of the logarithmic amplifier IN When the change occurs, the output voltage V OUT The rise/fall time of the amplifier is the response time of the logarithmic amplifier, the response time is an important technical index of the logarithmic amplifier, the smaller the response time is, the faster the output response is, and the shorter the time to reach the corresponding voltage of the input power is. The response time is mainly related to the conversion rate of the output stage, and the existing logarithmic amplifier output structure mainly adopts a transimpedance output structure formed by an operational amplifier.
Disclosure of Invention
In order to solve the problems, the invention provides a logarithmic amplifier with an output end adopting a differential-to-single-ended transimpedance structure, which comprises a main amplifying structure and a differential-to-single-ended transimpedance output structure; the main amplifying structure comprises 6 cascaded limiting amplifiers, the output of each limiting amplifier is connected with a rectifier, and the output of each rectifier is connected with a differential-to-single-ended trans-impedance output structure; the differential-to-single-end transimpedance output structure comprises a BUFFER BUFFER, a plurality of resistors and a plurality of NPN tubes.
Further, the limiting amplifier comprises an NPN tube Q L4 NPN tube Q L5 Current source I T1 Resistance R L1 Resistance R L2 Resistance R C1 Resistance R C2 Wherein:
resistor R L1 Upper end of (d) resistor R L2 The upper ends of the power supply are connected with a positive power supply VCC; resistor R C1 Right end of (2) and resistor R C2 The left end of the amplifier is connected with the point A', the point A is the common mode output end of the amplitude limiting amplifier, and the output voltage of the point A is V CM ；
NPN tube Q L4 The base electrode of the (C) is connected with the positive end of the input signal; NPN tube Q L4 Emitter and NPN tube Q of (C) L5 Emitter, current source I T1 Is connected with the upper end of the connecting rod; NPN tube Q L5 Collector, resistor R of (2) L2 Lower end of (2) and resistor R C2 The right end of the amplifier is connected with the point B 'which is the negative end of the differential mode output of the amplitude limiting amplifier, and the output voltage of the point B' is V CM -V od ；
NPN tube Q L5 The base electrode of the capacitor is connected with the negative end of the input signal; NPN tube Q L4 Collector, resistor R of (2) L1 Lower end of (C) resistor R C1 The left end of the (C) is connected with the C 'point which is the differential mode output positive end of the amplitude limiting amplifier, and the output voltage of the C' point is V CM +V od The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is od The difference between the output voltages at points B 'and C';
current source I T1 The lower end of which is grounded.
Further, the rectifier comprises an NPN tube Q L1 NPN tube Q L2 NPN tube Q L3 And a current source I T2 Wherein:
NPN tube Q L1 The base electrode of the NPN transistor Q is connected with the differential mode output positive end of the limiting amplifier L2 The base electrode of the NPN tube Q is connected with the differential mode output negative terminal of the limiting amplifier L3 The base electrode of the limiting amplifier is connected with the common mode output end of the limiting amplifier;
NPN tube Q L1 Emitter, NPN tube Q of (2) L2 Emitter, NPN tube Q of (2) L3 Emitter and current source I of (c) T2 Is connected with the upper end of the connecting rod; current source I T2 The lower end of the lower part is grounded; NPN tube Q L1 Collector and NPN tube Q L2 The collector of (C) is connected with the point D 'which is the differential mode output end of the rectifier, and the current of the point D' is I ID The method comprises the steps of carrying out a first treatment on the surface of the NPN tube Q L3 The collector of (2) is the common mode output end of the rectifier, and the current is I CM 。
Further, NPN tube Q L3 The emitter area of (2) is NPN tube Q L1 And NPN tube Q L2 2 times the emitter area, the following relationship is obtained:
I S3 ＝2I S2 ＝2I S1
wherein I is S1 ，I S2 ，I S3 Representing NPN tube Q L1 NPN tube Q L2 NPN tube Q L3 Transmission characteristic constant of (C) and crystalThe emitter area of the body tube is proportional.
Further, the differential to single-end transimpedance output structure comprises a BUFFER BUFFER, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, an NPN tube Q1, an NPN tube Q2, an NPN tube Q4, an NPN tube Q5, an NPN tube Q6, an NPN tube Q7 and an NPN tube Q8, wherein:
the upper end of the resistor R1 is connected with a power supply VS; the lower end of the resistor R1 is connected with the upper end of the resistor R5 and the collector of the NPN tube Q8 at the point A, and an independent branch line extending from the point A is connected with the output current of the negative end of the rectifier;
the upper end of the resistor R2 is connected with a power supply VS; the lower end of the resistor R2 is connected with the upper end of the resistor R6 at the point B, and an independent branch line extending from the point B is connected with the output current of the positive end of the rectifier;
the upper end of the resistor R3 is connected with the emitter of the NPN tube Q8 at the point C, and the point C is connected with the input end BF of the BUFFER BUFFER IN The method comprises the steps of carrying out a first treatment on the surface of the The lower end of the resistor R3 is grounded; the output end of the BUFFER BUFFER is the output end V of the logarithmic amplifier OUT ；
The upper end of the resistor R4 is connected with a power supply VS; the lower end of the resistor R4 is connected with the emitter of the NPN tube Q6;
the lower end of the resistor R5 is connected with the emitter of the NPN tube Q4;
the lower end of the resistor R6 is connected with the emitter of the NPN tube Q5;
the collector of the NPN tube Q1 is connected with the collector of the NPN tube Q4 and the base of the NPN tube Q8, the base of the NPN tube Q1 is connected with the base of the NPN tube Q2, the collector of the NPN tube Q2 and the collector of the NPN tube Q5, and the emitter of the NPN tube Q1 is grounded;
the emitter of the NPN tube Q2 is grounded;
the base electrode of the NPN tube Q4, the base electrode of the NPN tube Q5, the base electrode of the NPN tube Q6, the collector electrode of the NPN tube Q6 and the collector electrode of the NPN tube Q7 are connected at a point D;
the base of NPN tube Q7 is connected with BIAS voltage BIAS, and the emitter of NPN tube Q7 is grounded.
Further, the BUFFER includes a PNP transistor Q9, a PNP transistor Q10, a PNP transistor Q11, a PNP transistor Q12, an NPN transistor Q13, an NPN transistor Q14, a PNP transistor Q15, a PNP transistor Q16, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a current source I1, and a current source I2, wherein:
the base electrode of the PNP tube Q9 is the input end of the BUFFER BUFFER; the collector of the PNP tube Q9 is connected with the upper end of the resistor R7 and the emitter of the NPN tube Q14; the emitter of the PNP tube Q9 is connected with the lower end of the current source I1 and the emitter of the PNP tube Q10;
the base electrode of the PNP tube Q10 is connected with the lower end of the resistor R9 at the point E; the collector of the PNP tube Q10 is connected with the upper end of the resistor R8 and the emitter of the NPN tube Q13;
the base electrode of the PNP tube Q11 is connected with the collector electrode of the PNP tube Q11, the base electrode of the PNP tube Q12 and the collector electrode of the NPN tube Q13; the emitter of the PNP tube Q11, the upper end of the current source I1, the emitter of the PNP tube Q12, the upper end of the current source I2 and the emitter of the PNP tube Q16 are all connected to a power supply VCC;
the collector of the PNP tube Q12 is connected with the collector of the NPN tube Q14, the base of the PNP tube Q15 and the left end of the capacitor C1;
the base electrode of the NPN tube Q13 is connected with the base electrode of the NPN tube Q14 and the reference voltage VB;
the emitter of the PNP tube Q15 is connected with the lower end of the current source I2 and the base of the PNP tube Q16; the collector of the PNP tube Q15 is grounded;
the collector of the PNP tube Q16 is connected with the upper end of the resistor R9;
the lower end of the resistor R9, the right end of the capacitor C1 and the upper end of the resistor R10 are connected at the point E, and the point E is the output end of the BUFFER BUFFER;
the lower end of the resistor R7, the lower end of the resistor R8 and the lower end of the resistor R10 are grounded.
Further, the resistance value of the resistor R2 is the same as that of the resistor R1.
Further, the relation between the output current and the output voltage of the differential-to-single-end transimpedance output structure is as follows:
V OUT ＝I OUT ·R 3 ＝(I OUTP -I OUTM )·R 3
wherein R is 3 Represents the resistance value of the resistor R3, I OUTM Representing the sum of the output currents at the differential mode outputs of all rectifiers, I OUTP Representing the sum of the output currents at the common mode outputs of all rectifiers, V OUT Representing the logarithmic amplifier output voltage.
The invention has the beneficial effects that:
the invention can realize the conversion of differential current into single-ended voltage through the structure of converting differential into single-ended transimpedance output, is particularly suitable for the output end of a logarithmic amplifier, converts the rectified summation current into output voltage, and realizes the logarithmic relationship between an input signal and the output voltage.
The invention directly performs I-V conversion through the current mirror, does not relate to the conversion process of the operational amplifier closed loop feedback structure, can achieve the order of tens of ns in response time, and solves the problem of slow response time of the operational amplifier output stage adopted by the traditional logarithmic amplifier output stage.
The output stage of the invention is added with the buffer unit to reduce the output impedance of the logarithmic amplifier, and the buffer isolates the output end of the transimpedance output structure from the load, so that the logarithmic amplifier can drive the load and the logarithmic slope is not influenced by the load resistance.
The invention has strong universality, is suitable for bipolar technology and is suitable for application occasions of converting differential current into single-ended voltage.
Drawings
FIG. 1 is a logarithmic amplifier topology of the present invention;
FIG. 2 is a functional schematic of a logarithmic amplifier of the invention;
FIG. 3 is a circuit diagram of a limiting amplifier and rectifier of the present invention;
FIG. 4 is a schematic diagram of the rectifier and output stage interface of the present invention
FIG. 5 is a diagram of a fast response differential to single ended transresistance output architecture of the present invention;
FIG. 6 is a schematic diagram of an output stage buffer according to the present invention;
fig. 7 is a graph of the response time of a logarithmic amplifier of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a logarithmic amplifier adopting a differential-to-single-ended transimpedance structure, which is shown in figure 1 and comprises a main amplifying structure and an output stage I/V conversion module; the main amplifying structure comprises 6 cascade limiting amplifiers, the output of each limiting amplifier is connected with a rectifier, and the output of each rectifier is connected with the I/V conversion module of the output stage.
In particular, the limiting amplifier is essentially a differential pair of resistors acting as a load, which may be approximated as a linear amplifier when the input signal amplitude is small. The limiting amplifier is shown in FIG. 3, and comprises NPN tube Q L4 NPN tube Q L5 Current source I T1 Resistance R L1 Resistance R L2 Resistance R C1 Resistance R C2 Wherein:
resistor R L1 Upper end of (d) resistor R L2 The upper ends of the power supply are connected with a positive power supply VCC; resistor R C1 Right end of (2) and resistor R C2 The left end of the amplifier is connected with the point A', the point A is the common mode output end of the amplitude limiting amplifier, and the output voltage of the point A is V CM ；
NPN tube Q L4 The base electrode of the (C) is connected with the positive end of the input signal; NPN tube Q L4 Emitter and NPN tube Q of (C) L5 Emitter, current source I T1 Is connected with the upper end of the connecting rod; NPN tube Q L5 Collector, resistor R of (2) L2 Lower end of (2) and resistor R C2 The right end of the amplifier is connected with the point B 'which is the negative end of the differential mode output of the amplitude limiting amplifier, and the output voltage of the point B' is V CM -V od ；
NPN tube Q L5 The base electrode of the capacitor is connected with the negative end of the input signal; NPN tube Q L4 Collector, resistor R of (2) L1 Lower end of (C) resistor R C1 The left end of the (C) is connected with the C 'point which is the differential mode output positive end of the amplitude limiting amplifier, and the output voltage of the C' point is V CM +V od The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is od The difference between the output voltages at points B 'and C';
current source I T1 The lower end of which is grounded.
The input to output relationship of the limiting amplifier is expressed as:
V OD ＝AV ID (1)
wherein V is ID Representing the limiting amplifier input voltage, V OD The limiting amplifier output voltage is represented, and a is the limiting amplifier gain.
When the amplitude of the input signal reaches the threshold, the corresponding output amplitude is not increasing with the increase of the input, but is limited to a fixed amplitude.
Specifically, the rectifier is used for detecting the power information of the signal to be detected and outputting a differential current corresponding to the power information. The rectifier circuit structure is shown in FIG. 3 and comprises an NPN tube Q L1 NPN tube Q L2 NPN tube Q L3 And a current source I T2 Wherein:
NPN tube Q L1 The base electrode of the NPN transistor Q is connected with the differential mode output positive end of the limiting amplifier L2 The base electrode of the NPN tube Q is connected with the differential mode output negative terminal of the limiting amplifier L3 The base electrode of the limiting amplifier is connected with the common mode output end of the limiting amplifier;
NPN tube Q L1 Emitter, NPN tube Q of (2) L2 Emitter, NPN tube Q of (2) L3 Emitter and current source I of (c) T2 Is connected with the upper end of the connecting rod; current source I T2 The lower end of the lower part is grounded; NPN tube Q L1 Collector and NPN tube Q L2 The collector of (C) is connected with the point D 'which is the differential mode output end of the rectifier, and the current of the point D' is I ID The method comprises the steps of carrying out a first treatment on the surface of the NPN tube Q L3 The collector of (2) is the common mode output end of the rectifier, and the current is I CM 。
The rectifier is of a common emitter differential pair structure, two differential mode ends and a common mode end are simultaneously connected into a differential pair, and the following equation set can be obtained according to the connection relation in fig. 3:
wherein V is CM Representing the output common mode voltage, V, at the common mode output of the limiting amplifier BE1 Representing NPN tube Q L1 Base-emitter voltage difference, V BE2 Representing NPN tube Q L2 Base-emitter voltage difference, V BE3 Representing NPN tube Q L3 Base-emitter voltage difference of (a); from the formulas (2) and (3), it can be deduced that:
wherein V is T Indicating the dielectric constant of the semiconductor, I C1 Representing NPN tube Q L1 Collector current of I C2 Representing NPN tube Q L2 Collector current of I C3 Representing NPN tube Q L3 Collector current of I S1 ，I S2 ，I S3 Representing NPN tube Q L1 NPN tube Q L2 NPN tube Q L3 Is a transmission characteristic constant of (a).
Meanwhile, the following relation exists between the currents:
I C1 +I C2 +I C3 ＝I T2 (6)
wherein I is T2 Representing the current source I T2 Is set in the above-described state.
During design, NPN tube Q is selected L3 The emitter area of (2) is NPN tube Q L1 And NPN tube Q L2 2 times the emitter area, namely:
I S3 ＝2I S2 ＝2I S1 (7)
the following expressions can be obtained according to the expressions (4) to (7):
I ID ＝I C1 +I C2 for differential mode output current of single-stage rectifier, I CM ＝I C3 For single-stage rectifier common mode output current, as shown in FIG. 3, single-stage rectifier output current I DEM Can be represented by formula (11):
as can be seen from equation (11), the differential current output by a single stage rectifier is exponentially related to the input signal amplitude, and since the input power is logarithmically related to the input signal amplitude, the differential current output by each stage rectifier is linearly related to the input power.
As shown in fig. 4, the output current of the differential mode output terminal and the output current of the common mode output terminal of each stage rectifier are added to obtain a total positive output current I OUTP And total negative terminal output current I OUTM And make up the total differential current I OUT In order to obtain an output voltage which is in linear relation with the input power, an output structure is required to be introduced, so that the function of converting the total differential current into single-ended voltage is realized; in addition, in order to make the logarithmic amplifier respond to the change of the input amplitude quickly, the output structure needs to have the characteristic of quick response, so the invention provides a differential-to-single-end transimpedance output structure as shown in fig. 4.
Specifically, as shown in fig. 5, the differential-to-single-end transimpedance output structure includes a BUFFER, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, an NPN tube Q1, an NPN tube Q2, an NPN tube Q4, an NPN tube Q5, an NPN tube Q6, an NPN tube Q7, and an NPN tube Q8.
The connection relation of the differential-to-single-end trans-impedance output structure is as follows:
the upper end of the resistor R1 is connected with a power supply VS; the lower end of the resistor R1 is connected with the upper end of the resistor R5 and the collector of the NPN tube Q8 at the point A, and an independent branch line extending from the point A is connected with the output current of the negative end of the rectifier;
the upper end of the resistor R2 is connected with a power supply VS; the lower end of the resistor R2 is connected with the upper end of the resistor R6 at the point B, and an independent branch line extending from the point B is connected with the output current of the positive end of the rectifier;
the upper end of the resistor R3 is connected with the emitter of the NPN tube Q8 at the point C, and the point C is connected with the input end BF of the BUFFER BUFFER IN The method comprises the steps of carrying out a first treatment on the surface of the The lower end of the resistor R3 is grounded; the output end of the BUFFER BUFFER is the output end V of the logarithmic amplifier OUT ；
The upper end of the resistor R4 is connected with a power supply VS; the lower end of the resistor R4 is connected with the emitter of the NPN tube Q6;
the lower end of the resistor R5 is connected with the emitter of the NPN tube Q4;
the lower end of the resistor R6 is connected with the emitter of the NPN tube Q5;
the collector of the NPN tube Q1 is connected with the collector of the NPN tube Q4 and the base of the NPN tube Q8, the base of the NPN tube Q1 is connected with the base of the NPN tube Q2, the collector of the NPN tube Q2 and the collector of the NPN tube Q5, and the emitter of the NPN tube Q1 is grounded;
the emitter of the NPN tube Q2 is grounded;
the base electrode of the NPN tube Q4, the base electrode of the NPN tube Q5, the base electrode of the NPN tube Q6, the collector electrode of the NPN tube Q6 and the collector electrode of the NPN tube Q7 are connected at a point D;
the base of NPN tube Q7 is connected with BIAS voltage BIAS, and the emitter of NPN tube Q7 is grounded.
Specifically, as shown in fig. 6, the BUFFER includes a PNP transistor Q9, a PNP transistor Q10, a PNP transistor Q11, a PNP transistor Q12, an NPN transistor Q13, an NPN transistor Q14, a PNP transistor Q15, a PNP transistor Q16, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a current source I1, and a current source I2, wherein:
the base electrode of the PNP tube Q9 is the input end of the BUFFER BUFFER; the collector of the PNP tube Q9 is connected with the upper end of the resistor R7 and the emitter of the NPN tube Q14; the emitter of the PNP tube Q9 is connected with the lower end of the current source I1 and the emitter of the PNP tube Q10;
the base electrode of the PNP tube Q10 is connected with the lower end of the resistor R9 at the point E; the collector of the PNP tube Q10 is connected with the upper end of the resistor R8 and the emitter of the NPN tube Q13;
the base electrode of the PNP tube Q11 is connected with the collector electrode of the PNP tube Q11, the base electrode of the PNP tube Q12 and the collector electrode of the NPN tube Q13; the emitter of the PNP tube Q11, the upper end of the current source I1, the emitter of the PNP tube Q12, the upper end of the current source I2 and the emitter of the PNP tube Q16 are all connected to a power supply VCC;
the collector of the PNP tube Q12 is connected with the collector of the NPN tube Q14, the base of the PNP tube Q15 and the left end of the capacitor C1;
the base electrode of the NPN tube Q13 is connected with the base electrode of the NPN tube Q14 and the reference voltage VB;
the emitter of the PNP tube Q15 is connected with the lower end of the current source I2 and the base of the PNP tube Q16; the collector of the PNP tube Q15 is grounded;
the collector of the PNP tube Q16 is connected with the upper end of the resistor R9;
the lower end of the resistor R9, the right end of the capacitor C1 and the upper end of the resistor R10 are connected at the point E, and the point E is the output end of the BUFFER BUFFER;
the lower end of the resistor R7, the lower end of the resistor R8 and the lower end of the resistor R10 are grounded.
Specifically, adopt I OUTM Representing the sum of the output currents at the differential mode outputs of all rectifiers, I OUTP Representing the sum of the output currents at the common mode outputs of all rectifiers, the process of converting the total differential current to a single-ended voltage is specifically analyzed according to the structure shown in fig. 5. First, the relation between the output voltage and the output current is derived according to the circuit structure of fig. 5, which is expressed as:
wherein V is 1 Representing the voltage at point A, V 2 Representation ofVoltage at point B, R 1 Represents the resistance value of the resistor R1, R 2 Representing the resistance value of resistor R2, V S Represents the voltage of the power supply VS, I 1 Represents collector current of NPN tube Q1, I 2 Represents collector current of NPN tube Q1, I OUT Indicating the resistor R3 and NPN tube Q8 branch operating current.
I due to the action of the current mirror 2 ＝I 1 Assuming that the resistances of the resistor R1 and the resistor R2 are the same, the subtraction of the equation (12) and the equation (13) can be obtained:
in addition, V can be found from the circuit structure 1 And V 2 Is a correlation of (a):
V 1 -I 1 ·R 1 -V BE4 ＝V 3 ＝V 2 -I 2 ·R 2 -V BE5 (15)
wherein V is 3 Representing the voltage at point D, V BE4 Representing the base-emitter voltage difference, V, of PNP tube Q4 BE5 Representing the base-emitter voltage difference of PNP transistor Q5. Due to I 2 ＝I 1 Then formula (15) may be V 2 ＝V 1 Thus, formula (14) can be converted into:
I OUT ＝I OUTP -I OUTM
V OUT ＝I OUT ·R 3 ＝(I OUTP -I OUTM )·R 3
wherein R is 3 The resistance of the resistor R3.
From the above analysis, the differential-to-single-end transimpedance output structure can convert the differential current output by the rectifier into a single-end voltage. In addition, the structure shown in fig. 5 directly performs I-V conversion through a current mirror, does not involve the closed loop feedback structure conversion process, is processed by using a low-voltage complementary bipolar process, has response time of 40ns, and has the characteristic of quick response as shown in fig. 7.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "connected," "secured," "rotated," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other, unless explicitly defined otherwise, the meaning of the terms described above in this application will be understood by those of ordinary skill in the art in view of the specific circumstances.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The logarithmic amplifier adopting the differential-to-single-ended transimpedance structure is characterized by comprising a main amplifying structure and a differential-to-single-ended transimpedance output structure; the main amplifying structure comprises 6 cascaded limiting amplifiers, the output of each limiting amplifier is connected with a rectifier, and the output of each rectifier is connected with a differential-to-single-ended trans-impedance output structure; the differential-to-single-end transimpedance output structure comprises a BUFFER BUFFER, a plurality of resistors and a plurality of NPN tubes.
2. The logarithmic amplifier employing differential to single ended transimpedance configuration according to claim 1, wherein the limiting amplifier comprises NPN transistor Q L4 NPN tube Q L5 Current source I T1 Resistance R L1 Resistance R L2 Resistance R C1 Resistance R C2 Wherein:
resistor R L1 Upper end of (d) resistor R L2 The upper ends of the power supply are connected with a positive power supply VCC; resistor R C1 Right end of (2) and resistor R C2 The left end of the amplifier is connected with the point A', the point A is the common mode output end of the amplitude limiting amplifier, and the output voltage of the point A is V CM ；
NPN tube Q L4 The base electrode of the (C) is connected with the positive end of the input signal; NPN tube Q L4 Emitter and NPN tube Q of (C) L5 Emitter, current source I T1 Is connected with the upper end of the connecting rod; NPN tube Q L5 Collector, resistor R of (2) L2 Lower end of (2) and resistor R C2 The right end of the amplifier is connected with the point B 'which is the negative end of the differential mode output of the amplitude limiting amplifier, and the output voltage of the point B' is V CM -1/2*V od ；
NPN tube Q L5 The base electrode of the capacitor is connected with the negative end of the input signal; NPN tube Q L4 Collector, resistor R of (2) L1 Lower end of (C) resistor R C1 The left end of the (C) is connected with the C 'point which is the differential mode output positive end of the amplitude limiting amplifier, and the output voltage of the C' point is V CM +1/2*V od The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is od The difference between the output voltages at points B 'and C';
current source I T1 The lower end of which is grounded.
3. The logarithmic amplifier employing a differential to single ended transimpedance structure according to claim 1, wherein the rectifier comprises an NPN transistor Q L1 NPN tube Q L2 NPN tube Q L3 And a current source I T2 Wherein:
NPN tube Q L1 The base electrode of the NPN transistor Q is connected with the differential mode output positive end of the limiting amplifier L2 The base electrode of the NPN tube Q is connected with the differential mode output negative terminal of the limiting amplifier L3 The base electrode of the limiting amplifier is connected with the common mode output end of the limiting amplifier;
NPN tube Q L1 Emitter, NPN tube Q of (2) L2 Emitter, NPN tube Q of (2) L3 Emitter and current source I of (c) T2 Is connected with the upper end of the connecting rod; current source I T2 The lower end of the lower part is grounded; NPN tube Q L1 Collector and NPN tube Q L2 The collector of (C) is connected with the point D 'which is the differential mode output end of the rectifier, and the current of the point D' is I ID The method comprises the steps of carrying out a first treatment on the surface of the NPN tube Q L3 The collector of (2) is the common mode output end of the rectifier, and the current is I CM 。
4. A method according to claim 3, wherein the differential transferLogarithmic amplifier with end transimpedance structure, characterized in that NPN tube Q L3 The emitter area of (2) is NPN tube Q L1 And NPN tube Q L2 2 times the emitter area, the following relationship is obtained:
I S3 ＝2I S2 ＝2I S1
wherein I is S1 ，I S2 ，I S3 Representing NPN tube Q L1 NPN tube Q L2 NPN tube Q L3 Is proportional to the emitter area of the transistor.
5. The logarithmic amplifier of claim 1, wherein the differential to single ended transimpedance output structure comprises a BUFFER, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, NPN tube Q1, NPN tube Q2, NPN tube Q4, NPN tube Q5, NPN tube Q6, NPN tube Q7, and NPN tube Q8, wherein:
the upper end of the resistor R1 is connected with a power supply VS; the lower end of the resistor R1 is connected with the upper end of the resistor R5 and the collector of the NPN tube Q8 at the point A, and an independent branch line extending from the point A is connected with the output current of the negative end of the rectifier;
the upper end of the resistor R2 is connected with a power supply VS; the lower end of the resistor R2 is connected with the upper end of the resistor R6 at the point B, and an independent branch line extending from the point B is connected with the output current of the positive end of the rectifier;
the upper end of the resistor R3 is connected with the emitter of the NPN tube Q8 at the point C, and the point C is connected with the input end BF of the BUFFER BUFFER IN The method comprises the steps of carrying out a first treatment on the surface of the The lower end of the resistor R3 is grounded; the output end of the BUFFER BUFFER is the output end V of the logarithmic amplifier OUT ；
The upper end of the resistor R4 is connected with a power supply VS; the lower end of the resistor R4 is connected with the emitter of the NPN tube Q6;
the lower end of the resistor R5 is connected with the emitter of the NPN tube Q4;
the lower end of the resistor R6 is connected with the emitter of the NPN tube Q5;
the collector of the NPN tube Q1 is connected with the collector of the NPN tube Q4 and the base of the NPN tube Q8, the base of the NPN tube Q1 is connected with the base of the NPN tube Q2, the collector of the NPN tube Q2 and the collector of the NPN tube Q5, and the emitter of the NPN tube Q1 is grounded;
the emitter of the NPN tube Q2 is grounded;
the base electrode of the NPN tube Q4, the base electrode of the NPN tube Q5, the base electrode of the NPN tube Q6, the collector electrode of the NPN tube Q6 and the collector electrode of the NPN tube Q7 are connected at a point D;
the base of NPN tube Q7 is connected with BIAS voltage BIAS, and the emitter of NPN tube Q7 is grounded.
6. The logarithmic amplifier of claim 5, wherein the BUFFER comprises a PNP transistor Q9, a PNP transistor Q10, a PNP transistor Q11, a PNP transistor Q12, a NPN transistor Q13, a NPN transistor Q14, a PNP transistor Q15, a PNP transistor Q16, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a current source I1, and a current source I2, wherein:
the base electrode of the PNP tube Q9 is the input end of the BUFFER BUFFER; the collector of the PNP tube Q9 is connected with the upper end of the resistor R7 and the emitter of the NPN tube Q14; the emitter of the PNP tube Q9 is connected with the lower end of the current source I1 and the emitter of the PNP tube Q10;
the base electrode of the PNP tube Q10 is connected with the lower end of the resistor R9 at the point E; the collector of the PNP tube Q10 is connected with the upper end of the resistor R8 and the emitter of the NPN tube Q13;
the base electrode of the PNP tube Q11 is connected with the collector electrode of the PNP tube Q11, the base electrode of the PNP tube Q12 and the collector electrode of the NPN tube Q13; the emitter of the PNP tube Q11, the upper end of the current source I1, the emitter of the PNP tube Q12, the upper end of the current source I2 and the emitter of the PNP tube Q16 are all connected to a power supply VCC;
the collector of the PNP tube Q12 is connected with the collector of the NPN tube Q14, the base of the PNP tube Q15 and the left end of the capacitor C1;
the base electrode of the NPN tube Q13 is connected with the base electrode of the NPN tube Q14 and the reference voltage VB;
the emitter of the PNP tube Q15 is connected with the lower end of the current source I2 and the base of the PNP tube Q16; the collector of the PNP tube Q15 is grounded;
the collector of the PNP tube Q16 is connected with the upper end of the resistor R9;
the lower end of the resistor R9, the right end of the capacitor C1 and the upper end of the resistor R10 are connected at the point E, and the point E is the output end of the BUFFER BUFFER;
the lower end of the resistor R7, the lower end of the resistor R8 and the lower end of the resistor R10 are grounded.
7. The logarithmic amplifier of claim 5, wherein the resistance of resistor R2 is the same as the resistance of resistor R1.
8. The logarithmic amplifier of claim 5, wherein the output current versus output voltage for the differential to single ended transimpedance output structure is:
V OUT ＝(I OUTP -I OUTM )·R 3
wherein R is 3 Represents the resistance value of the resistor R3, I OUTM Representing the sum of the output currents at the differential mode outputs of all rectifiers, I OUTP Representing the sum of the output currents at the common mode outputs of all rectifiers, V OUT Representing the logarithmic amplifier output voltage.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117526946A (en) * | 2024-01-02 | 2024-02-06 | 上海安其威微电子科技有限公司 | Logarithmic conversion circuit and chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117526946A (en) * | 2024-01-02 | 2024-02-06 | 上海安其威微电子科技有限公司 | Logarithmic conversion circuit and chip |
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