CN116860096B - RSTN reset pin function multiplexing control method and circuit of MCU chip - Google Patents
RSTN reset pin function multiplexing control method and circuit of MCU chip Download PDFInfo
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Abstract
The invention discloses a multiplexing control method and a circuit for the functions of RSTN reset pins of an MCU chip, wherein a mode control circuit is additionally arranged on the existing RSTN reset pins of the MCU chip, the pulse width of low-level pulses input on the RSTN reset pins is identified through the mode control circuit, the RSTN reset pins are enabled to work in a C2CK debugging clock input mode, a chip test mode enabling signal generation mode or a reset signal input mode according to different identified pulse widths, thereby realizing the multifunctional multiplexing of the RSTN reset pins, saving the number of IO pins of the MCU chip, improving the integration level and reducing the chip cost. In addition, the mode control circuit is completely composed of the digital circuit, no extra power consumption is generated, the circuit structure is simple, and the occupied chip area is small.
Description
Technical Field
The invention belongs to the field of electronic circuits, and particularly relates to a multiplexing control method and circuit for RSTN reset pin functions of an MCU chip.
Background
At present, electronic products are developing towards high integration and low cost, and MCU chips are used as control brains of the electronic products to integrate more peripheral functions so as to simplify the complexity of the whole electronic product system and reduce the product cost. Integration of more peripheral functions inevitably leads to an increase in complexity of the MCU chip system, and the number of I/O pins required increases sharply. Therefore, the functional utilization rate of the I/O pins is improved, the multiplexing functional potential of each pin is fully excavated, the number of the I/O pins of the MCU chip is reduced, and the integration level of the chip is improved.
The working principle of the RSTN reset pin of the traditional MCU chip is shown in fig. 1, a Schmitt trigger is arranged in the MCU chip, the RSTN reset pin of the MCU chip is connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is connected to a CPU core reset control circuit of the MCU chip. Under the normal working condition of the MCU chip, the RSTN reset pin is input at a high level; when the MCU chip needs to be reset, only one low-level pulse is input to the RSTN reset pin, accidental shake is eliminated after the low-level pulse signal is filtered by the Schmitt trigger, and finally a pure low-level pulse RSTN_CORE signal is generated to the CPU CORE reset control circuit to reset the MCU chip. The RSTN reset pin of the structure can only realize the single function of inputting a chip reset signal.
The traditional RSTN reset pin can only realize the single function of resetting the MCU chip, and the MCU chip needs test mode signal input in the production stage for enabling the MCU chip to enter a test mode; in the normal use process of the MCU chip, the clock signal input needs to be debugged, so that operations such as online debugging and the like are performed on the MCU chip. The test mode signal input and the debug clock signal input need to occupy two additional I/O pins, so that the number of pins of the MCU chip is increased, the integration level is reduced, and the cost is increased.
Disclosure of Invention
The invention aims to provide a multiplexing control method for the RSTN reset pin function of an MCU chip, which can control the RSTN reset pin of the MCU chip to realize three functions of C2CK debugging clock signal input, test mode control enabling signal generation and reset signal input, thereby saving the number of I/O pins of the MCU chip, improving the integration level and reducing the chip cost.
The invention further aims to provide a RSTN reset pin function multiplexing control circuit of the MCU chip, which can realize that the RSTN reset pin of the MCU chip has three functions of C2CK debugging clock signal input, test mode control enabling signal generation and reset signal input, thereby saving the number of I/O pins of the MCU chip, improving the integration level and reducing the chip cost.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a mode control circuit is additionally arranged in the MCU chip, the pulse width of low-level pulses input by the RSTN reset pin of the MCU chip is identified through the mode control circuit, and the RSTN reset pin correspondingly works in a C2CK debugging clock input mode, a chip test mode enabling signal generation mode or a reset signal input mode according to different identified pulse widths, so that the RSTN reset pin is multifunctional in multiplexing.
Further, according to the RSTN reset pin function multiplexing control method of the MCU chip, when the duration of the pulse width of the low-level pulse input by the RSTN reset pin is smaller than t1, the RSTN reset pin works in a C2CK debugging clock input mode; when the pulse width duration of the low level pulse input by the RSTN reset pin is greater than t1 and less than t2, wherein t2> t1, the RSTN reset pin works in a chip test mode enabling signal generating mode; the RSTN reset pin operates in a reset signal input mode when a pulse width duration of a low level pulse input by the RSTN reset pin is greater than t 2.
The RSTN reset pin function multiplexing control circuit of the MCU chip comprises a Schmitt trigger and a mode control circuit, wherein the input end of the Schmitt trigger is connected with the RSTN reset pin of the MCU chip, the output end of the Schmitt trigger is respectively connected with the input end of the mode control circuit and the C2CK debugging control circuit of the MCU chip, and the output end of the mode control circuit is respectively connected with the test mode control circuit and the CPU core reset control circuit of the MCU chip; the clock reference input end of the mode control circuit is connected with a system clock signal of the MCU chip, and the reset end of the mode control circuit is connected with a power-on reset signal of the MCU chip; the mode control circuit is used for identifying the pulse width of the low-level pulse input on the RSTN reset pin of the MCU chip and correspondingly outputting a chip test mode enabling signal or a CPU core reset signal to the test mode control circuit or the CPU core reset control circuit of the MCU chip according to the identified different pulse widths, so that the RSTN reset pin of the MCU chip is multiplexed in a multifunctional mode.
The mode control circuit comprises an AND gate I, a counter I, an OR gate I, an AND gate II, a counter II, an OR gate II, a delay unit and a test mode detector;
the first and second AND gates have one input end connected to the system clock signal of the MCU chip, the first and second AND gates have another input end connected to the first and second counter output ends, and the first and second AND gates have output ends connected to the first and second counter input ends, respectively, so that the first AND gate and the first counter form a self-closing counter, and the second AND gate and the second counter form another self-closing counter; the counting time t2 of the counter II is longer than the counting time t1 of the counter I;
the input end of the delay unit is connected with the output end of the Schmitt trigger, the output end of the delay unit is respectively connected with one input end of the first or second or gate, the other input end of the first or second or gate is respectively connected with a power-on reset signal of the MCU chip, and the output ends of the first or second or gate are respectively connected with the reset end of the first counter and the reset end of the second counter;
the output end of the first counter is connected with one input end of the test mode detector, the output end of the second counter is respectively connected with a CPU core reset control circuit of the MCU chip and the other input end of the test mode detector, the control end of the test mode detector is connected with the output end of the Schmitt trigger, the reset end of the test mode detector is connected with a power-on reset signal of the MCU chip, and the output end of the test mode detector is connected with the test mode control circuit of the MCU chip.
The test mode detector comprises an inverter, an AND gate III and a D trigger, wherein the output end of the counter I is connected to the input end of the inverter, the output end of the inverter is connected with one input end of the AND gate III, the other input end of the AND gate III is connected with the output end of the counter II, the output end of the AND gate III is connected with the input end of the D trigger, the control end of the D trigger is connected with the output end of the Schmitt trigger, the reset end of the trigger is connected with a power-on reset signal of the MCU chip, and the output end of the trigger is connected with a test mode control circuit of the MCU chip.
After the technical scheme is adopted, the mode control circuit is additionally arranged on the existing RSTN reset pin of the MCU chip, the pulse width of low-level pulses input on the RSTN reset pin is identified through the mode control circuit, the RSTN reset pin is enabled to work in a C2CK debugging clock input mode, a chip test mode enabling signal generation mode or a reset signal input mode according to different identified pulse widths, and therefore the RSTN reset pin multifunctional multiplexing is achieved, the number of IO pins of the MCU chip is saved, the integration level is improved, and the chip cost is reduced.
In addition, in the invention, the mode control circuit is completely composed of a digital circuit, no additional static power consumption (only small dynamic power consumption) is generated, and the circuit has a simple structure and occupies small chip area.
Drawings
FIG. 1 is a functional block diagram of a reset pin of a conventional MCU chip RSTN;
FIG. 2 is a functional block diagram of a reset pin of an MCU chip RSTN in the present invention;
FIG. 3 is a functional block diagram of the mode controller of FIG. 2;
FIG. 4 is a functional block diagram of the test pattern detector of FIG. 3;
FIG. 5 is a timing diagram illustrating operation of the RSTN reset pin in the C2CK debug clock input mode in accordance with the present invention;
FIG. 6 is a timing diagram illustrating operation of the RSTN reset pin in a chip test mode enable signal generation mode in accordance with the present invention;
FIG. 7 is a timing diagram illustrating operation of the RSTN reset pin of the present invention in a reset signal input mode.
Detailed Description
According to the RSTN reset pin function multiplexing control method of the MCU chip, a mode control circuit is additionally arranged in the MCU chip, the pulse width of low-level pulses input by the RSTN reset pin of the MCU chip is identified through the mode control circuit, and the RSTN reset pin correspondingly works in a C2CK debugging clock input mode, a chip test mode enabling signal generation mode or a reset signal input mode according to different identified pulse widths, so that the RSTN reset pin multifunctional multiplexing is realized.
Further, according to the RSTN reset pin function multiplexing control method of the MCU chip, when the duration of the pulse width of the low-level pulse input by the RSTN reset pin is smaller than t1, the RSTN reset pin works in a C2CK debugging clock input mode; when the pulse width duration of the low level pulse input by the RSTN reset pin is greater than t1 and less than t2, wherein t2> t1, the RSTN reset pin works in a chip test mode enabling signal generating mode; the RSTN reset pin operates in a reset signal input mode when a pulse width duration of a low level pulse input by the RSTN reset pin is greater than t 2.
As shown in FIG. 2, the RSTN reset PIN function multiplexing control circuit of the MCU chip comprises a Schmitt trigger and a mode control circuit, wherein the input end of the Schmitt trigger is connected with the RSTN reset PIN of the MCU chip, the output end of the Schmitt trigger is respectively connected with the input end of the mode control circuit and the C2CK debugging control circuit of the MCU chip, and the RSTN_PIN signal input from the exterior of the MCU chip is filtered through the Schmitt trigger to obtain a purer C2CK (RSTN) signal. And C2 communication comprises clock signals C2CK and data signals C2D, and when an operator sends a communication instruction to the MCU chip through the upper computer according to a corresponding C2 communication protocol, the C2CK signals output by the Schmidt trigger are used as debugging clock input signals of the MCU chip and are sent to a C2CK debugging control circuit of the MCU chip for debugging the clock signal input.
The output end of the mode control circuit is respectively connected to the test mode control circuit and the CPU core reset control circuit of the MCU chip; the clock reference input end of the mode control circuit is connected with a system clock signal (CLK_IN) of the MCU chip, and the reset end of the mode control circuit is connected with a power-on reset signal (POR) of the MCU chip. The mode control circuit is used for identifying the pulse width of the low-level pulse input on the RSTN reset pin of the MCU chip and correspondingly outputting a chip test mode enabling signal or a CPU core reset signal to the test mode control circuit or the CPU core reset control circuit of the MCU chip according to the identified different pulse widths, so that the RSTN reset pin of the MCU chip is multiplexed in a multifunctional mode.
In the invention, the mode control circuit can be realized by adopting various circuits, so long as the pulse width of the low-level pulse input on the RSTN reset pin of the MCU chip can be identified, and the chip test mode enabling signal or the CPU core reset signal can be correspondingly output to the test mode control circuit or the CPU core reset control circuit of the MCU chip according to the identified different pulse widths.
As a preferred embodiment, as shown in fig. 3, the mode control circuit includes an and gate first, a counter first, an or gate first, an and gate second, a counter second, an or gate second, a delay unit and a test mode detector;
the first and second AND gates have one input end connected to the system clock signal (CLK_IN) of the MCU chip, and the first and second AND gates have another input end connected to the output end of the first counter and the output end of the second counter, and the first and second AND gates have output ends connected to the input ends of the first and second counters, respectively, so that the first AND gate and the first counter form a self-closing counter, and the second AND gate and the second counter form another self-closing counter; the counting time t2 of the counter II is longer than the counting time t1 of the counter I;
the input end of the delay unit is connected with the output end of the Schmitt trigger, the output end of the delay unit is respectively connected with one input end of the first or second or gate, the other input end of the first or second or gate is respectively connected with a power-on reset signal (POR) of the MCU chip, and the output ends of the first or second or gate are respectively connected with the reset end of the first counter and the reset end of the second counter;
the output end of the first counter is connected with one input end of the test mode detector, the output end of the second counter is respectively connected with a CPU core reset control circuit of the MCU chip and the other input end of the test mode detector, the control end of the test mode detector is connected with the output end of the Schmitt trigger, the reset end of the test mode detector is connected with a power-on reset signal (POR) of the MCU chip, and the output end of the test mode detector is connected with the test mode control circuit of the MCU chip.
As shown in fig. 4, the test mode detector includes an inverter, an and gate three and a D flip-flop, where an output end of the first counter is connected to an input end of the inverter, an output end of the inverter is connected to one input end of the third and gate, another input end of the third and gate is connected to an output end of the second counter, an output end of the third and gate is connected to an input end D of the D flip-flop, a control end of the D flip-flop is connected to an output end of the schmitt trigger, a reset end R of the D flip-flop is connected to a power-on reset signal of the MCU chip, and an output end Q of the D flip-flop is connected to a test mode control circuit of the MCU chip.
IN the invention, the CLK_IN signal is an MCU system clock signal used for providing timing reference for the first counter and the second counter IN the mode controller; the POR signal is a power-on reset signal of the MCU chip and is used for providing a power-on reset function for the mode controller, so that the mode controller can enter a preset state (avoid entering an uncertain state) after the MCU chip is powered on. When the MCU chip is powered on and reset, the POR signal is high level, and when the MCU chip works normally, the POR signal is low level. And the reset ends of the first counter and the second counter are both reset at high level. And the reset end of the D trigger is reset at a high level.
The working principle of the invention is as follows: when the low-level pulse width of the RSTN_PIN signal input by the RSTN reset PIN of the MCU chip is smaller (about 5 mu s), the RSTN_PIN signal is used as the debugging clock input signal of the MCU chip, and the CPU CORE reset signal RSTN_core and the chip TEST MODE enabling signal TEST_MODE_EN are not triggered in the state; when the low level pulse of the RSTN_PIN signal is of a medium pulse width (about 20 us), the RSTN reset PIN of the MCU chip triggers the TEST_MODE_EN signal to be high, but does not trigger the RSTN_CORE signal, and the MCU chip enters a TEST MODE; when the low level pulse width of the RSTN_PIN signal is larger (more than 100 us), the RSTN reset PIN of the MCU chip triggers the RSTN_CORE signal to generate a low level pulse, but does not trigger the TEST_MODE_EN signal, and the MCU chip enters a reset state.
Specifically, when the RSTN signal output by the schmitt trigger is at a high level IN the normal operating state of the MCU chip, the first or second or gate outputs a high level to the reset terminals of the first or second counter, the first or second counter is IN a reset state, and the first or second counter output a full_dly1 signal and the second counter output a full_dly2 signal (rstn_core signal) are reset to a high level, and at this time, the first or second and gate inputs enable to clk_in.
When the low level pulse of the RSTN signal comes, the POR signal is at a low level, the or gate one and the or gate two output low levels to the reset terminals of the counter one and the counter two respectively, and the counter one and the counter two are reset to enter a counting state, as described above, the counter one needs time t1, the counter two needs time t2, and t2> t1.
The TEST MODE detector determines whether to set the test_mode_en signal high by detecting the states of the FALL_DLY1 signal and the FALL_DLY2 signal, and the test_mode_en signal is set low by the POR signal after the MCU chip is first powered on and reset.
If the duration of the low pulse width of the RSTN signal is < t1, then the high pulse of the RSTN signal is encountered again when neither of the first nor second counters is full, so that both of the first and second counters enter the reset state again, and the FALL_DLY1 signal and the FALL_DLY2 signal (RSTN_CORE signal) remain high without generating low pulses, i.e., without triggering the CPU CORE reset control circuitry of the MCU chip. And the inverter outputs a low level, the AND gate outputs a low level to the D trigger, and the TEST_MODE_EN signal output by the D trigger is a low level and does not trigger a TEST MODE control circuit of the MCU chip.
If the low pulse width duration of the RSTN signal is greater than t1 and less than t2, then the counter-one will be full after a time delay of t1, the FALL_DLY1 signal output by the counter-one will be low, at which time the AND gate-one pair of CLK_IN signal inputs are disabled, the counter-one stops counting, and the FALL_DLY1 signal remains low. At this point the second counter is not fully charged and the FALL_DLY2 signal (RSTN_CORE signal) remains high without generating a low pulse, i.e., without triggering the CPU CORE reset control circuitry of the MCU chip. The D flip-flop is a rising edge trigger circuit, and the input signal D can be transmitted to the output terminal Q only at the rising edge time of the RSTN signal. Thus, when the low level pulse of the RSTN signal comes, at the rising edge time of the RSTN signal, the D flip-flop will detect the states of the fail_dly 1 signal and the fail_dly 2 signal, if the fail_dly 1 signal is low and the fail_dly 2 signal is high at this time, the inverter outputs a high level to the and gate three, which outputs a high level to the D flip-flop, the D flip-flop outputs a high level, the test_mode_en signal will be set high, the MCU chip enters the TEST MODE, otherwise the test_mode_en signal remains low all the time. Until the RSTN signal goes high and is delayed by t3 (t 3 is the delay time of the delay unit, t3 is mainly determined by the inter-chip dispersion of the production process and the mismatch of the trace length of the circuit board, and the effect is to ensure that the rising edges of the FALL_DLY1 signal and the FALL_DLY2 signal are later than the rising edge of the RSIN signal, so that the t3 time is very short, generally a few ns is required), and then the FALL_DLY1 signal is set high due to the reset of the first counter, and the FALL_DLY2 signal is also set high due to the reset of the second counter.
If the low pulse width duration of the RSTN signal is greater than t2, then the first counter is full, the FALL_DLY1 signal remains low, the second counter is also full, and the FALL_DLY2 signal (RSTN_CORE signal) remains low, at which point the MCU chip will enter a reset state. And the AND gate three outputs a low level, and the TEST_MODE_EN signal output by the D trigger is a low level, so that the TEST MODE is not triggered.
In the present invention, the operation timing sequence of the multiplexing control of the RSTN reset pin function of the MCU chip is shown in fig. 5 to 7, and the counting time t2 of the counter two is adjusted to make t2=kχt1 (k > 1).
FIG. 5 is a timing diagram corresponding to the operation of the RSTN reset pin in the C2CK clock signal input mode, where after the MCU chip is first powered on reset, the output of the power on reset control circuit will generate a segment of high level reset pulse, and then remain low level. That is, after the MCU chip is first powered on and reset, the first counter and the second counter are reset by the POR signal due to the high level reset pulse (POR signal), the fail_dly 1 signal and the fail_dly 2 signal are reset to the high level, and the test_mode_en signal is reset to the low level by the POR signal; when the rstn_pin signal is a high-speed clock signal (the debug clock signal is typically a high-speed clock signal), the fall_dly1 signal and the fall_dly2 signal remain high because the low-level pulse width of the high-speed clock signal is very short (less than t1 and t2, typically around 5 μs), and thus do not trigger the rst_core (fall_dly 2) signal and the test_mode_en signal.
FIG. 6 is a timing diagram corresponding to an operation of the RSTN reset PIN in a chip test mode enable signal generation mode, wherein when the pulse width of the low level pulse of the RSTN_PIN signal is greater than t1 and less than t2, the FALL_DLY1 signal will generate the low level pulse while the FALL_DLY2 signal remains high; the D flip-flop is a rising edge trigger circuit, and the input signal D can be transmitted to the output terminal Q only at the rising edge time of the RSTN signal, so that the TEST_MODE_EN signal is set high when the rising edge time of the RSTN signal comes, and the RSTN_CORE (FALL_DLY2) signal is always kept high, so that the MCU chip cannot enter the reset state. After the MCU chip enters the TEST MODE, a corresponding mechanism is needed to enable the MCU chip to exit the TEST MODE and enter the normal working MODE, and when the MCU chip works in the TEST MODE, a low-level pulse is input through an RSTN reset pin, so that the pulse width of the low-level pulse is smaller than t1 (as no operator gives a communication instruction to the MCU chip through an upper computer, the low-level pulse cannot be mistaken for a debugging clock input signal), the FALL_DLY1 signal and the FALL_DLY2 signal are both high-level at the rising edge moment of the low-level pulse, the TEST_MODE_EN signal is set low, and the chip TEST MODE is released and enters the normal working MODE.
FIG. 7 is a timing diagram corresponding to the operation of the RSTN reset PIN in the reset signal input mode, when the pulse width of the low level pulse of the RSTN_PIN signal is greater than t1 and t2, both the FALL_DLY1 signal and the FALL_DLY2 signal will generate the low level pulse, and the RSTN_CORE (FALL_DLY2) signal will enter the reset state when the low level pulse is on; the test_mode_en signal remains low all the time, so the chip does not enter TEST MODE.
According to the RSTN reset pin function multiplexing control method and circuit of the MCU chip, the mode control circuit is additionally arranged on the existing RSTN reset pin of the MCU chip, the pulse width of low-level pulses input on the RSTN reset pin is identified through the mode control circuit, the RSTN reset pin is enabled to work in a C2CK debugging clock input mode, a chip test mode enabling signal generation mode or a reset signal input mode according to different identified pulse widths, and therefore RSTN reset pin multifunctional multiplexing is achieved, the number of IO pins of the MCU chip is saved, the integration level is improved, and the chip cost is reduced.
In addition, in the invention, the mode control circuit is completely composed of a digital circuit, no additional static power consumption (only small dynamic power consumption) is generated, and the circuit has a simple structure and occupies small chip area.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the technical scope of the present invention, so that any minor modifications, equivalent changes and modifications made to the above examples according to the technical principles of the present invention are within the scope of the technical solutions of the present invention.
Claims (3)
1. The RSTN reset pin function multiplexing control method of the MCU chip is characterized in that a Schmitt trigger is arranged in the MCU chip, and the RSTN reset pin of the MCU chip is connected to the input end of the Schmitt trigger, and the method is characterized in that: a mode control circuit is additionally arranged in the MCU chip, the output end of the Schmitt trigger is respectively connected with the input end of the mode control circuit and the C2CK debugging control circuit of the MCU chip, the pulse width of low-level pulses input by an RSTN reset pin of the MCU chip is identified through the mode control circuit, and the RSTN reset pin correspondingly works in a C2CK debugging clock input mode, a chip test mode enabling signal generation mode or a reset signal input mode according to different identified pulse widths, so that the RSTN reset pin is multifunctional and multiplexing is realized;
the mode control circuit comprises an AND gate I, a counter I, an OR gate I, an AND gate II, a counter II, an OR gate II, a delay unit and a test mode detector; the first and second AND gates have one input end connected to the system clock signal of the MCU chip, the first and second AND gates have another input end connected to the first and second counter output ends, and the first and second AND gates have output ends connected to the first and second counter input ends, respectively, so that the first AND gate and the first counter form a self-closing counter, and the second AND gate and the second counter form another self-closing counter; the counting time t2 of the counter II is longer than the counting time t1 of the counter I; the input end of the delay unit is connected with the output end of the Schmitt trigger, the output end of the delay unit is respectively connected with one input end of the first or second or gate, the other input end of the first or second or gate is respectively connected with a power-on reset signal of the MCU chip, and the output ends of the first or second or gate are respectively connected with the reset end of the first counter and the reset end of the second counter; the output end of the first counter is connected with one input end of the test mode detector, the output end of the second counter is respectively connected with a CPU core reset control circuit of the MCU chip and the other input end of the test mode detector, the control end of the test mode detector is connected with the output end of the Schmitt trigger, the reset end of the test mode detector is connected with a power-on reset signal of the MCU chip, and the output end of the test mode detector is connected with the test mode control circuit of the MCU chip;
the test mode detector comprises an inverter, an AND gate III and a D trigger, wherein the output end of the counter I is connected to the input end of the inverter, the output end of the inverter is connected with one input end of the AND gate III, the other input end of the AND gate III is connected with the output end of the counter II, the output end of the AND gate III is connected with the input end of the D trigger, the control end of the D trigger is connected with the output end of the Schmitt trigger, the reset end of the D trigger is connected with a power-on reset signal of the MCU chip, and the output end of the D trigger is connected with a test mode control circuit of the MCU chip.
2. The method for multiplexing control of the RSTN reset pin function of the MCU chip according to claim 1, wherein: when the pulse width duration of the low-level pulse input by the RSTN reset pin is smaller than t1, the RSTN reset pin works in a C2CK debugging clock input mode; when the pulse width duration of the low level pulse input by the RSTN reset pin is greater than t1 and less than t2, wherein t2> t1, the RSTN reset pin works in a chip test mode enabling signal generating mode; the RSTN reset pin operates in a reset signal input mode when a pulse width duration of a low level pulse input by the RSTN reset pin is greater than t 2.
3. The RSTN reset pin function multiplexing control circuit of the MCU chip, performing the RSTN reset pin function multiplexing control method of the MCU chip as defined in claim 1, wherein: the output end of the mode control circuit is respectively connected to the test mode control circuit and the CPU core reset control circuit of the MCU chip; the clock reference input end of the mode control circuit is connected with a system clock signal of the MCU chip, and the reset end of the mode control circuit is connected with a power-on reset signal of the MCU chip; the mode control circuit is used for identifying the pulse width of the low-level pulse input on the RSTN reset pin of the MCU chip and correspondingly outputting a chip test mode enabling signal or a CPU core reset signal to the test mode control circuit or the CPU core reset control circuit of the MCU chip according to the identified different pulse widths, so that the RSTN reset pin of the MCU chip is multiplexed in a multifunctional mode.
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