CN116864445A - Forming method of trench isolation structure - Google Patents
Forming method of trench isolation structure Download PDFInfo
- Publication number
- CN116864445A CN116864445A CN202310850629.4A CN202310850629A CN116864445A CN 116864445 A CN116864445 A CN 116864445A CN 202310850629 A CN202310850629 A CN 202310850629A CN 116864445 A CN116864445 A CN 116864445A
- Authority
- CN
- China
- Prior art keywords
- isolation
- layer
- trench
- substrate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 132
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 35
- 238000000151 deposition Methods 0.000 claims abstract description 30
- 238000004544 sputter deposition Methods 0.000 claims abstract description 29
- 230000008021 deposition Effects 0.000 claims abstract description 22
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000007517 polishing process Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 129
- 239000000758 substrate Substances 0.000 claims description 56
- 150000004767 nitrides Chemical class 0.000 claims description 26
- 239000007789 gas Substances 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 5
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 229910000077 silane Inorganic materials 0.000 claims description 2
- 238000005429 filling process Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 229910052710 silicon Inorganic materials 0.000 description 22
- 239000010703 silicon Substances 0.000 description 22
- 239000010408 film Substances 0.000 description 8
- 238000012876 topography Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The application provides a method for forming a trench isolation structure. The method comprises the following steps: a groove etching step, an isolation material deposition step, an isolation layer etching step and a sputtering step; repeating the isolation material deposition step, the isolation layer etching step and the sputtering step until the isolation material is filled in the groove, and the flatness of the isolation layer at the corner meets a preset flatness threshold value; and a planarization step. According to the application, by improving the trench filling process and adopting a mode of deposition, etching and sputtering, on the basis of ensuring the filling capability with a larger depth-to-width ratio, the flatness of the isolation layer at the corner of the trench is effectively improved, the uniformity of the surface of the film is improved, the risk and challenges of the subsequent chemical mechanical polishing process are reduced, and the product competitiveness is improved.
Description
Technical Field
The present application relates to the field of semiconductor manufacturing, and in particular, to a method for forming a trench isolation structure.
Background
In semiconductor device fabrication, as the integration of semiconductor devices increases, shallow trench isolation (Shallow Trench Isolation, STI) technology is widely used in integrated circuit fabrication. Compared with the local oxidation isolation (Local Oxidation of Silicon, LOCOS) technology, the shallow slot isolation technology occupies a smaller area of a silicon wafer, and can improve the integration level of devices on unit silicon wafers.
Shallow trench isolation techniques are typically performed by forming and patterning a nitride layer on a silicon substrate, which acts as a hard mask; then carrying out an etching process with a preset depth on the silicon substrate to form a groove on the silicon substrate; thereafter, a Deposition (Dep) isolation layer is filled in the trench and an isolation structure is formed by a Chemical Mechanical Polishing (CMP) process for isolation from the silicon substrate.
Please refer to fig. 1, which is a schematic diagram of a trench isolation structure formed in a conventional filling mode. As shown in fig. 1, a patterned nitride layer 11 is formed on a silicon substrate 10, and a trench 101 is formed by performing an etching process to a predetermined depth on the silicon substrate 10 based on the nitride layer 11 as a hard mask, and an isolation layer 13 is filled in the trench 101. Since the trench 101 has a certain Aspect Ratio (AR), when the trench 101 is filled with the deposited isolation layer 13, the isolation layer 13 forms a protrusion (Overhang) 131 at the upper corner 102 of the trench 101, and the topography of the protrusion 131 may seriously affect the surface topography of the film, which brings risks and challenges to the subsequent chemical mechanical polishing process.
Disclosure of Invention
The technical problem to be solved by the application is to provide the forming method of the trench isolation structure, which can effectively improve the flatness of the isolation layer at the corner of the trench on the basis of meeting the filling capability, improve the uniformity of the surface of the film, reduce the risk and challenges of the subsequent chemical mechanical polishing process and improve the competitiveness of the product.
In order to solve the above problems, the present application provides a method for forming a trench isolation structure, the method comprising the steps of: a groove etching step, namely etching a substrate by taking a preset mask plate as a mask, and forming a groove on the substrate; an isolation material deposition step, namely depositing an isolation material on the surface of the substrate and in the groove to form an isolation layer, wherein a bulge is formed at the corner of the groove, which is close to the preset mask plate, of the isolation layer; an isolation layer etching step, namely etching the isolation layer at the corner to planarize the bulge; sputtering, namely introducing sputtering gas to bombard the isolation layer at the corner so as to further planarize the bulge; repeating the isolation material deposition step, the isolation layer etching step and the sputtering step until the isolation material is filled in the groove, and the flatness of the isolation layer at the corner meets a preset flatness threshold value; and flattening the isolation layer by adopting a flattening process so as to form the trench isolation structure in the trench.
In some embodiments, in the sputtering step, the sputtering gas is selected from at least one of argon, helium, hydrogen.
In some embodiments, the trench isolation structure is formed in a semiconductor substrate, or in an interlayer dielectric layer, or in an inter-metal dielectric layer.
According to the technical scheme, through improving the trench filling process and adopting the modes of deposition, etching and sputtering, the flatness of the isolation layer at the corner of the trench is effectively improved, the uniformity of the surface of the film is improved, the risk and challenges of the subsequent chemical mechanical polishing process are reduced, and the product competitiveness is improved on the basis of ensuring the filling capacity with a large depth-to-width ratio.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic illustration of a trench isolation structure formed in a conventional fill mode;
FIG. 2 is a flowchart illustrating a method for forming a trench isolation structure according to an embodiment of the present application;
fig. 3A to 9 are schematic views of a device structure formed by main steps of a method for forming a trench isolation structure according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 2 to fig. 9 together, fig. 2 is a flowchart of a method for forming a trench isolation structure according to an embodiment of the present application, and fig. 3A to fig. 9 are schematic device structures formed by main steps of the method for forming a trench isolation structure according to an embodiment of the present application.
As shown in fig. 2, the method for forming the trench isolation structure according to the present embodiment includes the following steps: s1, etching a groove, namely etching a substrate by taking a preset mask plate as a mask, and forming a groove on the substrate; s2, an isolation material deposition step, namely depositing an isolation material on the surface of the substrate and in the groove to form an isolation layer, wherein a bulge is formed at the corner of the groove, which is close to the preset mask plate, of the isolation layer; s3, etching the isolation layer at the corner to planarize the protrusion; s4, sputtering step, namely, introducing sputtering gas to bombard the isolation layer at the corner so as to planarize the protrusion further; s5, repeating the isolation material deposition step, the isolation layer etching step and the sputtering step until the isolation material is filled in the groove, and the flatness of the isolation layer at the corner meets a preset flatness threshold value; s6, flattening the isolation layer by adopting a flattening process so as to form the groove isolation structure in the groove.
Referring to step S1 and fig. 3C, a trench etching step etches the substrate 30 using a predetermined mask as a mask, and a trench 301 is formed on the substrate 30.
In some embodiments, the trench etching step is further formed using the steps of: (1) Providing a substrate 30, and forming a nitride layer 311 on the surface of the substrate 30, as shown in fig. 3A; (2) Etching the nitride layer 311 with the patterned photoresist layer 312 as a mask to form a patterned nitride layer 311, as shown in fig. 3B; (3) And removing the remaining patterned photoresist layer 312, and etching the substrate 30 by using the patterned nitride layer 311 as the preset mask to form the trench 301, as shown in fig. 3C.
In some embodiments, the base 30 may be a semiconductor substrate, or an interlayer dielectric layer (ILD), or an inter-metal dielectric layer (IMD). The trench 301 formed on the substrate 30 may be used for isolation between devices on the substrate 30 by filling to form a trench isolation structure. The semiconductor substrate may include a Silicon (Si) substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon-On-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, or the like; the semiconductor substrate may also be a stacked structure, such as a silicon/silicon germanium stack or the like. In this embodiment, a substrate 30 is taken as a silicon substrate, and a shallow trench isolation (Shallow Trench Isolation, STI) structure is formed in the silicon substrate to define an active region between two adjacent shallow trench isolation structures, where the shallow trench isolation structures are used to isolate the active region from other devices in the silicon substrate.
In some embodiments, the material of the nitride layer 311 may be silicon nitride (SiN). Since silicon nitride is a strong masking material, it helps protect other areas on the substrate 30 during the isolation layer material deposition process; and the nitride layer 311 may also act as a barrier material during a subsequent planarization process. The nitride layer 311 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD for short). Chemical vapor deposition refers to a process of introducing vapor containing a gaseous reactant or a liquid reactant constituting a thin film element and other gases required for reaction into a reaction chamber to perform chemical reaction on the surface of a substrate to generate a thin film; after the chemical vapor deposition treatment, the adhesiveness of the surface-treated film was improved by about 30%, and scratches generated during molding such as bending and stretching were prevented. Photoresists (PR) are also known as photoresists, which are organic compounds that are sensitive to light and change in solubility in a developer after exposure to ultraviolet light. The pattern on the mask can be transferred to the photoresist layer on the top layer of the wafer surface through the photoresist.
Specifically, in connection with the above embodiment, before forming the nitride layer 311 on the surface of the substrate 30, the method further includes: an isolation oxide layer 310 is formed on the surface of the substrate 30, and the nitride layer 311 covers the isolation oxide layer 310. When the nitride layer 311 is etched using the patterned photoresist layer 312 as a mask, the corresponding region of the isolation oxide layer 310 is also etched. The isolation oxide layer 310 may be silicon oxide (SiO) to reduce the damage of the stress of the nitride layer 31 to the substrate 30. When the base 30 is a silicon substrate, the active region in the silicon substrate may be protected from chemical contamination during subsequent removal of the nitride layer by growing an isolation oxide layer on the surface of the silicon substrate to a thickness of about 150-200 angstroms.
In this embodiment, before the isolating material depositing step in step S2, the method further includes: and S20, a liner oxide layer forming step, namely forming a liner oxide layer on the bottom and the side wall of the groove. By forming a liner oxide layer on the bottom and sidewalls of the trench, oxygen molecules can be prevented from diffusing to the substrate during trench fill deposition; at the same time, the liner oxide layer can also improve the interface characteristic between the substrate and the trench filling isolation layer.
Referring to step S20 and fig. 4, a pad oxide layer forming step is performed to form a pad oxide layer 32 on the bottom and the sidewalls of the trench 301. Specifically, in the step of forming the pad oxide layer, the pad oxide layer 32 may be formed by depositing on the bottom and the sidewall of the trench 301 by using a chemical vapor deposition method, or the pad oxide layer 32 may be formed by growing on the bottom and the sidewall of the trench 301 by using a thermal oxidation growth method. When the base 30 is a silicon substrate, such a thermally grown pad oxide layer 32 passivates the silicon substrate surface and may isolate the trench fill deposited isolation layer from the silicon substrate; the liner oxide layer 32 also serves as an effective barrier to prevent sidewall leakage current in the device. The material of the pad oxide layer 32 may be silicon oxide.
Referring to step S2 and fig. 5, an isolation material deposition (Dep) step is performed to deposit an isolation material on the surface of the substrate 30 and in the trench 301 to form an isolation layer 33, wherein the isolation layer 33 forms a protrusion (Overhang) 331 at a corner 302 of the trench 301 adjacent to the predetermined mask (specifically, adjacent to the patterned nitride layer 311), that is, an upper corner of the trench 301. Since trench 301 has a certain Aspect Ratio (AR), isolation layer 33 forms protrusions 331 at corners 302 of trench 301 when trench 301 is filled with deposited isolation layer 33. The topography of the protrusions 331 can severely impact the film surface topography, which can present risks and challenges for subsequent cmp processes. And for trenches with larger aspect ratios (AR 4-6), the isolation layer formed in the trench may also have voids 332 during deposition of the isolation material, affecting device performance.
In some embodiments, in the isolation material deposition step of step S2, the isolation material is deposited by introducing silane (SiH 4 ) With oxygen (O) 2 ) As a deposition reaction gas, to form an oxide isolation layer, i.e., to fill the trench 301 with deposited silicon oxide as the isolation layer 33.
In some embodiments, in the step S2 of depositing the isolation material, the oxide isolation layer is formed by chemical vapor deposition.
Referring to step S3 and fig. 6, an isolation layer etching (Etch) step etches the isolation layer 33 at the corner 302 to planarize the bump 331. By etching the isolation layer 33, the protrusions 331 may be planarized to facilitate subsequent further deposition of isolation material. And in the case of the isolation layer 33 formed in the trench 301 having a void 332; the voids 332 may also be exposed by etching the isolation layer 33 to facilitate subsequent further deposition of isolation material.
In some embodiments, in the isolation layer etching step of step S3, nitrogen trifluoride (NF) 3 ) Trifluoromethane (CHF) 3 ) Tetrafluoromethane (CF) 4 ) At least one of which is used as a plasma etching gas. That is, one of the above gases may be used as the plasma etching gas, or a mixed gas of two or more of the above gases may be used as the plasma etching gas.
Referring to step S4 and fig. 7, a sputtering (sputtering) step is performed to bombard the isolation layer 33 at the corner 302 by introducing a sputtering gas, so as to further planarize the protrusion 331. The topography of the protrusions 331 may be further modified to further planarize by bombarding the spacer layer 33, and in particular the protrusions 331 at the corners 302, with sputtering gas. And for the isolation layer with the cavity formed in the trench with the larger depth-to-width ratio, the cavity can be further exposed in the step, so that the isolation material can be further deposited later.
In this embodiment, sputtering gas may be used to bombard the protrusions 331 at the corners 302 under a bias power of 5000-6000W, so that the protrusions 331 may be effectively planarized, so that the surface film morphology of the grooves 301 is flatter. The sputtering step may also be performed to open the spacer layer 33 to be sealed and then slowly fill it, and finally form a void-free spacer layer.
In some embodiments, the sputtering gas may be selected from argon (Ar), helium (He), hydrogen (H) 2 ) At least one of (2). That is, one of argon, helium, and hydrogen may be used as the sputtering gas, or a mixed gas of two or more of the above gases may be used as the sputtering gas; for example, a mixed gas of argon and helium is used as the sputtering gas.
Referring to step S5 and fig. 8, the isolation material deposition step (S2), the isolation layer etching step (S3) and the sputtering step (S4) are repeated until the trench 301 is filled with isolation material and the flatness of the isolation layer 33 at the corner 302 meets a predetermined flatness threshold. For the groove 301 with a larger depth-to-width ratio (AR is 4-6), good filling effect can be obtained through two or more progressive filling depositions, so that the surface morphology of the isolation layer 33 film layer at the corner 302 is flatter, the subsequent chemical mechanical polishing process is facilitated, the isolation layer formed in the groove can be prevented from having holes, and the device performance is improved.
Referring to step S6 and fig. 9, a planarization step is performed to planarize the isolation layer 33 by using a planarization process to form the trench isolation structure 39 in the trench 301.
In some embodiments, in the planarization step of step S6, the planarization process used is a chemical mechanical polishing process. The isolation layer 33 is planarized by CMP until the surface of the patterned nitride layer 311 as a pre-set mask is exposed.
In some embodiments, the planarizing step of step S6 further comprises: and removing the preset mask plate. And removing the preset mask plate through an etching process. The patterned nitride layer 311 is removed as a pre-set reticle, for example, using a wet etch. The nitride layer and the oxide layer have an etching selectivity to the solution used for wet etching, and therefore, the nitride layer is etched back while the oxide layer can be left.
In some embodiments, the trench isolation structure 39 is formed in a semiconductor substrate, or in an interlayer dielectric layer, or in an inter-metal dielectric layer. The trench isolation structure 39 is suitable for silicon-based devices including, but not limited to, silicon-based MOSFET and IGBT devices, for silicon carbide (SiC) based and/or Diamond (Diamond) based devices. The trench isolation structure 39 may be a shallow trench isolation structure having aspect ratios (4:1) - (6:1).
According to the embodiment of the application, the trench filling adopts a deposition, etching and sputtering (Dep+etch+Sputter) mode, so that the flatness of the isolation layer at the corner of the trench is effectively improved, the uniformity of the surface of the film layer is improved, the risk and challenges of the subsequent chemical mechanical polishing process are reduced, and the product competitiveness is improved on the basis of ensuring the filling capability of a large depth-to-width ratio (AR is 4-6). Compared with the trench isolation structure formed in the conventional filling mode shown in fig. 1, the flatness of the isolation layer at the trench corners of the trench isolation structure formed in the above embodiment of the application shown in fig. 8 is greatly improved.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprise," "include," or any other variation thereof, are intended to cover a non-exclusive inclusion. In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. It should be noted that modifications and adaptations to the present application may occur to one skilled in the art without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (12)
1. A method of forming a trench isolation structure, the method comprising:
a groove etching step, namely etching a substrate by taking a preset mask plate as a mask, and forming a groove on the substrate; an isolation material deposition step, namely depositing an isolation material on the surface of the substrate and in the groove to form an isolation layer, wherein a bulge is formed at the corner of the groove, which is close to the preset mask plate, of the isolation layer;
an isolation layer etching step, namely etching the isolation layer at the corner to planarize the bulge; sputtering, namely introducing sputtering gas to bombard the isolation layer at the corner so as to further planarize the bulge;
repeating the isolation material deposition step, the isolation layer etching step and the sputtering step until the isolation material is filled in the groove, and the flatness of the isolation layer at the corner meets a preset flatness threshold value; and
and flattening the isolation layer by adopting a flattening process so as to form the trench isolation structure in the trench.
2. The method of claim 1, wherein in the spacer material depositing step, the oxide spacer layer is formed by introducing silane and oxygen as deposition reaction gases.
3. The method of claim 1, wherein the isolating material is deposited by chemical vapor deposition to form an oxide isolating layer.
4. The method of claim 1, wherein at least one of nitrogen trifluoride, trifluoromethane, and tetrafluoromethane is used as the plasma etching gas in the spacer etching step.
5. The method of claim 1, wherein in the sputtering step, the sputtering gas is selected from at least one of argon, helium, and hydrogen.
6. The method of claim 1, wherein the planarization process used in the planarization step is a chemical mechanical polishing process.
7. The method of claim 1, wherein the isolating material depositing step is preceded by the step of:
and forming a liner oxide layer on the bottom and the side wall of the trench.
8. The method of claim 7, wherein in the step of forming the pad oxide layer, the pad oxide layer is formed on the bottom and the side wall of the trench by chemical vapor deposition, or the pad oxide layer is formed on the bottom and the side wall of the trench by thermal oxidation growth.
9. The method of claim 1, wherein the trench etching step further comprises: providing a substrate and forming a nitride layer on the surface of the substrate;
etching the nitride layer by taking the patterned photoresist layer as a mask to form a patterned nitride layer;
and removing the residual patterned photoresist layer to form a patterned nitride layer serving as the preset mask plate to etch the substrate so as to form the groove.
10. The method of claim 9, wherein the forming a nitride layer on the substrate surface is preceded by:
and forming an isolation oxide layer on the surface of the substrate, wherein the nitride layer covers the isolation oxide layer.
11. The method of claim 1, wherein the planarizing step is followed by further comprising: and removing the preset mask plate.
12. The method of claim 1, wherein the trench isolation structure is formed in a semiconductor substrate, or in an interlayer dielectric layer, or in an inter-metal dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310850629.4A CN116864445A (en) | 2023-07-11 | 2023-07-11 | Forming method of trench isolation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310850629.4A CN116864445A (en) | 2023-07-11 | 2023-07-11 | Forming method of trench isolation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116864445A true CN116864445A (en) | 2023-10-10 |
Family
ID=88235473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310850629.4A Pending CN116864445A (en) | 2023-07-11 | 2023-07-11 | Forming method of trench isolation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116864445A (en) |
-
2023
- 2023-07-11 CN CN202310850629.4A patent/CN116864445A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105047660B (en) | Shallow trench isolation structure | |
| US6743728B2 (en) | Method for forming shallow trench isolation | |
| US6258676B1 (en) | Method for forming a shallow trench isolation using HDP silicon oxynitride | |
| US6071792A (en) | Methods of forming shallow trench isolation regions using plasma deposition techniques | |
| JP4052790B2 (en) | Device isolation film manufacturing method that prevents divot generation and simple processes | |
| US20140175597A1 (en) | Trench with reduced silicon loss | |
| KR100518587B1 (en) | Fabrication Method for shallow trench isolation structure and microelectronic device having the same structure | |
| US6828248B1 (en) | Method of pull back for forming shallow trench isolation | |
| US20100129983A1 (en) | Method of Fabricating Semiconductor Device | |
| US6194286B1 (en) | Method of etching thermally grown oxide substantially selectively relative to deposited oxide | |
| CN105655285A (en) | Trench isolation structure and formation method thereof | |
| US20110207290A1 (en) | Semiconductor device fabrication method | |
| US6355539B1 (en) | Method for forming shallow trench isolation | |
| US6383874B1 (en) | In-situ stack for high volume production of isolation regions | |
| CN116864445A (en) | Forming method of trench isolation structure | |
| CN116864444A (en) | Method for forming trench isolation structure | |
| US7018905B1 (en) | Method of forming isolation film in semiconductor device | |
| CN117238838A (en) | Method for forming trench isolation structure | |
| KR100685581B1 (en) | Device Separator Formation Method | |
| KR100874429B1 (en) | Gap filling method in semiconductor device manufacturing | |
| US20020119628A1 (en) | STI method for semiconductor processes | |
| KR100500942B1 (en) | Fabricating method for trench isoaltion layer using bottom anti reflection coating | |
| KR100912988B1 (en) | Manufacturing Method of Semiconductor Device | |
| US7981800B1 (en) | Shallow trench isolation structures and methods for forming the same | |
| KR100538809B1 (en) | Fabricating method of isolation layer adopting nf3 high density plasma oxide layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |