CN116844954A

CN116844954A - Method for forming semiconductor element pattern

Info

Publication number: CN116844954A
Application number: CN202310768739.6A
Authority: CN
Inventors: 洪朝臻; 翁文毅; 陈煌彬; 陈瑛蕙
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2023-06-27
Filing date: 2023-06-27
Publication date: 2023-10-03

Abstract

The invention provides a method for forming a semiconductor element pattern, which is characterized in that an overlay monitoring pattern is synchronously formed in a surrounding area during a patterning process, overlay data of the overlay monitoring pattern in different manufacturing stages are measured, and contributions of the processes in different manufacturing stages to the overall overlay offset are distinguished, so that the overlay offset can be fed back and compensated more accurately, and the overlay accuracy of a double patterning process is improved.

Description

Method for forming semiconductor element pattern

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor device pattern.

Background

The manufacturing process of the semiconductor component is to write the circuit layout pattern onto a photomask to form a photomask pattern, and then transfer the photomask pattern into the target material layer through the patterning process. Conventional patterning processes typically include first forming a photoresist layer over a target material layer, then performing a photolithography process to transfer a photomask pattern into the photoresist layer in a certain proportion to form a photoresist pattern, then etching the target material layer with the photoresist as an etching mask, and further transferring the photoresist pattern into the target material layer to define a layout pattern in the target material layer.

In advanced semiconductor manufacturing technology, multiple patterning processes (multi-patterning process) have been proposed to achieve more closely arranged layout patterns. Multiple patterning processes involve decomposing a single layout pattern into multiple photomasks, and then performing the patterning process separately with the photomasks to collectively define the layout pattern in the target material layer. Overlay accuracy is a critical factor in whether a multiple patterning process can produce an ideal layout pattern.

Disclosure of Invention

The invention aims to provide a method for forming a semiconductor element pattern, which is used for synchronously forming an overlay monitoring pattern in a surrounding area during a patterning process, measuring overlay data of the overlay monitoring pattern in different manufacturing stages, and feeding the overlay data back to the patterning process, so that overlay offset can be more accurately compensated, the overlay accuracy of the patterning process is improved, and the method is helpful for obtaining an ideal pattern of a storage unit in a unit area.

A method for forming a semiconductor device pattern according to an embodiment of the present invention includes the following steps. First, a first mask layer is formed, which includes a cell region and a surrounding region. And then, patterning the first mask layer, forming a first pattern in the first mask layer of the surrounding area, wherein the first pattern extends along a first direction and is arranged in parallel along a second direction, and the first direction is perpendicular to the second direction. And then, forming a second mask layer on the first mask layer, patterning the second mask layer, and forming second patterns in the second mask layer, wherein the second patterns are respectively positioned between the first patterns along the second direction. And measuring a difference D1 between the second pattern and the first patterns at two sides of the second pattern to obtain first overlay data. Then, an etching process is performed, the second pattern is transferred to the first mask layer, a third pattern is formed between the first patterns, and a difference D2 between the third pattern and the distances between the first patterns on two sides of the third pattern is measured to obtain second overlay data. And then, feeding back the first overlay data and the second overlay data to the second mask layer for patterning, and forming a unit pattern in the unit area of the first mask layer.

A method of forming a semiconductor device pattern according to another embodiment of the present invention includes the following steps. First, a first mask layer is formed, which includes a cell region and a surrounding region. And then, patterning the first mask layer, and forming a first line segment pattern in the first mask layer of the surrounding area, wherein the first line segment pattern extends along a first direction and is arranged in parallel along a second direction, and the first direction is perpendicular to the second direction. And then, forming a second mask layer on the first mask layer, patterning the second mask layer, and forming a first opening pattern in the second mask layer, wherein the first opening pattern at least partially overlaps with the first line segment pattern. And measuring a difference D1 between the first opening pattern and the spacing of the first line segment patterns at two sides of the first opening pattern to obtain first overlay data. Then, an etching process is performed, the first opening pattern is transferred to the first mask layer, a second opening pattern cut through the first line segment pattern is formed, and then a difference D2 between the second opening pattern and the distances between the second opening pattern and the first line segment patterns on two sides of the second opening pattern is measured, so that second overlay data are obtained. And then, feeding back the first overlay data and the second overlay data to the second mask layer for patterning, and forming a unit pattern in the unit area of the first mask layer.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.

Fig. 2 to 8 are schematic views illustrating a method of forming a semiconductor device pattern according to an embodiment of the present invention.

Fig. 9 and 10 are schematic views illustrating a method of forming a semiconductor device pattern according to an embodiment of the present invention.

Fig. 11 and 12 are schematic views illustrating a method of forming a semiconductor device pattern according to an embodiment of the present invention.

Fig. 13 and 14 are schematic views illustrating a method of forming a semiconductor device pattern according to an embodiment of the present invention.

Wherein reference numerals are as follows:

10. substrate and method for manufacturing the same

12. Silicon oxide layer

14. Amorphous silicon layer

16. Silicon nitride layer

18. Flat layer

20. Antireflection layer

22. Photoresist layer

110. First pattern

120. Second pattern

130. Third pattern

140. Fourth pattern

150. Fifth pattern

160. Sixth pattern

210. First line segment pattern

220. First opening pattern

230. Second opening pattern

240. Second line segment pattern

250. Third opening pattern

260. Fourth opening pattern

16a line pattern

16b opening pattern

16c cell pattern

22a opening pattern

a spacing

b spacing

ACT unit pattern

11. End portion

L1 spacing

L2 spacing

L3 spacing

L4 pitch

L5 spacing

L6 pitch

ML1 first mask layer

ML2 second mask layer

R1 unit region

R2 peripheral region

In the X direction

Y direction

In the Z direction

R direction

Detailed Description

In order to enable those skilled in the art to which the invention pertains, a few preferred embodiments of the invention are described below in detail, together with the accompanying drawings, in order to further explain the principles of the invention and its advantages. Those skilled in the art to which the invention pertains will be able to replace, reorganize, and mix features in several different embodiments with reference to the following examples to complete other embodiments without departing from the spirit of the invention.

Fig. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. The semiconductor device may be a memory device including a substrate 10, wherein the substrate 10 defines at least a cell region R1 and a peripheral region R2, the cell region R1 includes memory cells, and the peripheral region R2 includes various mark patterns, monitor patterns, and test key patterns for electrical analysis, but is not limited thereto. For ease of understanding, the X-direction, Y-direction, R-direction, and Z-direction are defined in the figure, wherein the X-direction, Y-direction, and R-direction are in the same plane as the surface of the substrate 10, and the Z-direction is perpendicular to the surface of the substrate 10. According to an embodiment of the present invention, the X direction and the Y direction are perpendicular to each other, and the R direction and the X direction may include an included angle between 15 degrees and 130 degrees.

In some embodiments, the fabrication of the semiconductor device shown in fig. 1 involves the use of a double patterning process to define the pattern of memory cells in the cell region R1. The method for forming a semiconductor device pattern according to the embodiments described below, which is used for forming an overlay monitor pattern in the surrounding region R2 during a double patterning process, and measuring overlay data of the overlay monitor pattern at different manufacturing stages, and distinguishing contributions of processes (such as a photolithography process and an etching process) at different manufacturing stages to the overall overlay offset, can accurately feed back and compensate the overlay offset, improve overlay accuracy of the double patterning process, and help to obtain a desired pattern of a memory cell in the cell region R1.

Fig. 2 to 8 are schematic views of a method of forming a semiconductor device pattern according to an embodiment of the present invention, wherein fig. 2, 4 and 6 are cross-sectional views (lower part) and upper view (upper part) of a cell region R1 at different steps, and fig. 3, 5 and 7 are cross-sectional views (lower part) and upper view (upper part) of a surrounding region R2 (refer to fig. 1) at the steps of fig. 2, 4 and 6, respectively. Fig. 8 is a cross-sectional view (lower part) and a top view (upper part) of the first mask layer ML1 of fig. 6 after transferring the pattern to the cell region R1 of the substrate 10.

Referring to fig. 2 and 3, a substrate 10 is provided, on which a first mask layer ML1 is disposed. The substrate 10 is, for example, a silicon base, an epitaxial silicon base, a silicon germanium base, a silicon carbide base, or a silicon-on-insulator (SOI) base, but is not limited thereto. The first mask layer ML1 may include a single-layer or multi-layer structure. According to an embodiment of the present invention, the first mask layer ML1 may include, but is not limited to, a silicon oxide layer 12, an amorphous silicon layer 14, and a silicon nitride layer 16 from bottom to top. The first mask layer ML1 may include a cell region and a surrounding region corresponding to the cell region R1 (refer to fig. 1) and the surrounding region R2 (refer to fig. 1) of the substrate 10, respectively. Next, a patterning process (e.g., a photolithography and etching process) is performed on the first mask layer ML1, the pattern on the first photomask (not shown) is transferred into the first mask layer ML1, a plurality of line patterns 16a are formed in the cell region of the first mask layer ML1, and a plurality of first patterns 110 are formed in the peripheral region of the first mask layer ML1. The line patterns 16a are linearly extended along the R direction and are arranged in parallel along the Y direction, as viewed from above. The first patterns 110 are line segment patterns, respectively extending along the Y direction, substantially equidistantly arranged along the X direction at a pitch L1, and parallel to each other. According to an embodiment of the present invention, the line pattern 16a and the first pattern 110 are both defined in the silicon nitride layer 16 of the first mask layer ML1.

Referring to fig. 4 and 5, a planarization layer 18 (e.g., an organic dielectric layer) is formed on the first mask layer ML1, and then a second mask layer ML2 is formed on the planarization layer 18. The second mask layer ML2 may include a single-layer or multi-layer structure. According to an embodiment of the present invention, the second mask layer ML2 may include an anti-reflection layer 20 and a photoresist layer 22. The second mask layer ML2 may include a cell region and a surrounding region corresponding to the cell region R1 (refer to fig. 1) and the surrounding region R2 (refer to fig. 1) of the substrate 10, respectively. Next, a patterning process (e.g., photolithography or photolithography and etching process) is performed on the second mask layer ML2, the pattern on the second photomask (not shown) is transferred into the second mask layer ML2, a plurality of opening patterns 22a are formed in the cell region of the second mask layer ML2, and a plurality of second patterns 120 are formed in the peripheral region of the second mask layer ML2. The opening pattern 22a is in an array arrangement in a top view, overlapping the line pattern 16 a. The second patterns 120 are respectively disposed between two adjacent first patterns 110, and are groove patterns, extending along the Y direction, and the two adjacent second patterns 120 are substantially equidistantly and parallel arranged along the X direction at a distance L2. The first patterns 110 extend along the Y direction and are substantially equally spaced in parallel along the X direction by a pitch L1. The pitch L2 and the pitch L1 may be equal or unequal. According to an embodiment of the present invention, the opening pattern 22a and the second pattern 120 are both defined in the photoresist layer 22 of the second mask layer ML2.

With reference to fig. 5, after forming the second patterns 120, the pitches a and b of each second pattern 120 and the first patterns 110 on both sides thereof are measured, and then the differences D1 between each group of pitches a and b are calculated to obtain the first overlay data. The first overlay data can determine an overlay shift of the opening pattern 22a with respect to the line pattern 16a in the X direction.

Referring to fig. 5, 6 and 7, the photoresist layer 22 of the second mask layer ML2 is used as a mask to etch the underlying material layer (including the anti-reflection layer 20, the planarization layer 18 and the silicon nitride layer 16 and the amorphous silicon layer 14 of the first mask layer ML 1), the pattern of the second mask layer ML2 is transferred into the first mask layer ML1, a plurality of opening patterns 16b are formed in the cell region of the first mask layer ML1, and a plurality of third patterns 130 are formed in the surrounding region of the first mask layer ML1. Then, the remaining flat layer 18 and the second mask layer ML2 on the first mask layer ML1 are removed. The opening pattern 16b cuts each line pattern 16a into a plurality of line segments, obtaining a unit pattern 16c. The third patterns 130 are respectively located between two adjacent first patterns 110. In some embodiments, the third pattern 130 is a groove pattern defined in the amorphous silicon layer 14. The third patterns 130 extend along the Y direction and are substantially equally spaced in parallel along the X direction by a pitch L3. The pitch L3 and the pitch L2 may be made equal or unequal by adjusting etching trim.

With reference to fig. 7, next, the pitches a and b of each third pattern 130 and the first patterns 110 on both sides thereof are measured, and then the difference D2 between each group of pitches a and b is calculated to obtain the second overlay data. The second overlay data can determine the overlay shift of the opening pattern 16b with respect to the line pattern 16a (refer to fig. 6) in the X direction.

In some embodiments, the distances L1 and L2 in fig. 5 and the distance L3 in fig. 7 are substantially equal, and the difference D1 and the difference D2 are constant. In some embodiments, the spacing L1 and the spacing L2 in fig. 5 are substantially equal, the spacing L1 and the spacing L3 in fig. 7 are not equal, the difference D1 is a constant value, and the difference D2 is a variable value. In some embodiments, the distances L1 and L2 in fig. 5 and the distance L3 in fig. 7 are different from each other, and the difference D1 and the difference D2 are all variable values.

Referring to fig. 7 and 8, after determining that the overlapping of the double patterning process in the X direction in the foregoing fig. 2 to 7 meets the process specification according to the first overlapping data and the second overlapping data, the underlying substrate 10 is etched using the first mask layer ML1 as a mask, and the cell pattern 16c in fig. 6 is transferred into the cell region R1 (refer to fig. 1) of the substrate 10, so as to obtain the cell pattern ACT. Referring to fig. 4 and 8, the opening pattern 22a of the second mask layer ML2 determines the position of the end portion 11 of the cell pattern ACT.

In some embodiments, referring to fig. 1-8, if it is determined that the overlay shift does not meet the process specification, a rework (rework) process is entered. The rework process includes completely removing the first mask layer ML1 and the second mask layer ML2 on the substrate 10, and then performing the double patterning process of fig. 2 to 7 on the substrate 10 again. The first overlay data and the second overlay data can be fed back to the reproduction flow, and the preset overlay offset of the patterning process of the second mask layer ML2 is corrected, so that the required overlay accuracy can be achieved after the reproduction flow, and the finally obtained pattern can meet the overlay specification. In some embodiments, the first and second stacks of data may also be fed back to the double patterning process performed on another substrate.

Other overlay monitoring patterns may be formed on another portion of the surrounding region R2 (refer to fig. 1) for determining overlay shift in other directions (e.g., Y direction). For example, please refer to fig. 9 and 10, which are schematic diagrams illustrating a method for forming a semiconductor device pattern according to an embodiment of the present invention. Fig. 9 and 10 are a sectional view (lower part of the drawing) and a top view (upper part of the drawing) of the step shown in fig. 4 and 6 in the surrounding region R2 (refer to fig. 1), respectively.

As shown in fig. 9, after forming the first mask layer ML1 on the substrate 10, a patterning process (e.g., a photolithography and etching process) is performed on the first mask layer ML1, a pattern on a first photomask (not shown) is transferred into the first mask layer ML1, a plurality of line patterns 16a (refer to fig. 2) are formed in a cell region of the first mask layer ML1, and a plurality of fourth patterns 140 are formed in a peripheral region of the first mask layer ML1. Next, the planarization layer 18 and the second mask layer ML2 are formed on the first mask layer ML1 in an overall manner, and then a patterning process (e.g., photolithography or photolithography and etching process) is performed on the second mask layer ML2, so that the pattern on the second photomask (not shown) is transferred into the second mask layer ML2, a plurality of opening patterns 22a (refer to fig. 4) are formed in the cell region of the second mask layer ML2, and a plurality of fifth patterns 150 are formed in the peripheral region of the second mask layer ML2. The fourth patterns 140 are line segment patterns extending along the X direction, substantially equidistantly arranged along the Y direction at a pitch L4, and parallel to each other, as viewed from above. The fifth patterns 150 are respectively interposed between two adjacent fourth patterns 140, and are groove patterns extending along the X direction and arranged in parallel at substantially equal intervals along the Y direction with a pitch L5. According to an embodiment of the present invention, the fourth pattern 140 is defined in the silicon nitride layer 16 of the first mask layer ML1, and the fifth pattern 150 is defined in the photoresist layer 22 of the second mask layer ML2.

With continued reference to fig. 9, next, the pitches a and b of each fifth pattern 150 and the fourth patterns 140 on both sides thereof are measured, and then the difference D3 between each set of pitches a and b is calculated to obtain the third overlay data. Referring to fig. 4, the third overlay data may determine an overlay shift of the opening pattern 22a of the unit region R1 with respect to the line pattern 16a in the Y direction.

As shown in fig. 9 and 10, the photoresist layer 22 of the second mask layer ML2 is used as a mask to etch the underlying material layer, the pattern of the second mask layer ML2 is transferred into the first mask layer ML1, a plurality of opening patterns 16b (refer to fig. 6) are formed in the cell region of the first mask layer ML1, and a plurality of sixth patterns 160 are formed in the surrounding region of the first mask layer ML1. Then, the remaining flat layer 18 and the second mask layer ML2 on the first mask layer ML1 are removed. The sixth patterns 160 are respectively located between two adjacent fourth patterns 140. In some embodiments, the sixth pattern 160 is a groove pattern defined in the amorphous silicon layer 14. The sixth patterns 160 extend along the X-direction and are substantially equally and parallel arranged along the Y-direction at a pitch L6. The pitch L6 and the pitch L5 may be made equal or unequal by adjusting etching trim.

With reference to fig. 10, after forming the sixth patterns 160, the pitches a and b of each sixth pattern 160 and the fourth patterns 140 on both sides thereof are measured, and then the difference D4 between each group of pitches a and b is calculated to obtain fourth overlay data. Referring to fig. 2 and 6, the fourth overlay data may determine an overlay shift of the opening pattern 16b of the cell region R1 with respect to the line pattern 16a in the Y direction.

In some embodiments, the distances L4 and L5 in fig. 9 and the distance L6 in fig. 10 are substantially equal, and the difference D3 and the difference D4 are constant. In some embodiments, the distance L4 and the distance L5 in fig. 9 are substantially equal, the distance L4 and the distance L6 in fig. 10 are not equal, the difference D3 is a constant value, and the difference D4 is a variable value. In some embodiments, the distances L4 and L5 in fig. 9 and the distance L6 in fig. 10 are different from each other, and the difference D3 and the difference D4 are all variable values.

Subsequently, it is determined whether the overlapping of the double patterning process in the X direction and the Y direction meets the specifications of the process according to the first overlapping data, the second overlapping data, the third overlapping data and the fourth overlapping data, and if so, the etching process of fig. 8 is entered, and referring to fig. 7 and 8, the pattern of the first mask layer ML1 is transferred into the substrate 10, and the unit pattern ACT is formed in the unit region R1 (refer to fig. 1) of the substrate 10. If the pattern does not meet the specification, entering a reproduction flow, feeding the first overlay data and the second overlay data back to a double patterning process of the reproduction flow, and correcting the preset overlay offset to enable the finally obtained pattern to meet the overlay specification.

The overlay monitoring pattern of the present invention can refer to the layout of the cell region R1 (refer to fig. 1), the first pattern of the surrounding region R2 (refer to fig. 1) is designed as a line segment pattern, and the second pattern is designed as an opening pattern. For example, please refer to fig. 11 and 12, which are schematic diagrams illustrating a method for forming a semiconductor device pattern according to an embodiment of the present invention. Fig. 11 and 12 are a sectional view (lower part of the drawing) and a top view (upper part of the drawing) of the step shown in fig. 4 and 6, respectively, in the surrounding region R2 (refer to fig. 1).

As shown in fig. 11, a first mask layer ML1 is formed on the substrate 10, and then a patterning process (e.g., a photolithography and etching process) is performed on the first mask layer ML1, a pattern on a first photomask (not shown) is transferred into the first mask layer ML1, a plurality of line patterns 16a (refer to fig. 2) are formed in a cell region of the first mask layer ML1, and a plurality of first line segment patterns 210 are formed in a peripheral region of the first mask layer ML1. Next, the planarization layer 18 and the second mask layer ML2 are formed on the first mask layer ML1 in an overall manner, and then a patterning process (e.g., photolithography or photolithography and etching process) is performed on the second mask layer ML2, so that a pattern on a second photomask (not shown) is transferred into the second mask layer ML2, a plurality of opening patterns 22a (refer to fig. 4) are formed in a cell region of the second mask layer ML2, and a plurality of first opening patterns 220 are formed in a peripheral region of the second mask layer ML2. The first line patterns 210 extend along the Y direction, are substantially equidistantly arranged along the X direction at a pitch L1, and are parallel to each other, respectively, when viewed from above. The first opening patterns 220 are arranged in an array, at least partially overlapped with the first line segment patterns 210, and are substantially equidistantly and parallel arranged along the X-direction at a distance L2. According to an embodiment of the present invention, the first line segment pattern 210 is defined in the silicon nitride layer 16 of the first mask layer ML1, and the first opening pattern 220 is defined in the photoresist layer 22 of the second mask layer ML2.

Please continue to refer to fig. 11. Next, the pitches a and b of the first opening patterns 220 and the first line segment patterns 210 on both sides thereof are measured, and then the difference D1 between the pitches a and b is calculated to obtain the first overlay data. Referring to fig. 4, the first overlay data may determine an overlay shift of the opening pattern 22a of the unit region R1 with respect to the line pattern 16a in the X direction.

As shown in fig. 11 and 12, the photoresist layer 22 of the second mask layer ML2 is used as a mask to etch the underlying material layer, the pattern of the second mask layer ML2 is transferred into the first mask layer ML1, a plurality of opening patterns 16b (refer to fig. 6) are formed in the cell region of the first mask layer ML1, and a plurality of second opening patterns 230 are formed in the peripheral region of the first mask layer ML1. Then, the remaining flat layer 18 and the second mask layer ML2 on the first mask layer ML1 are removed. The second opening patterns 230 are defined in the silicon nitride layer 16, at least partially overlap the first line segment patterns 210, and are substantially equidistantly and parallel arranged along the X-direction at a pitch L3. The pitch L2 and the pitch L3 may be made equal or unequal by adjusting etching trim.

Please continue to refer to fig. 12. Next, the distance a and the distance b between each second opening pattern 230 and the first line segment patterns 210 on both sides thereof are measured, and then the difference D2 between each set of the distance a and the distance b is calculated to obtain second overlay data. The second overlay data can determine the overlay shift of the opening pattern 16b (refer to fig. 6) of the cell region R1 with respect to the line pattern 16a in the X direction.

In some embodiments, the distances L1 and L2 in fig. 11 and the distance L3 in fig. 12 are substantially equal, and the difference D1 and the difference D2 are constant. In some embodiments, the distances L1 and L2 in fig. 11 are substantially equal, the distances L1 and L3 in fig. 12 are not equal, the difference D1 is a constant value, and the difference D2 is a variable value. In some embodiments, the pitches L1 and L2 in fig. 11 and the pitch L3 in fig. 12 are different from each other, and the difference D1 and the difference D2 are all variable values.

Subsequently, according to the first overlay data and the second overlay data, it is determined whether the overlay of the double patterning process in the X direction meets the specification of the process, if so, the etching process of fig. 8 is entered, and referring to fig. 7 and 8, the pattern of the first mask layer ML1 is transferred to the substrate 10, and the unit pattern ACT is formed in the unit region R1 of the substrate 10. If the pattern does not meet the specification, entering a reproduction flow, feeding the first overlay data and the second overlay data back to a double patterning process of the reproduction flow, and correcting the preset overlay offset to enable the finally obtained pattern to meet the overlay specification.

Fig. 13 and 14 are schematic views illustrating a method for forming a semiconductor device pattern according to an embodiment of the invention. Fig. 13 and 14 are a sectional view (lower part of the drawing) and a top view (upper part of the drawing) of the step shown in fig. 4 and 6, respectively, in the surrounding region R2 (refer to fig. 1). In some embodiments, another portion of the surrounding region R2 forms an overlay monitoring pattern for determining overlay shift in other directions (e.g., the Y-direction).

As shown in fig. 13, a first mask layer ML1 is formed on the substrate 10 and a patterning process (e.g., a photolithography and etching process) is performed on the first mask layer ML1, a pattern on a first photomask (not shown) is transferred into the first mask layer ML1, a plurality of line patterns 16a (refer to fig. 2) are formed in a cell region of the first mask layer ML1, and a plurality of second line segment patterns 240 are formed in a peripheral region of the first mask layer ML1. Next, the planarization layer 18 and the second mask layer ML2 are formed on the first mask layer ML1 in an overall manner, and then a patterning process (e.g., photolithography or photolithography and etching process) is performed on the second mask layer ML2, so that a pattern on a second photomask (not shown) is transferred into the second mask layer ML2, a plurality of opening patterns 22a (refer to fig. 4) are formed in a cell region of the second mask layer ML2, and a plurality of third opening patterns 250 are formed in a peripheral region of the second mask layer ML2. The second line segment patterns 240 are line segment patterns extending along the X-direction, substantially equidistantly arranged along the Y-direction at a pitch L4, and parallel to each other, as viewed from above. The third opening patterns 250 are arranged in an array, at least partially overlapping the second line segment patterns 240, and are arranged in parallel at a distance L5 along the Y direction. According to an embodiment of the present invention, the second line segment pattern 240 is defined in the silicon nitride layer 16 of the first mask layer ML1, and the third opening pattern 250 is defined in the photoresist layer 22 of the second mask layer ML2.

Please continue to refer to fig. 13. After forming the third opening patterns 250, the distances a and b between each third opening pattern 250 and the second line segment patterns 240 on both sides thereof are measured, and then the differences D3 between each group of distances a and b are calculated to obtain third overlay data. Referring to fig. 4, the third overlay data may determine an overlay shift of the opening pattern 22a of the unit region R1 with respect to the line pattern 16a in the Y direction.

As shown in fig. 13 and 14, the photoresist layer 22 of the second mask layer ML2 is used as a mask to etch the underlying material layer, the pattern of the second mask layer ML2 is transferred into the first mask layer ML1, a plurality of opening patterns 16b (refer to fig. 6) are formed in the cell region of the first mask layer ML1, and a plurality of fourth opening patterns 260 are formed in the peripheral region of the first mask layer ML1. Then, the remaining flat layer 18 and the second mask layer ML2 on the first mask layer ML1 are removed. The fourth opening patterns 260 are defined in the silicon nitride layer 16, at least partially overlap the second line segment patterns 240, and are substantially equidistantly and parallel arranged along the Y-direction at a pitch L6. The pitch L5 and the pitch L6 may be made equal or unequal by adjusting etching trim.

Please continue to refer to fig. 14. Next, the distance a and the distance b between each fourth opening pattern 260 and the second line segment patterns 240 on both sides thereof are measured, and then the difference D4 between each group of the distance a and the distance b is calculated to obtain fourth overlay data. The fourth overlay data can determine the overlay shift of the opening pattern 16b (refer to fig. 6) of the cell region R1 with respect to the line pattern 16a in the Y direction.

In some embodiments, the distances L4 and L5 in fig. 13 and the distance L6 in fig. 14 are substantially equal, and the difference D3 and the difference D4 are constant. In some embodiments, the spacing L4 and the spacing L5 in fig. 13 are substantially equal, the spacing L4 and the spacing L6 in fig. 14 are not equal, the difference D3 is a constant value, and the difference D4 is a variable value. In some embodiments, the distances L4 and L5 in fig. 13 and the distance L6 in fig. 14 are different from each other, and the difference D1 and the difference D2 are all variable values.

Subsequently, according to the first overlay data, the second overlay data, the third overlay data and the fourth overlay data, whether the overlay of the double patterning process in the X direction and the Y direction accords with the specification of the process is judged, and the etching process of fig. 8 is selected to be entered or the remanufacturing process is selected to be entered.

In summary, the method for forming a semiconductor device pattern according to the embodiments of the present invention forms an overlay monitor pattern in a peripheral region of a semiconductor device during a double patterning process, measures overlay data of the overlay monitor pattern at different manufacturing stages, and distinguishes contributions of processes (e.g., photolithography and etching processes) at different manufacturing stages to an overall overlay offset, so as to more accurately feed back and compensate the overlay offset, improve overlay accuracy of the double patterning process, and help to obtain a desired pattern of memory cells in a cell region of the semiconductor device.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of forming a semiconductor element pattern, comprising:

forming a first mask layer including a cell region and a surrounding region;

patterning the first mask layer, forming a first pattern in the first mask layer of the surrounding area, extending along a first direction and being arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction;

forming a second mask layer on the first mask layer;

patterning the second mask layer to form second patterns in the second mask layer, wherein the second patterns are respectively positioned between the first patterns along the second direction;

measuring a difference D1 between the second pattern and the first patterns on two sides of the second pattern to obtain first overlay data;

performing an etching process, transferring the second pattern into the first mask layer, and forming a third pattern between the first patterns;

measuring a difference D2 between the third pattern and the first patterns on both sides of the third pattern to obtain second overlay data; and

and feeding back the first overlay data and the second overlay data to the patterning of the second mask layer to form a unit pattern in the unit area of the first mask layer.

2. The method of forming a semiconductor element pattern according to claim 1, wherein the first patterns are arranged equidistantly at a pitch L1, the second patterns are arranged equidistantly at a pitch L2, and the third patterns are arranged equidistantly at a pitch L3 along the second direction.

3. The method of forming a semiconductor device pattern according to claim 2, wherein the pitch L1, the pitch L2, and the pitch L3 are equal, and the difference D1 and the difference D2 are constant.

4. The method of forming a semiconductor device pattern according to claim 2, wherein the pitch L1 and the pitch L2 are equal, the pitch L2 and the pitch L3 are not equal, the difference D1 is a constant value, and the difference D2 is a variable value.

5. The method of forming a semiconductor device pattern according to claim 2, wherein the pitch L1, the pitch L2, and the pitch L3 are different from each other, and the difference D1 and the difference D2 are each variable values.

6. The method of forming a semiconductor element pattern according to claim 1, wherein the first mask layer of the peripheral region further includes a fourth pattern extending along the second direction and arranged in parallel along the first direction, the method further comprising:

forming fifth patterns in the second mask layer, wherein the fifth patterns are respectively located between the fourth patterns along the first direction;

measuring a difference D3 between the fifth pattern and the fourth pattern on both sides of the fifth pattern to obtain third overlay data; performing the etching process, transferring the fifth pattern into the first mask layer, and forming a sixth pattern between the fourth patterns;

measuring a difference D4 between the sixth pattern and the fourth pattern on both sides of the sixth pattern to obtain fourth overlay data; and

and feeding back the first overlay data, the second overlay data, the third overlay data and the fourth overlay data to the second mask layer for patterning, and forming a unit pattern in the unit area of the first mask layer.

7. The method of forming a semiconductor device pattern according to claim 6, wherein the fourth patterns are arranged equidistantly at a pitch L4, the fifth patterns are arranged equidistantly at a pitch L5, and the sixth patterns are arranged equidistantly at a pitch L6 along the first direction.

8. The method of forming a semiconductor device pattern according to claim 7, wherein the pitch L4, the pitch L5, and the pitch L6 are equal, and the difference D3 and the difference D4 are constant.

9. The method of forming a semiconductor device pattern according to claim 7, wherein the pitch L4 and the pitch L5 are equal, the pitch L5 and the pitch L6 are unequal, the difference D3 is a constant value, and the difference D4 is a variable value.

10. The method of forming a semiconductor device pattern according to claim 7, wherein the pitch L4, the pitch L5, and the pitch L6 are different from each other, and the difference D3 and the difference D4 are each variable values.

11. A method of forming a semiconductor element pattern, comprising:

forming a first mask layer including a cell region and a surrounding region;

patterning the first mask layer, forming a first line segment pattern in the first mask layer of the surrounding area, extending along a first direction and being arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction;

forming a second mask layer on the first mask layer;

patterning the second mask layer, and forming a first opening pattern in the second mask layer, wherein the first opening pattern at least partially overlaps the first line segment pattern;

measuring a difference D1 between the first opening pattern and the spacing of the first line segment patterns at two sides of the first opening pattern to obtain first overlay data;

performing an etching process, transferring the first opening pattern into the first mask layer to form a second opening pattern cut through the first line segment pattern;

measuring a difference D2 between the second opening pattern and the first line segment patterns at two sides of the second opening pattern to obtain second overlay data; and

12. The method of forming a semiconductor device according to claim 11, wherein the first line segment patterns are arranged equidistantly at a pitch L1, the first opening patterns are arranged equidistantly at a pitch L2, and the second opening patterns are arranged equidistantly at a pitch L3 along the second direction.

13. The method of forming a semiconductor device pattern according to claim 12, wherein the pitch L1, the pitch L2, and the pitch L3 are equal, and the difference D1 and the difference D2 are constant.

14. The method of forming a semiconductor device pattern according to claim 12, wherein the pitch L1 and the pitch L2 are equal, the pitch L2 and the pitch L3 are unequal, the difference D1 is a constant value, and the difference D2 is a variable value.

15. The method of forming a semiconductor device pattern according to claim 12, wherein the pitch L1, the pitch L2, and the pitch L3 are different from each other, and the difference D1 and the difference D2 are each variable values.

16. The method of forming a semiconductor element pattern according to claim 11, wherein the first mask layer of the peripheral region further includes a second line segment pattern extending along the second direction and arranged in parallel along the first direction, the method further comprising:

forming a third opening pattern in the second mask layer, wherein the third opening pattern at least partially overlaps the second line segment pattern;

measuring a difference D3 between the third opening pattern and the intervals of the second line segment patterns at two sides of the third opening pattern to obtain third overlapping data;

performing the etching process, and transferring the third opening pattern into the first mask layer to form a fourth opening pattern cut through the second line segment pattern;

measuring a difference D4 between the fourth opening pattern and the intervals of the second line segment patterns at two sides of the fourth opening pattern to obtain fourth overlapping data; and

17. The method of forming a semiconductor device according to claim 16, wherein the second line segment patterns are arranged equidistantly at a pitch L4, the third opening patterns are arranged equidistantly at a pitch L5, and the fourth opening patterns are arranged equidistantly at a pitch L6 along the first direction.

18. The method of forming a semiconductor device according to claim 17, wherein the pitch L4, the pitch L5, and the pitch L6 are equal, and the difference D3 and the difference D4 are constant.

19. The method of forming a semiconductor device pattern according to claim 17, wherein the pitch L4 and the pitch L5 are equal, the pitch L5 and the pitch L6 are unequal, the difference D3 is a constant value, and the difference D4 is a variable value.

20. The method of forming a semiconductor device pattern according to claim 17, wherein the pitch L4, the pitch L5, and the pitch L6 are not equal, and the difference D3 and the difference D4 are each variable values.