CN116820832A

CN116820832A - Error checking method, medium and device for high-speed data transmission

Info

Publication number: CN116820832A
Application number: CN202311105062.4A
Authority: CN
Inventors: 乔帅
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Priority date: 2023-08-30
Filing date: 2023-08-30
Publication date: 2023-09-29
Anticipated expiration: 2043-08-30
Also published as: CN116820832B

Abstract

The application provides an error checking method, medium and device for high-speed data transmission. The method comprises the following steps: obtaining data to be processed, wherein the data processing flow comprises the steps of executing a first data processing flow and then executing a second data processing flow; executing a first data processing flow on the data to be processed to obtain a first data processing result; at least before the first data processing result is obtained, performing an error check procedure on the data to be processed to obtain an error check result, and allowing the second data processing procedure to be performed when the error check result indicates that there is no error, and prohibiting the second data processing procedure to be performed when the error is indicated to be present. The first data processing flow is performed on the data to be processed and the error checking flow is performed on the data to be processed at least partially synchronously, wherein the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow. This reduces latency and ensures data transmission accuracy.

Description

Error checking method, medium and device for high-speed data transmission

Technical Field

The present application relates to the field of computer technologies, and in particular, to an error checking method, medium, and apparatus for high-speed data transmission.

Background

In applications for high-speed data transmission, such as data communication based on SERializer de-SERializer (SERializer/DESerializer, SERDES), and also interconnection devices employing the peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe) standard protocol, verification information is typically generated at the transmitting end and transmitted along with the original data to the receiving end over a communication channel, where the verification information is then used to detect the erroneous codeword. As data transmission rate and data transmission amount increase, and coding and decoding algorithms and logic become more and more complex, adverse effects are caused on overall transmission delay of the system.

Therefore, the application provides an error checking method, medium and device for high-speed data transmission, which are used for solving the technical problems in the prior art.

Disclosure of Invention

In a first aspect, the present application provides an error checking method for high speed data transmission. The error checking method comprises the following steps: obtaining data to be processed, wherein a data processing flow associated with the data to be processed comprises the steps of executing a first data processing flow and then executing a second data processing flow on an execution result of the first data processing flow; executing the first data processing flow on the data to be processed to obtain the first data processing result; performing an error check procedure on the data to be processed to obtain an error check result at least before the first data processing result is obtained, and allowing the second data processing procedure to be performed on the first data processing result when the error check result indicates that the data to be processed has no error, and prohibiting the second data processing procedure to be performed on the first data processing result when the error check result indicates that the data to be processed has an error, wherein the performing of the first data processing procedure on the data to be processed and the performing of the error check procedure on the data to be processed are performed at least partially in synchronization, and an expected processing delay of the first data processing procedure is greater than an expected processing delay of the error check procedure.

According to the first aspect of the application, the first data processing flow is executed on the data to be processed and the error checking flow is executed on the data to be processed at least partially synchronously, so that the situation that the data processing is started after the data checking is completely completed is avoided, and the overall delay of the system is reduced; in addition, for the case of errors such as error codes, the expected processing delay of the first data processing flow is larger than the expected processing delay of the error checking flow, so that timely error detection is effectively realized, the follow-up flow is forbidden to be performed by the data with the detected errors, and the efficiency and the correctness of data transmission are ensured.

In a possible implementation manner of the first aspect of the present application, a start time of performing the first data processing procedure on the data to be processed is the same as a start time of performing the error checking procedure on the data to be processed.

In a possible implementation manner of the first aspect of the present application, the completion time of executing the first data processing procedure on the data to be processed is later than the completion time of executing the error checking procedure on the data to be processed.

In a possible implementation manner of the first aspect of the present application, a difference between the expected processing delay of the first data processing flow minus the expected processing delay of the error checking flow is greater than a delay margin threshold, the delay margin threshold being determined based on at least one of: data bit width, algorithm complexity, iteration number, polynomial.

In a possible implementation manner of the first aspect of the present application, the error checking method further includes: when the error check result indicates that the data to be processed has errors, correcting the data to be processed to obtain data to be processed after error correction, and then interrupting the execution of the first data processing flow on the data to be processed and starting the execution of the first data processing flow on the data to be processed after error correction.

In a possible implementation manner of the first aspect of the present application, the data processing procedure associated with the data to be processed includes sequentially executing 1 st to nth steps of N steps, where N is a positive integer greater than 1, and the first data processing procedure includes sequentially executing 1 st to kth steps of the N steps, where K is a positive integer greater than 1 and less than N, an expected processing delay from 1 st to kth steps is greater than an expected processing delay of the error checking procedure, and an expected processing delay from 1 st to kth-1 st steps is not greater than an expected processing delay of the error checking procedure.

In a possible implementation manner of the first aspect of the present application, the error checking procedure includes performing at least one of the following data checking algorithms: cyclic redundancy check algorithm, forward error correction algorithm, automatic retransmission request algorithm.

In a possible implementation manner of the first aspect of the present application, the error checking procedure includes sequentially executing a plurality of first error checking algorithms and then executing a plurality of second error checking algorithms in parallel, where an error probability of each of the plurality of first error checking algorithms is greater than an error probability of each of the plurality of second error checking algorithms.

In a possible implementation manner of the first aspect of the present application, when any one of the plurality of first error checking algorithms indicates that the data to be processed has an error or any one of the plurality of second error checking algorithms indicates that the data to be processed has an error, the error checking procedure indicates that the data to be processed has an error, and execution of the first data processing procedure on the data to be processed is interrupted.

In a possible implementation manner of the first aspect of the present application, the plurality of first error checking algorithms includes a cyclic redundancy check algorithm and a forward error correction algorithm, and the plurality of second error checking algorithms includes an automatic retransmission request algorithm.

In a possible implementation manner of the first aspect of the present application, the error checking method is applied to an error checking device, where the error checking device includes a first data processing module, a second data processing module, an error checking module, and a first output control module, where the first data processing module is configured to perform the first data processing procedure on the data to be processed to obtain the first data processing result, the second data processing module is configured to perform the second data processing procedure on an output of the first data processing module, the error checking module is configured to perform the error checking procedure on the data to be processed to obtain the error checking result, and the first output control module is configured to turn on or off the output of the first data processing module according to the error checking result provided by the error checking module.

In a possible implementation manner of the first aspect of the present application, when the error check result indicates that the data to be processed has no error, the first output control module starts output of the first data processing module so as to allow the second data processing module to execute the second data processing flow on the first data processing result; when the error check result indicates that the data to be processed has an error, the first output control module turns off the output of the first data processing module so as to prohibit the second data processing module from executing the second data processing flow on the first data processing result.

In a possible implementation manner of the first aspect of the present application, the first output control module is configured to switch between a first operation mode and a second operation mode, where the first output control module defaults on an output of the first data processing module in the first operation mode and turns off the output of the first data processing module when the error check result indicates that the data to be processed has an error, and the first output control module defaults off the output of the first data processing module in the second operation mode and turns on the output of the first data processing module when the error check result indicates that the data to be processed has no error.

In a possible implementation manner of the first aspect of the present application, when the priority of dynamic consumption of the system is greater than the priority of robustness of the system, the first output control module is configured to the first operation mode; the first output control module is configured to the second mode of operation when the priority of system dynamic consumption is less than the priority of system robustness.

In a possible implementation manner of the first aspect of the present application, when the error checking method is applied to data transmission of an intelligent terminal device, the first output control module is configured to the first working mode; when the error checking method is applied to data transmission of a data center, the first output control module is configured to be in the second working mode.

In a second aspect, embodiments of the present application further provide a computer device, the computer device including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing a method according to any one of the implementations of any one of the above aspects when the computer program is executed.

In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fifth aspect, the present application provides an error checking apparatus for high-speed data transmission. The error checking device includes: the first data processing module is used for executing a first data processing flow to the data to be processed to obtain a first data processing result, wherein the data processing flow associated with the data to be processed comprises the steps of executing the first data processing flow first and then executing a second data processing flow to the execution result of the first data processing flow; the second data processing module is used for executing the second data processing flow; the error checking module is used for executing an error checking flow to the data to be processed to obtain an error checking result, wherein the first data processing module executes the first data processing flow to the data to be processed and the error checking module executes the error checking flow to the data to be processed at least partially synchronously, and the expected processing delay of the first data processing module executing the first data processing flow is larger than the expected processing delay of the error checking module executing the error checking flow; and the first output control module is used for switching on or switching off the output from the first data processing module to the second data processing module according to the error checking result provided by the error checking module.

In a possible implementation manner of the fifth aspect of the present application, when the error check result indicates that the data to be processed has no error, the first output control module starts output of the first data processing module to the second data processing module so as to allow the second data processing module to perform the second data processing flow on the first data processing result; when the error check result indicates that the data to be processed has an error, the first output control module turns off the output from the first data processing module to the second data processing module so as to prohibit the second data processing module from executing the second data processing flow on the first data processing result.

In a possible implementation manner of the fifth aspect of the present application, the first output control module is configured to switch between a first operation mode and a second operation mode, wherein the first output control module turns on an output of the first data processing module to the second data processing module by default in the first operation mode and turns off the output of the first data processing module to the second data processing module when the error check result indicates that the data to be processed has an error, and turns off the output of the first data processing module to the second data processing module by default in the second operation mode and turns on the output of the first data processing module to the second data processing module when the error check result indicates that the data to be processed has no error.

In a possible implementation manner of the fifth aspect of the present application, when the priority of the dynamic consumption of the system is greater than the priority of the robustness of the system, the first output control module is configured to the first operation mode; the first output control module is configured to the second mode of operation when the priority of system dynamic consumption is less than the priority of system robustness.

In a possible implementation manner of the fifth aspect of the present application, the error checking module is further configured to: when the error check result indicates that the data to be processed has an error, the first data processing module is interrupted to execute the first data processing flow on the data to be processed and correct the data to be processed to obtain error-corrected data to be processed, and the error check device further comprises: a first data selection module for: and when the error check result indicates that the data to be processed has errors, sending the data to be processed after error correction to the first data processing module so that the first data processing module starts to execute the first data processing flow on the data to be processed after error correction.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is an application scenario for data verification in high-speed data transmission;

fig. 2 is a schematic flow chart of an error checking method for high-speed data transmission according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an error checking device for high-speed data transmission according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another implementation of the error checking apparatus shown in FIG. 3 according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of the application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

Fig. 1 is an application scenario for performing data verification in high-speed data transmission. As shown in fig. 1, the basic flow of sending a target packet from a sending end to a receiving end includes: in step S102, the transmitting end encodes the original data to generate verification information; in step S104, the transmitting end transmits the verification information together with the original data through the communication channel; in step S106, the receiving end decodes the received verification information; in step S108, the receiving end detects the received data according to the decoded verification information and corrects the error. Here, the transmitting end and the receiving end need to perform encoding and decoding for error checking, respectively. For example, the transmitting end and the receiving end may be both of high-speed data transmission based on a SERializer-deserializer (SERializer/DESerializer, SERDES). As another example, the sender and receiver may be interconnected devices that employ a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe) standard protocol. Among them, a communication channel or a communication link for data transmission between a transmitting end and a receiving end may have factors such as channel noise, damage, distortion, etc., which may cause errors in messages, data, etc., transmitted through the communication channel. In order to ensure the efficiency and the correctness of data transmission, a transmitting end encodes the original data, generates check information and transmits the check information and the original data together through a communication channel. The receiving end detects and corrects the error code word according to the check information through the corresponding decoding module. With the development of communication technology, the transmission rate and the transmission data volume are increasingly increased, more complex and diversified various data verification algorithms are presented, and the logic of the encoding and decoding modules for error verification is increasingly complex, and the processing delay is also increasingly large. In practical applications, a multi-level error checking mechanism is also needed, for example, multiple communication protocols and requirements of interconnection standards may need to be considered, and a decoding module for providing a response is needed at a receiving end and performs decoding operation, which greatly increases transmission delay of the system. The following describes in detail how the error checking method, medium and device for high-speed data transmission provided by the embodiment of the application ensure the efficiency and correctness of data transmission and simultaneously control the influence of error checking at the receiving end on the transmission delay of the system.

Fig. 2 is a flow chart of an error checking method for high-speed data transmission according to an embodiment of the present application. As shown in fig. 2, the error checking method includes the following steps.

Step S210: obtaining data to be processed, wherein the data processing flow associated with the data to be processed comprises the steps of executing a first data processing flow and then executing a second data processing flow on the execution result of the first data processing flow.

Step S220: and executing the first data processing flow on the data to be processed to obtain the first data processing result.

Step S230: performing an error check procedure on the data to be processed to obtain an error check result at least before the first data processing result is obtained, and allowing the second data processing procedure to be performed on the first data processing result when the error check result indicates that the data to be processed has no error, and prohibiting the second data processing procedure to be performed on the first data processing result when the error check result indicates that the data to be processed has an error, wherein the performing of the first data processing procedure on the data to be processed and the performing of the error check procedure on the data to be processed are performed at least partially in synchronization, and an expected processing delay of the first data processing procedure is greater than an expected processing delay of the error check procedure.

Referring to the above steps, in the application where the data to be processed may be high-speed data transmission, the receiving end receives the network message, the network data, and so on. And the transmitting end transmits the verification information for data verification and the original data together to the receiving end when transmitting. For example, the transmitting end and the receiving end may be both of high-speed data transmission based on a SERializer-deserializer (SERializer/DESerializer, SERDES). As another example, the sender and receiver may be interconnected devices that employ a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe) standard protocol. In data transmission applications, such as SERDES systems or interface interconnection between wafers, a data encoding scheme is used at a transmitting end to generate a check code for checking errors possibly occurring in data transmission or data storage, the check code is transmitted as additional information together with data, and then a data decoding scheme is used at a receiving end to perform error detection and correction. This allows control of transmission errors and error recovery of additional information sent with the data to reduce bit error rate. Examples of data checking algorithms may be e.g. cyclic redundancy check (cyclic redundancy check, CRC), forward error correction (forward error correction, FEC), automatic retransmission request (Automatic Repeat Request, ARQ), etc. And executing a data processing flow associated with the data to be processed at the receiving end, such as performing flow matching, flow control and the like on network message data, and executing a specific operation formula, algorithm and the like. As described above, in the data transmission process, there may be errors in the data to be processed obtained in step S210 due to factors such as channel noise, corruption, and distortion, and in order to ensure that the data processing procedure associated with the data to be processed can be performed correctly, error detection and correction are required in combination with the check information. In terms of error detection and correction of the data to be processed, a decoding scheme corresponding to the encoding scheme used by the transmitting end is required, and a multi-level error checking mechanism may be required, including considering the requirements of various communication protocols and interconnection standards. For this purpose, after the data to be processed is obtained in step S210, next, in step S220, the first data processing flow is performed on the data to be processed to obtain the first data processing result. Here, the first data processing flow is a part of a data processing flow associated with the data to be processed, and the data processing flow associated with the data to be processed includes executing the first data processing flow first and then executing the second data processing flow on the execution result of the first data processing flow. Thus, the first data processing flow executed at step S220 is a part of the data processing flow associated with the data to be processed that was originally executed. In a possible implementation, the portion that is initially executed may be determined as the first data processing flow executed in step S220 by parsing a data processing flow associated with the data to be processed, for example, parsing a code, logic, algorithm, model, etc. In another possible embodiment, the data processing procedure associated with the data to be processed may be a standardized procedure or have a reference procedure. For example, in applications related to high-speed data transmission, such as SERDES systems, inter-chip interface, data centers, and intelligent network cards, a standardized or normalized data processing flow is generally used to perform operations such as flow table matching, image processing, data compression, and the like. It is thus possible to conveniently determine a portion that is initially executed from these standardized flows or reference flows as the first data processing flow executed at step S220.

In step S220, the first data processing procedure is performed on the data to be processed to obtain the first data processing result. Associated with step S220 is step S230, wherein, at step S230, at least before the first data processing result is obtained, an error check result is obtained by performing an error check procedure on the data to be processed, and the second data processing procedure is permitted to be performed on the first data processing result when the error check result indicates that there is no error in the data to be processed, and the second data processing procedure is prohibited from being performed on the first data processing result when the error check result indicates that there is an error in the data to be processed. Wherein executing the first data processing flow on the data to be processed and executing the error checking flow on the data to be processed are performed at least partially in synchronization, and an expected processing delay of the first data processing flow is greater than an expected processing delay of the error checking flow. It should be understood that the operation in step S220, that is, performing the first data processing procedure on the data to be processed to obtain the first data processing result, and the operation in step S230, that is, performing the error checking procedure on the data to be processed to obtain the error checking result, are performed at least partially in synchronization. Therefore, the operation of step S230 (performing an error check flow on the data to be processed) is not started until the operation of step S220 (performing the first data processing flow on the data to be processed) is completed; but the operation of step S220 (the first data processing flow is performed on the data to be processed) and the operation of step S230 (the error checking flow is performed on the data to be processed) are performed at least partially in synchronization. In some examples, the first data processing flow is started to be performed on the data to be processed and the error checking flow is started to be performed on the data to be processed at the same time or almost the same time. For example, data to be processed may be simultaneously input to a module for performing the first data processing flow on the data to be processed and another module for performing an error checking flow on the data to be processed. In some examples, the start time of performing the first data processing procedure on the data to be processed may be the same as the start time of performing an error checking procedure on the data to be processed, or nearly the same (e.g., within a certain range of difference). Performing an error check procedure on the data to be processed to obtain an error check result means that any suitable error check mechanism, such as a multi-level error check mechanism, may be used to perform data check on the data to be processed. Based on an error check result obtained by performing an error check process on the data to be processed, it can be determined whether an error such as an error code or the like exists in the data to be processed. And allowing the second data processing flow to be executed on the first data processing result when the error check result indicates that the data to be processed has no error, namely, continuing other parts, relative to the first data processing flow, of the data processing flow associated with the data to be processed. And prohibiting the second data processing flow from being executed on the first data processing result when the error check result indicates that the data to be processed has an error, so that the data to be processed, of which the error is detected, is prevented from being used for other parts, relative to the first data processing flow, of the data processing flows associated with the data to be processed. On the one hand, on the basis of whether the error exists in the data to be processed indicated by the error checking result, the data to be processed is not used for subsequent processing when the error code is found, so that the efficiency and the correctness of data transmission are ensured; on the other hand, performing the first data processing flow on the data to be processed and performing the error checking flow on the data to be processed are performed at least partly in synchronization, which means that the first data processing flow on the data to be processed may be started without waiting for the execution of the error checking flow on the data to be processed to be completed in its entirety, and in some examples, the first data processing flow on the data to be processed may be started while the execution of the error checking flow on the data to be processed is started. Considering that the probability of error found by data checking at the receiving end is generally lower, that is, there is no error as a result of error checking on the received data with a higher probability, and once the error found in the received data is found, error correction is required and the first data processing flow is started by using the data after error correction, the first data processing flow is executed on the data to be processed and the error checking flow is executed on the data to be processed at least partially synchronously, so that the overall delay of the system can be reduced.

Further, the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow. Here, for specific data to be processed, the actual processing delay of each of the first data processing flow and the error checking flow is affected by factors such as data bit width, algorithm, logic, and the like. However, the expected processing delay of the first data processing flow, or the range of variation of the processing delay caused by the execution of the first data processing flow, such as the maximum possible processing delay and the minimum possible processing delay, may be determined in advance. Similarly, the expected processing delay of the error checking procedure, or the range of variation of the processing delay caused by performing the error checking procedure, such as the maximum possible processing delay and the minimum possible processing delay, may be determined in advance. In some examples, the minimum possible processing delay of the first data processing flow may be regarded as the expected processing delay of the first data processing flow and the maximum possible processing delay of the error checking flow may be regarded as the expected processing delay of the error checking flow, thus, when the relation that the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow is satisfied, this means that the minimum possible processing delay of the first data processing flow is greater than the maximum possible processing delay of the error checking flow. In other examples, the expected processing delays for each of the first data processing flow and the error checking flow may be calculated using mathematical expectations, median, or any suitable mathematical model, algorithm. When the relation that the expected processing delay of the first data processing procedure is larger than the expected processing delay of the error checking procedure is satisfied, the first data processing procedure is executed on the data to be processed and the error checking procedure is executed on the data to be processed at least partially synchronously, which means that the error checking procedure on the data to be processed may be completed before the execution of the first data processing procedure on the data to be processed is completed or before the execution of all the first data processing procedure on the data to be processed is completed. In most cases, that is, with a higher probability, the error check result indicates that there is no error, so that delay caused by waiting for the first data processing flow to restart after the error check flow is completed is avoided; and under the lower probability, the error check result indicates that an error exists, and the process of executing the first data processing flow on the data to be processed is generally still in the process of executing the first data processing flow on the data to be processed, the process of executing the first data processing flow on the data to be processed can be interrupted, and the process of executing the first data processing flow can be restarted by using the data after error correction, so that the lost data processing time is from the start of executing the first data processing flow on the data to be processed until the process of executing the error check on the data to be processed obtains the error check result. By determining that the expected processing delay of the first data processing procedure is greater than the expected processing delay of the error checking procedure in advance, when the error checking procedure is performed on the data to be processed to obtain an error checking result, the first data processing procedure is generally not completely performed, so that the execution of the second data processing procedure on the first data processing result can be timely prohibited, and other parts, relative to the first data processing procedure, of the data processing procedures associated with the data to be processed, of which the error is detected are avoided. In other words, when a relation that the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow is satisfied, a characteristic that the execution of the first data processing flow on the data to be processed and the execution of the error checking flow on the data to be processed are at least partially synchronized is combined, and in general, the completion of the error checking flow is already performed before the execution of the first data processing flow is completed, so that the execution of the second data processing flow on the first data processing result or the execution of the second data processing flow on the first data processing result can be selectively permitted. The error checking method for high-speed data transmission shown in fig. 2 at least partially synchronizes the execution of the first data processing flow on the data to be processed and the execution of the error checking flow on the data to be processed, so that the data processing is prevented from being started after the data checking is completely completed, and the overall delay of the system is reduced; in addition, for the case of errors such as error codes, the expected processing delay of the first data processing flow is larger than the expected processing delay of the error checking flow, so that timely error detection is effectively realized, the follow-up flow is forbidden to be performed by the data with the detected errors, and the efficiency and the correctness of data transmission are ensured.

In one possible implementation, the start time of the first data processing procedure performed on the data to be processed is the same as the start time of the error checking procedure performed on the data to be processed. As mentioned above, the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow. Therefore, when the start time of the execution of the first data processing flow on the data to be processed is the same as the start time of the execution of the error checking flow on the data to be processed, this means that the execution of the first data processing flow on the data to be processed and the execution of the error checking flow on the data to be processed are simultaneously started, and thus, it means that the completion of the error checking flow is already performed before the completion of the execution of the first data processing flow, so that the execution of the second data processing flow on the first data processing result can be selectively permitted or the execution of the second data processing flow on the first data processing result can be prohibited. In this way, by synchronously starting the first data processing flow for the data to be processed and starting the error checking flow for the data to be processed, the data processing is prevented from being started after the data checking is completely completed, so that the overall delay of the system is reduced; in addition, under the condition of errors such as error codes, the method effectively realizes timely error detection and prohibits subsequent processes from being carried out by using the data with the detected errors, and ensures the efficiency and the correctness of data transmission.

In one possible implementation, the completion time of performing the first data processing procedure on the data to be processed is later than the completion time of performing the error checking procedure on the data to be processed. The completion of the error checking procedure is performed before the completion of the first data processing procedure is performed, so that the execution of the second data processing procedure on the first data processing result can be selectively permitted or inhibited. Therefore, timely error detection is effectively realized, follow-up flow is forbidden to be carried out by using the data with the detected error, and the efficiency and the correctness of data transmission are ensured.

In one possible implementation, the difference of the expected processing delay of the first data processing flow minus the expected processing delay of the error checking flow is greater than a delay margin threshold, the delay margin threshold being determined based on at least one of: data bit width, algorithm complexity, iteration number, polynomial. Here, as the delay margin threshold as a quantization index for evaluating whether the relationship that the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow is satisfied, various possible error checking mechanisms that need to be adopted in practical application and other factors that may affect the processing delay may be considered. The estimation of the processing delay is mainly determined according to the characteristics of the data to be processed and a data verification algorithm. Thus, the delay margin threshold is determined based on at least one of: data bit width, algorithm complexity, iteration number, polynomial.

In one possible implementation manner, the error checking method further includes: when the error check result indicates that the data to be processed has errors, correcting the data to be processed to obtain data to be processed after error correction, and then interrupting the execution of the first data processing flow on the data to be processed and starting the execution of the first data processing flow on the data to be processed after error correction. When a relation that an expected processing delay of the first data processing flow is larger than an expected processing delay of the error checking flow is satisfied, a characteristic that the first data processing flow is executed on the data to be processed and the error checking flow is executed on the data to be processed are at least partially synchronized is combined, and in general, the error checking flow is executed before the first data processing flow is executed, so that the second data processing flow can be selectively allowed to be executed on the first data processing result or the second data processing flow can be forbidden to be executed on the first data processing result. In this way, the error checking result indicates that there is an error, and the first data processing flow may be interrupted for the data to be processed and restarted with the error-corrected data, where the lost data processing time is from the start of the first data processing flow for the data to be processed until the error checking result is obtained by the error checking flow for the data to be processed. In some examples, the first data processing procedure may be started to be performed on the data to be processed and the error checking procedure may be started to be performed on the data to be processed synchronously, so that the interruption of the first data processing procedure to be performed on the data to be processed may be conveniently implemented by, for example, a data enabling switch, a data enabling controller, etc., and the execution of the first data processing procedure may be restarted by a data selector, etc., with the corrected data, which means that error detection and correction may be implemented with only very limited logic and limited dynamic power consumption. Moreover, as described above, in most cases, that is, with a high probability, the error check result indicates that there is no error, thus avoiding delay caused by waiting for the first data processing flow to restart after the error check flow is completed entirely. Therefore, by performing error detection operation, that is, performing an error checking procedure on the data to be processed to obtain an error checking result, at least partially in synchronization with the first data processing procedure, overall system delay can be reduced, and performing the first data processing procedure is interrupted by error correction operation, thereby realizing timely error correction.

In one possible implementation, the data processing procedure associated with the data to be processed includes sequentially performing 1 st to nth steps of N steps, where N is a positive integer greater than 1, and wherein the first data processing procedure includes sequentially performing 1 st to kth steps of the N steps, where K is a positive integer greater than 1 and less than N, an expected processing delay from 1 st to kth steps is greater than an expected processing delay of the error checking procedure, and an expected processing delay from 1 st to kth-1 st steps is not greater than an expected processing delay of the error checking procedure. It should be appreciated that for the first data processing flow and the division of the modules for executing the first data processing flow, it is necessary to meet the requirement that the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow, that is, to ensure a sufficient delay margin. Moreover, on the premise of providing enough delay margin, the processing details of the first data processing flow should be simplified as much as possible, for example, fewer functional modules or steps are included, which is helpful for early detection of errors and correction of errors, and the loss of restarting the first data processing flow is also small. For this purpose, the first data processing flow may be determined by splitting the data processing flow associated with the data to be processed into sequentially performing the 1 st to nth steps and then based on the expected processing delays of the respective steps, the first data processing flow may include sequentially performing the 1 st to kth steps. Wherein the expected processing delay from step 1 to step K is greater than the expected processing delay of the error checking procedure and the expected processing delay from step 1 to step K-1 is not greater than the expected processing delay of the error checking procedure. In this way, simplifying the processing details of the first data processing flow is achieved, which is conducive to early detection of errors and correction of errors, and the loss of restarting the first data processing flow is also small.

In one possible implementation, the error checking procedure includes performing at least one of the following data checking algorithms: cyclic redundancy check (cyclic redundancy check, CRC) algorithm, forward error correction (forward error correction, FEC) algorithm, automatic repeat request (Automatic Repeat Request, ARQ) algorithm. Generally, the cyclic redundancy check algorithm and the forward error correction algorithm have higher probability of detecting errors, and the automatic retransmission request algorithm has lower probability of detecting errors.

In one possible implementation, the error checking procedure includes sequentially executing a plurality of first error checking algorithms and then executing a plurality of second error checking algorithms in parallel, each of the plurality of first error checking algorithms having a greater probability of error than a respective probability of error of the plurality of second error checking algorithms. In some embodiments, when any one of the plurality of first error checking algorithms indicates that the data to be processed has an error or any one of the plurality of second error checking algorithms indicates that the data to be processed has an error, the error checking process indicates that the data to be processed has an error, and execution of the first data processing process on the data to be processed is discontinued. In some embodiments, the plurality of first error checking algorithms includes a cyclic redundancy check algorithm and a forward error correction algorithm, and the plurality of second error checking algorithms includes an automatic repeat request algorithm. For the situation that multiple error checking mechanisms exist, for example, multiple levels of error checking mechanisms, such as multiple communication protocols, interconnection standards and the like, multiple error checking algorithms can be combined in a serial-parallel mode, and classified according to error probability, the error checking algorithm with lower error probability is improved in speed in a multi-path parallel mode, and the error checking algorithm with higher error probability is improved in actual control of each error checking algorithm in a serial mode. Specifically, a plurality of first error-checking algorithms, each of which has a greater probability of error than a respective probability of error of a plurality of second error-checking algorithms, are executed serially and then a plurality of second error-checking algorithms are executed in parallel. In this way, control may be applied to the plurality of first error checking algorithms separately, e.g. establishing separate modules and control logic, while the plurality of second error checking algorithms may be executed in parallel by simplified logic. Further, when any one of the first error checking algorithms indicates that the data to be processed has an error or any one of the second error checking algorithms indicates that the data to be processed has an error, it means that at least one error exists in the data to be processed, or at least one error checking mechanism detects that the data to be processed has an error, so that the execution of the first data processing flow on the data to be processed can be interrupted in time, which is helpful to reduce delay of error checking as a whole and ensure timely discovery of errors.

In one possible implementation manner, the error checking method is applied to an error checking device, and the error checking device includes a first data processing module, a second data processing module, an error checking module and a first output control module, where the first data processing module is configured to execute the first data processing procedure on the data to be processed to obtain the first data processing result, the second data processing module is configured to execute the second data processing procedure on the output of the first data processing module, the error checking module is configured to execute the error checking procedure on the data to be processed to obtain the error checking result, and the first output control module is configured to turn on or off the output of the first data processing module according to the error checking result provided by the error checking module. Therefore, through the above module design, for example, the first output control module controls the whole data flow, and through turning on or off the output of the first data processing module, the error detected data is prevented from being used for the subsequent flow, and the accuracy of data transmission is ensured.

In a possible implementation manner, when the error check result indicates that the data to be processed has no error, the first output control module starts output of the first data processing module so as to allow the second data processing module to execute the second data processing flow on the first data processing result; when the error check result indicates that the data to be processed has an error, the first output control module turns off the output of the first data processing module so as to prohibit the second data processing module from executing the second data processing flow on the first data processing result. Therefore, the data with errors detected is prevented from being used for subsequent processes, and the correctness of data transmission is ensured.

In one possible implementation, the first output control module is configured to switch between a first operation mode and a second operation mode, wherein the first output control module turns on the output of the first data processing module by default in the first operation mode and turns off the output of the first data processing module when the error check result indicates that the data to be processed has an error, and the first output control module turns off the output of the first data processing module by default in the second operation mode and turns on the output of the first data processing module when the error check result indicates that the data to be processed has no error. Here, in combination with the above-described module design, the first output control module turns on or off the output of the first data processing module, thereby exerting control over the entire data stream. As mentioned above, the expected processing delay of the first data processing flow is greater than the expected processing delay of the error checking flow. When an abnormal condition occurs, such as a device failure, aging, etc., the substantial processing delay of the error checking procedure may be significantly greater than the expected processing delay of the error checking procedure, such that the substantial processing delay of the error checking procedure may occur to be greater than the substantial processing delay of the first data processing procedure. For this purpose, an optimization can be performed by means of a first and a second operating mode of the first output control module. In particular, on the one hand, if the first output control module is in the first operating mode, also called the normally open mode, this means that it is turned on by default and is turned off when an error is found to be present. In consideration of the lower probability of error occurrence, the first output control module is turned off for a smaller number of times, so that dynamic power consumption can be reduced. When the first output control module faces an abnormal situation, the system robustness may be reduced because the first output control module defaults to turn on the output of the first data processing module in the first operation mode. On the other hand, if the first output control module is in the second mode of operation, also called normally off mode, this means that it is turned off by default and turned on when no errors are found. When the first output control module faces to an abnormal condition, the first output control module is turned off by default in the second working mode, so that the robustness of the system can be improved, but the first output control module is turned off for a plurality of times, and the dynamic power consumption can be increased. Therefore, through the configuration between the first working mode and the second working mode of the first output control module, the system requirement can be combined for optimization, and the abnormal situation can be overcome. In some embodiments, the first output control module is configured to the first mode of operation when the priority of system dynamic consumption is greater than the priority of system robustness; the first output control module is configured to the second mode of operation when the priority of system dynamic consumption is less than the priority of system robustness. In some embodiments, when the error checking method is applied to data transmission of an intelligent terminal device, the first output control module is configured to the first operation mode; when the error checking method is applied to data transmission of a data center, the first output control module is configured to be in the second working mode. In this way, flexible configuration of the first output control module according to system requirements and application scenarios is achieved. For a system with high integration level, small volume and high heat dissipation requirement of the transistor, the dynamic power consumption can be preferentially reduced, for example, intelligent terminal equipment such as a mobile phone, a vehicle-mounted chip and the like, so that the first output control module is configured into the first working mode. For systems with high stability requirements, such as large data centers, such as data processing modules, robustness may be prioritized, so that the first output control module is configured in the second operating mode.

Fig. 3 is a schematic diagram of an error checking device for high-speed data transmission according to an embodiment of the present application. As shown in fig. 3, the error checking apparatus includes: a first data processing module 310, configured to execute a first data processing procedure on the data to be processed 302 to obtain a first data processing result, where the data processing procedure associated with the data to be processed 302 includes executing the first data processing procedure first and then executing a second data processing procedure on the execution result of the first data processing procedure; a second data processing module 320, configured to execute the second data processing flow; an error checking module 330, configured to perform an error checking procedure on the data to be processed 302 to obtain an error checking result, where the first data processing module 310 performs the first data processing procedure on the data to be processed 302 and the error checking module 330 performs the error checking procedure on the data to be processed 302 at least partially in synchronization, and an expected processing delay of the first data processing module 310 performing the first data processing procedure is greater than an expected processing delay of the error checking module 330 performing the error checking procedure; and a first output control module 340 for turning on or off the output of the first data processing module 310 to the second data processing module 320 according to the error check result provided by the error check module 330.

The error checking device for high-speed data transmission shown in fig. 3, in which the first data processing module 310 executes the first data processing flow on the data to be processed 302 and the error checking module 330 executes the error checking flow on the data to be processed 302 at least partially synchronously, avoids starting data processing after waiting for the complete completion of data checking, and thus reduces the overall delay of the system; in addition, in the case of errors such as errors, the expected processing delay of the first data processing module 310 for executing the first data processing flow is greater than the expected processing delay of the error checking module 330 for executing the error checking flow, and the first output control module 340 is configured to turn on or off the output from the first data processing module 310 to the second data processing module 320 according to the error checking result provided by the error checking module 330, so that timely error detection is effectively realized, and subsequent flows with the data with detected errors are prohibited, thereby ensuring efficiency and correctness of data transmission.

In a possible implementation, when the error check result indicates that the data to be processed has no error, the first output control module 340 turns on the output of the first data processing module 310 to the second data processing module 320 so as to allow the second data processing module 320 to perform the second data processing flow on the first data processing result; when the error check result indicates that the data to be processed has an error, the first output control module 340 turns off the output of the first data processing module 310 to the second data processing module 320 so as to prohibit the second data processing module 320 from executing the second data processing flow on the first data processing result. Therefore, the data with errors detected is prevented from being used for subsequent processes, and the correctness of data transmission is ensured.

In a possible implementation, the first output control module 340 is configured to switch between a first operation mode and a second operation mode, wherein the first output control module 340 turns on the output of the first data processing module 310 to the second data processing module 320 by default in the first operation mode and turns off the output of the first data processing module 310 to the second data processing module 320 when the error check result indicates that the data to be processed has an error, and the first output control module 340 turns off the output of the first data processing module 310 to the second data processing module 320 by default in the second operation mode and turns on the output of the first data processing module 310 to the second data processing module 320 when the error check result indicates that the data to be processed has no error. In this way, flexible configuration of the first output control module 340 according to system requirements and application scenarios is achieved.

In one possible implementation, the first output control module 340 is configured to the first operating mode when the priority of system dynamic consumption is greater than the priority of system robustness; the first output control module 340 is configured to the second mode of operation when the priority of system dynamic consumption is less than the priority of system robustness. In this way, flexible configuration of the first output control module 340 according to system requirements and application scenarios is achieved.

FIG. 4 is a schematic diagram of another embodiment of the error checking apparatus shown in FIG. 3 according to an embodiment of the present application. The error checking device shown in fig. 4 is based on the error checking device shown in fig. 3, and the error checking module 330 is further configured to: when the error check result indicates that the data 302 to be processed has an error, the first data processing module 310 is interrupted to execute the first data processing procedure on the data 302 to be processed and to perform error correction on the data 302 to be processed to obtain error-corrected data to be processed. The error checking apparatus shown in fig. 4 further includes: a first data selection module 350, configured to: when the error check result indicates that the data 302 to be processed has an error, the data to be processed after error correction is sent to the first data processing module 310 so that the first data processing module 310 starts to execute the first data processing flow on the data to be processed after error correction.

In this way, the error checking result indicates that there is an error, and the first data processing flow may be interrupted for the data to be processed and restarted with the error-corrected data, where the lost data processing time is from the start of the first data processing flow for the data to be processed until the error checking result is obtained by the error checking flow for the data to be processed. In some examples, the first data processing procedure may be started to be performed on the data to be processed and the error checking procedure may be started to be performed on the data to be processed synchronously, so that the interruption of the first data processing procedure to be performed on the data to be processed may be conveniently implemented by, for example, a data enabling switch, a data enabling controller, etc., and the execution of the first data processing procedure may be restarted by a data selector, etc., with the corrected data, which means that error detection and correction may be implemented with only very limited logic and limited dynamic power consumption. Moreover, as described above, in most cases, that is, with a high probability, the error check result indicates that there is no error, thus avoiding delay caused by waiting for the first data processing flow to restart after the error check flow is completed entirely. Therefore, by performing error detection operation, that is, performing an error checking procedure on the data to be processed to obtain an error checking result, at least partially in synchronization with the first data processing procedure, overall system delay can be reduced, and performing the first data processing procedure is interrupted by error correction operation, thereby realizing timely error correction.

Fig. 5 is a schematic structural diagram of a computing device according to an embodiment of the present application, where the computing device 500 includes: one or more processors 510, a communication interface 520, and a memory 530. The processor 510, communication interface 520, and memory 530 are interconnected by a bus 540. Optionally, the computing device 500 may further include an input/output interface 550, where the input/output interface 550 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 500 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in embodiments of the present application; the processor 510 can also be used to implement some or all of the operational steps of the method embodiments described above in connection with the embodiments of the present application. For example, specific implementations of the computing device 500 performing various operations may refer to specific details in the above-described embodiments, such as the processor 510 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in an embodiment of the present application, the computing device 500 may be used to implement some or all of the functionality of one or more components of the apparatus embodiments described above, and the communication interface 520 may be used in particular for communication functions and the like necessary to implement the functionality of such apparatus, components, and the processor 510 may be used in particular for processing functions and the like necessary to implement the functionality of such apparatus, components.

It should be appreciated that the computing device 500 of fig. 5 may include one or more processors 510, and that the plurality of processors 510 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the plurality of processors 510 may constitute a processor sequence or processor array, or that the plurality of processors 510 may be separated into primary and secondary processors, or that the plurality of processors 510 may have different architectures such as employing heterogeneous computing architectures. In addition, the computing device 500 shown in FIG. 5, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 500 may include more or fewer components than shown in fig. 5, or combine certain components, or split certain components, or have a different arrangement of components.

Processor 510 may take many specific forms, for example, processor 510 may include one or more combinations of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), and embodiments of the present application are not limited in this respect. Processor 510 may also be a single-core processor or a multi-core processor. Processor 510 may be a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 510 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 520 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.

The memory 530 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 530 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 530 may also be used to store program code and data such that processor 510 invokes the program code stored in memory 530 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 500 may contain more or fewer components than shown in FIG. 5, or may have a different configuration of components.

The bus 540 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 540 may be classified into an address bus, a data bus, a control bus, and the like. The bus 540 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 5 for clarity of illustration, but does not represent only one bus or one type of bus.

The method and the device provided by the embodiment of the application are based on the same inventive concept, and because the principle of solving the problem by the method and the device is similar, the embodiment, the implementation, the example or the implementation of the method and the device can be mutually referred, and the repetition is not repeated. Embodiments of the present application also provide a system comprising a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), implement the method steps of the method embodiments described above. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the application may be implemented, in whole or in part, in software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the embodiments of the application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. The present application is also intended to include such modifications and alterations if they come within the scope of the claims and the equivalents thereof.

Claims

1. An error checking method for high-speed data transmission, the error checking method comprising:

obtaining data to be processed, wherein a data processing flow associated with the data to be processed comprises the steps of executing a first data processing flow and then executing a second data processing flow on an execution result of the first data processing flow;

executing the first data processing flow on the data to be processed to obtain the first data processing result;

Performing an error check procedure on the data to be processed to obtain an error check result at least before the first data processing result is obtained, and allowing the second data processing procedure to be performed on the first data processing result when the error check result indicates that the data to be processed has no error, and prohibiting the second data processing procedure to be performed on the first data processing result when the error check result indicates that the data to be processed has an error, wherein the performing of the first data processing procedure on the data to be processed and the performing of the error check procedure on the data to be processed are performed at least partially in synchronization, and an expected processing delay of the first data processing procedure is greater than an expected processing delay of the error check procedure.

2. The error checking method according to claim 1, wherein a start time of performing the first data processing flow on the data to be processed is the same as a start time of performing the error checking flow on the data to be processed.

3. The error checking method according to claim 1, wherein a completion time of performing the first data processing flow on the data to be processed is later than a completion time of performing the error checking flow on the data to be processed.

4. The error checking method of claim 1, wherein a difference of an expected processing delay of the first data processing flow minus an expected processing delay of the error checking flow is greater than a delay margin threshold, the delay margin threshold being determined based on at least one of: data bit width, algorithm complexity, iteration number, polynomial.

5. The error checking method according to claim 1, characterized in that the error checking method further comprises:

when the error check result indicates that the data to be processed has errors, correcting the data to be processed to obtain data to be processed after error correction, and then interrupting the execution of the first data processing flow on the data to be processed and starting the execution of the first data processing flow on the data to be processed after error correction.

6. The error checking method according to claim 1, wherein the data processing flow associated with the data to be processed includes sequentially performing 1 st to nth steps of N steps, N being a positive integer greater than 1, wherein the first data processing flow includes sequentially performing 1 st to kth steps of the N steps, K being a positive integer greater than 1 and less than N, an expected processing delay from 1 st to kth steps is greater than an expected processing delay of the error checking flow, and an expected processing delay from 1 st to kth-1 st steps is not greater than an expected processing delay of the error checking flow.

7. The error checking method of claim 1, wherein the error checking procedure comprises performing at least one of the following data checking algorithms: cyclic redundancy check algorithm, forward error correction algorithm, automatic retransmission request algorithm.

8. The error checking method of claim 1, wherein the error checking procedure comprises executing a plurality of first error checking algorithms in series followed by a plurality of second error checking algorithms in parallel, each of the plurality of first error checking algorithms having a greater probability of error than a respective probability of error of the plurality of second error checking algorithms.

9. The error checking method according to claim 8, wherein when any one of the plurality of first error checking algorithms indicates that the data to be processed has an error or any one of the plurality of second error checking algorithms indicates that the data to be processed has an error, the error checking flow indicates that the data to be processed has an error, and the execution of the first data processing flow on the data to be processed is interrupted.

10. The error checking method of claim 8, wherein the first plurality of error checking algorithms comprises a cyclic redundancy check algorithm and a forward error correction algorithm, and the second plurality of error checking algorithms comprises an automatic repeat request algorithm.

11. The error checking method according to claim 1, wherein the error checking method is applied to an error checking device, the error checking device includes a first data processing module, a second data processing module, an error checking module, and a first output control module, wherein the first data processing module is configured to perform the first data processing procedure on the data to be processed to obtain the first data processing result, the second data processing module is configured to perform the second data processing procedure on an output of the first data processing module, the error checking module is configured to perform the error checking procedure on the data to be processed to obtain the error checking result, and the first output control module is configured to turn on or off the output of the first data processing module according to the error checking result provided by the error checking module.

12. The error checking method according to claim 11, wherein when the error checking result indicates that the data to be processed is not erroneous, the first output control module turns on an output of the first data processing module so as to allow the second data processing module to execute the second data processing flow on the first data processing result; when the error check result indicates that the data to be processed has an error, the first output control module turns off the output of the first data processing module so as to prohibit the second data processing module from executing the second data processing flow on the first data processing result.

13. The error checking method of claim 11, wherein the first output control module is configured to switch between a first mode of operation in which the first output control module defaults to turn on the output of the first data processing module and turns off the output of the first data processing module when the error checking result indicates that the data to be processed has an error, and a second mode of operation in which the first output control module defaults to turn off the output of the first data processing module and turns on the output of the first data processing module when the error checking result indicates that the data to be processed has no error.

14. The error checking method of claim 13, wherein the first output control module is configured to the first mode of operation when a priority of system dynamic consumption is greater than a priority of system robustness; the first output control module is configured to the second mode of operation when the priority of system dynamic consumption is less than the priority of system robustness.

15. The error checking method according to claim 13, wherein when the error checking method is applied to data transmission of an intelligent terminal device, the first output control module is configured to the first operation mode; when the error checking method is applied to data transmission of a data center, the first output control module is configured to be in the second working mode.

16. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 15.

17. An error checking apparatus for high-speed data transmission, the error checking apparatus comprising:

The first data processing module is used for executing a first data processing flow to the data to be processed to obtain a first data processing result, wherein the data processing flow associated with the data to be processed comprises the steps of executing the first data processing flow first and then executing a second data processing flow to the execution result of the first data processing flow;

the second data processing module is used for executing the second data processing flow;

the error checking module is used for executing an error checking flow to the data to be processed to obtain an error checking result, wherein the first data processing module executes the first data processing flow to the data to be processed and the error checking module executes the error checking flow to the data to be processed at least partially synchronously, and the expected processing delay of the first data processing module executing the first data processing flow is larger than the expected processing delay of the error checking module executing the error checking flow; and

and the first output control module is used for switching on or switching off the output from the first data processing module to the second data processing module according to the error checking result provided by the error checking module.

18. The error checking apparatus of claim 17, wherein when the error checking result indicates that the data to be processed is not erroneous, the first output control module turns on output of the first data processing module to the second data processing module so as to allow the second data processing module to perform the second data processing flow on the first data processing result; when the error check result indicates that the data to be processed has an error, the first output control module turns off the output from the first data processing module to the second data processing module so as to prohibit the second data processing module from executing the second data processing flow on the first data processing result.

19. The error checking apparatus of claim 18, wherein the first output control module is configured to switch between a first mode of operation and a second mode of operation, wherein the first output control module defaults on output of the first data processing module to the second data processing module in the first mode of operation and turns off output of the first data processing module to the second data processing module when the error check result indicates that the data to be processed is in error, and wherein the first output control module defaults off output of the first data processing module to the second data processing module in the second mode of operation and turns on output of the first data processing module to the second data processing module when the error check result indicates that the data to be processed is not in error.

20. The error checking apparatus of claim 19, wherein the first output control module is configured to the first mode of operation when a priority of system dynamic consumption is greater than a priority of system robustness; the first output control module is configured to the second mode of operation when the priority of system dynamic consumption is less than the priority of system robustness.

21. The error checking apparatus of claim 17, wherein the error checking module is further configured to: when the error check result indicates that the data to be processed has errors, the first data processing module is interrupted to execute the first data processing flow on the data to be processed and error correction is carried out on the data to be processed to obtain error-corrected data to be processed,

the error checking apparatus further includes:

a first data selection module for: and when the error check result indicates that the data to be processed has errors, sending the data to be processed after error correction to the first data processing module so that the first data processing module starts to execute the first data processing flow on the data to be processed after error correction.