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CN116825162A - Sense amplifier and semiconductor memory - Google Patents

Sense amplifier and semiconductor memory Download PDF

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Publication number
CN116825162A
CN116825162A CN202210284403.8A CN202210284403A CN116825162A CN 116825162 A CN116825162 A CN 116825162A CN 202210284403 A CN202210284403 A CN 202210284403A CN 116825162 A CN116825162 A CN 116825162A
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CN
China
Prior art keywords
type transistor
coupled
voltage
drain
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210284403.8A
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Chinese (zh)
Inventor
周润发
季汝敏
杨宇
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202210284403.8A priority Critical patent/CN116825162A/en
Priority to PCT/CN2022/086401 priority patent/WO2023178743A1/en
Publication of CN116825162A publication Critical patent/CN116825162A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Amplifiers (AREA)

Abstract

The disclosure provides a sense amplifier and a semiconductor memory, wherein a first input end of a body bias adjusting module is coupled with a drain electrode of a first N-type transistor, a second input end of the body bias adjusting module is coupled with a drain electrode of a second N-type transistor, a first output end of the body bias adjusting module is coupled with a body end of a first P-type transistor, a second output end of the body bias adjusting module is coupled with a body end of a second P-type transistor, and a control end of the body bias adjusting module is coupled with an enabling signal. After receiving the enabling signal, the body bias adjusting module adjusts the body terminal voltage of the first P-type transistor and/or the body terminal voltage of the second P-type transistor according to the difference between the drain voltage of the first N-type transistor and the drain voltage of the second N-type transistor so as to adjust the body bias voltage of the first P-type transistor and/or the body bias voltage of the second P-type transistor, so that the threshold voltage of the first N-type transistor or the threshold voltage of the second N-type transistor is compensated, mismatch of the threshold voltages of the first N-type transistor and the second N-type transistor is reduced, and the voltage difference between the bit line and the complementary bit line is effectively amplified by the sense amplifier.

Description

Sense amplifier and semiconductor memory
Technical Field
The present disclosure relates to, but is not limited to, a sense amplifier and a semiconductor memory.
Background
A Sense Amplifier (SA) is an important component of a semiconductor memory, which is capable of amplifying a voltage difference between a Bit Line (BL) and a complementary Bit Line (BLB) to read data stored in a memory cell.
However, since there is a mismatch between devices in the sense amplifier, the sense amplifier cannot effectively amplify a voltage difference between the bit line and the complementary bit line, thereby causing erroneous read and write results in the data reading process.
Disclosure of Invention
The present disclosure provides a sense amplifier and a semiconductor memory for reducing mismatch between devices in the sense amplifier.
An embodiment of the present disclosure provides a sense amplifier including:
a first P-type transistor, the source of which is coupled to the first power terminal;
a second P-type transistor having a source coupled to the source of the first P-type transistor, a gate coupled to the drain of the first P-type transistor, and a drain coupled to the gate of the first P-type transistor;
a first N-type transistor, the drain electrode of which is coupled with the drain electrode of the first P-type transistor, and the source electrode of which is coupled with a second power supply end;
a second N-type transistor having a drain coupled to the drain of the second P-type transistor and a source coupled to the source of the first N-type transistor;
And the body bias adjusting module is used for responding to the enabling signal to compensate the difference of threshold voltages between the second N-type transistor and the first N-type transistor.
In some embodiments, the body bias adjustment module comprises:
the first input end of the first adjusting module is coupled with the second input end of the body bias adjusting module, the second input end of the first adjusting module is coupled with the first input end of the body bias adjusting module, the output end of the first adjusting module is the first output end of the body bias adjusting module, and the control end of the first adjusting module is coupled with the enabling signal;
the method is used for reducing the body terminal voltage of the first P-type transistor when the drain voltage of the first N-type transistor is larger than the drain voltage of the second N-type transistor so as to compensate the threshold voltage of the first N-type transistor.
In some embodiments, the first adjustment module comprises:
The first comparator is coupled with the second input end of the body bias adjusting module at the same direction input end, is coupled with the first input end of the body bias adjusting module at the opposite direction input end, is coupled with the first output end of the body bias adjusting module at the output end, and is coupled with the enabling signal at the control end.
In some embodiments, the body bias adjustment module comprises:
the first input end of the second adjusting module is coupled with the first input end of the body bias adjusting module, the second input end of the second adjusting module is coupled with the second input end of the body bias adjusting module, the output end of the second adjusting module is coupled with the second output end of the body bias adjusting module, and the control end of the second adjusting module is coupled with the enabling signal;
the method is used for reducing the body terminal voltage of the second P-type transistor when the drain voltage of the first N-type transistor is smaller than the drain voltage of the second N-type transistor so as to compensate the threshold voltage of the second N-type transistor.
In some embodiments, the second adjustment module comprises:
and the second comparator is coupled with the drain electrode of the first P-type transistor at the same direction input end, the drain electrode of the second P-type transistor at the opposite direction input end, the body end of the second P-type transistor at the output end and the enabling signal at the control end.
In some embodiments, further comprising:
and a control unit for controlling coupling between the bit line and the first N-type transistor and coupling between the complementary bit line and the second N-type transistor.
In some embodiments, the control unit includes a first control unit having a first end coupled to the bit line and a second end coupled to the drain of the first N-type transistor.
In some embodiments, the first control unit includes a first control transistor;
the source electrode of the first control transistor is used as the first end of the first control unit and is coupled with a bit line;
the drain of the first control transistor is used as a second end of the first control unit and is coupled with the drain of the first N-type transistor.
In some embodiments, the control unit includes a second control unit having a first end coupled to the complementary bit line and a second end coupled to the drain of the second N-type transistor.
In some embodiments, the second control unit includes a second control transistor;
the source electrode of the second control transistor is used as a first end of the second control unit and is coupled with the complementary bit line;
the drain electrode of the second control transistor is used as a second end of the second control unit and is coupled with the drain electrode of the second N-type transistor.
In some embodiments, further comprising:
and a third control unit, a first end of which is coupled with the first power supply end, and a second end of which is coupled with the source electrode of the first P-type transistor and is used for supplying voltage.
In some embodiments, the third control unit includes a third control transistor;
the source electrode of the first P-type transistor is used as the first end of the third control unit, the first power end is coupled, the drain electrode of the first P-type transistor is used as the second end of the third control unit, and the source electrode of the first P-type transistor is coupled.
In some embodiments, further comprising:
and a fourth control unit, the first end of which is coupled with the second power supply end, and the second end of which is coupled with the source electrode of the first N-type transistor and is used for supplying voltage.
In some embodiments, the fourth control unit includes a fourth control transistor;
the source electrode of the first N-type crystal is used as the first end of the fourth control unit, the second power end is coupled, the drain electrode of the first N-type crystal is used as the second end of the fourth control unit, and the source electrode of the first N-type crystal is coupled.
Another embodiment of the present disclosure provides a semiconductor memory including:
the sense amplifier described above.
The sensitive amplifier comprises a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor and a body bias adjusting module. The source electrode of the first P-type transistor is coupled with the first power supply end, the source electrode of the second P-type transistor is coupled with the source electrode of the first P-type transistor, the grid electrode is coupled with the drain electrode of the first P-type transistor, and the drain electrode is coupled with the grid electrode of the first P-type transistor. The drain electrode of the first N-type transistor is coupled with the drain electrode of the first P-type transistor, the source electrode of the first N-type transistor is coupled with the second power end, the drain electrode of the second N-type transistor is coupled with the drain electrode of the second P-type transistor, and the source electrode of the second N-type transistor is coupled with the source electrode of the first N-type transistor. The first input end of the body bias adjusting module is coupled with the drain electrode of the first N-type transistor, the second input end of the body bias adjusting module is coupled with the drain electrode of the second N-type transistor, the first output end of the body bias adjusting module is coupled with the body end of the first P-type transistor, the second output end of the body bias adjusting module is coupled with the body end of the second P-type transistor, and the control end of the body bias adjusting module is coupled with an enabling signal. After receiving the enabling signal, the body bias adjusting module adjusts the body terminal voltage of the first P-type transistor and/or the body terminal voltage of the second P-type transistor according to the difference between the drain voltage of the first N-type transistor and the drain voltage of the second N-type transistor so as to adjust the body bias voltage of the first P-type transistor and/or adjust the body bias voltage of the second P-type transistor, so that the threshold voltage of the first P-type transistor and/or the threshold voltage of the second P-type transistor is adjusted, the threshold voltage of the first N-type transistor or the threshold voltage of the second N-type transistor is further compensated, the mismatch between the threshold voltage of the first N-type transistor and the threshold voltage of the second N-type transistor is reduced, and a cross coupling circuit formed by the first P-type transistor and the second P-type transistor can effectively amplify the voltage difference between a bit line and a complementary bit line, and the accuracy of read data is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic circuit diagram of a sense amplifier;
FIG. 2 is a schematic circuit diagram of a sense amplifier according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of the operation of a sense amplifier provided in an embodiment of the present disclosure;
fig. 4 is a cross-sectional structure diagram of a P-type transistor according to an embodiment of the present disclosure;
fig. 5 is a schematic circuit diagram of a P-type transistor according to an embodiment of the disclosure.
Specific embodiments of the present disclosure have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
As shown in fig. 1, the sense amplifier includes a pair of PMOS transistors (a first PMOS transistor P11 and a second PMOS transistor P12) and a pair of NMOS transistors (a first NMOS transistor N11 and a second NMOS transistor N12), the first PMOS transistor P11 and the second PMOS transistor P12 are cross-coupled, a source of the first PMOS transistor P11 is coupled to the first power supply terminal, a source of the second PMOS transistor P12 is coupled to a source of the first PMOS transistor P11, a gate is coupled to a drain of the first PMOS transistor P11, and a drain is coupled to a gate of the first PMOS transistor P11. The first NMOS transistor N11 and the second NMOS transistor N12 are cross-coupled, the drain of the first NMOS transistor N11 is coupled to the drain of the first PMOS transistor P11, the source is coupled to the second power supply terminal, and the gate is coupled to the drain of the second PMOS transistor P12. The drain electrode of the second NMOS transistor N12 is coupled with the gate electrode of the first NMOS transistor N11, the gate electrode is coupled with the drain electrode of the first NMOS transistor N11, and the source electrode is coupled with the source electrode of the first NMOS transistor N11. The drain of the first NMOS transistor N11 and the drain of the first PMOS transistor P11 are coupled to a bit line, and the drain of the second NMOS transistor N12 and the drain of the second PMOS transistor P12 are coupled to a complementary bit line. In the manufacturing process of the first NMOS transistor N11 and the second NMOS transistor N12, due to the influence of factors such as process and temperature, there is a difference in doping concentration between the first NMOS transistor N11 and the second NMOS transistor N12, so that there is a mismatch between the threshold voltage of the first NMOS transistor N11 and the threshold voltage of the second NMOS transistor N12, which affects the voltage difference between the sense amplifier amplifying bit line and the complementary bit line, and causes erroneous read/write results in the data reading process.
Fig. 2 is a circuit schematic diagram of a sense amplifier in a mismatch elimination stage according to an embodiment of the present disclosure, and as shown in fig. 2, an embodiment of the present disclosure provides a sense amplifier including a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, and a body bias adjustment module 100. The source of the first P-type transistor P1 is coupled to the first power supply terminal VDD, the source of the second P-type transistor P2 is coupled to the source of the first P-type transistor P1, the gate is coupled to the drain of the first P-type transistor P1, and the drain is coupled to the gate of the first P-type transistor P1. The drain electrode of the first N-type transistor N1 is coupled with the drain electrode of the first P-type transistor P1, the source electrode is coupled with the second power supply end VSS, the drain electrode of the second N-type transistor N2 is coupled with the drain electrode of the second P-type transistor P2, and the source electrode is coupled with the source electrode of the first N-type transistor N1. The body bias adjustment module 100 has a first input terminal I1 coupled to the drain of the first N-type transistor N1, a second input terminal I2 coupled to the drain of the second N-type transistor N2, a first output terminal coupled to the body terminal of the first P-type transistor P1, a second output terminal coupled to the body terminal of the second P-type transistor P2, and a control terminal coupled to the enable signal (EN).
When there is a difference between the threshold voltage of the first N-type transistor N1 and the threshold voltage of the second N-type transistor N2, if the body bias adjustment module 100 receives the enable signal, the difference between the threshold voltage of the first N-type transistor N1 and the threshold voltage of the second N-type transistor N2 is compensated in response to the enable signal. The body bias adjustment module 100 adjusts the body terminal voltage of the first P-type transistor P1 and/or the body terminal voltage of the second P-type transistor P2 to adjust the body bias voltage of the first P-type transistor P1 and/or the body bias voltage of the second P-type transistor P2 to adjust the threshold voltage of the first P-type transistor P1 and/or the threshold voltage of the second P-type transistor, compensate the threshold voltage of the first N-type transistor N1 or the threshold voltage of the second N-type transistor N2, and reduce the difference between the threshold voltage of the second N-type transistor N2 and the threshold voltage of the first N-type transistor N1. The complementary read bit line SABLB of the sense amplifier reads the voltage signal on the complementary bit line BLB of the memory cell, the read bit line SABL of the sense amplifier reads the voltage signal on the bit line BL of the memory cell, and when the first P-type transistor P1 and the second P-type transistor P2 are in the cross coupling mode, the sense amplifier can amplify the voltage difference between the bit line BL and the complementary bit line BLB of the memory cell when the first N-type transistor N1 and the second N-type transistor N2 are in the cross coupling mode, thereby improving the accuracy in the data reading process.
Fig. 3 is a flowchart illustrating the operation of a sense amplifier, in some embodiments, as shown in fig. 3, the drain voltage of the N-type transistor in the first branch and the drain voltage of the N-type transistor in the second branch are detected, a feedback voltage is generated according to the voltage difference between the drain voltage of the N-type transistor in the first branch and the drain voltage of the N-type transistor in the second branch, and then it is determined whether the drain voltage of the N-type transistor in the first branch is greater than the drain voltage of the second branch. When the drain voltage of the N-type transistor in the first branch is larger than that of the second branch, the body terminal voltage of the P-type transistor in the first branch is reduced, and the body terminal voltage of the P-type transistor in the second branch is kept unchanged; when the drain voltage of the N-type transistor in the first branch is smaller than that of the second branch, the body terminal voltage of the P-type transistor in the first branch is maintained unchanged, and the body terminal voltage of the P-type transistor in the second branch is reduced.
It should be noted that, in the process of reducing the body voltage of the P-type transistor of one branch, the body voltage of the P-type transistor of the other branch may also be changed. Referring to fig. 2, by adjusting the output values of the comparators A1 and A2, the influence of the body terminal voltage of the P-type transistor on the threshold voltage thereof can be controlled. For example, when the drain voltage of the N-type transistor in the first branch is greater than the drain voltage of the N-type transistor in the second branch, the final adjustment result is that the absolute value of the threshold voltage of the P-type transistor in the first branch is smaller than the absolute value of the threshold voltage of the P-type transistor in the second branch.
Therefore, in some embodiments, when the drain voltage of the N-type transistor in the first branch is greater than the drain voltage of the second branch, the comparator A1 outputs a first feedback value, the body voltage of the P-type transistor in the first branch is reduced by using the first feedback value, the comparator A2 outputs a second feedback value, and the body voltage of the P-type transistor in the second branch is raised by using the second feedback value; when the drain voltage of the N-type transistor in the first branch is smaller than the drain voltage of the second branch, the comparator A1 outputs a third feedback value, the body voltage of the P-type transistor in the first branch is raised by using the third feedback value, the comparator A1 outputs a fourth feedback value, and the body voltage of the P-type transistor in the second branch is lowered by using the fourth feedback value. Therefore, the comparator A1 can be used for adjusting the body terminal voltage of the P-type transistor in the first branch, and the comparator A2 can be used for adjusting the body terminal voltage of the P-type transistor in the second branch, so that the efficiency is improved.
In some embodiments, when the drain voltage of the N-type transistor in the first branch is greater than the drain voltage of the second branch, maintaining the body voltage of the P-type transistor in the first branch unchanged, outputting a feedback value by using the comparator A2, and raising the body voltage of the P-type transistor in the second branch by using the feedback value; when the drain voltage of the N-type transistor in the first branch is smaller than that of the second branch, the comparator A1 is used for outputting a feedback value, and the body terminal voltage of the P-type transistor in the first branch is raised by using the feedback value, so that the body terminal voltage of the P-type transistor in the second branch is kept unchanged. Therefore, a comparator may also be used to adjust the body voltage of the P-type transistor in the first branch or the body voltage of the P-type transistor in the second branch.
As shown in fig. 2, during the precharge phase, when the OC signal is active, the control unit 200 controls the drain coupling of the bit line BL and the first N-type transistor N1, and the drain coupling of the bit line BL and the gate coupling of the first N-type transistor N1, the drain voltage of the first N-type transistor N1 is equal to the gate voltage of the first N-type transistor N1, and the first N-type transistor N1 is in the saturated amplifying mode. In addition, when the OC signal is active, the control unit 200 further controls the complementary bit line BLB to be coupled with the drain of the second N-type transistor N2, and the complementary bit line BLB to be coupled with the gate of the second N-type transistor N2, so that the drain of the second N-type transistor N2 is coupled with the gate, and the drain voltage of the second N-type transistor N2 is equal to the gate voltage of the second N-type transistor N2, and the second N-type transistor N2 is in the saturated amplifying mode.
When the threshold voltage of the first N-type transistor N1 is greater than the threshold voltage of the second N-type transistor N2, the drain-source voltage of the first N-type transistor N1 is greater than the drain-source voltage of the second N-type transistor N2, and since the source of the first N-type transistor N1 is coupled to the source of the second N-type transistor N2, the source voltage of the first N-type transistor N1 is equal to the source voltage of the second N-type transistor N2, and thus the drain voltage of the first N-type transistor N1 is greater than the drain voltage of the second N-type transistor N2.
When the threshold voltage of the first N-type transistor N1 is smaller than the threshold voltage of the second N-type transistor N2, the drain-source voltage of the first N-type transistor N1 is smaller than the drain-source voltage of the second N-type transistor N2, and since the source voltage of the first N-type transistor N1 is equal to the source voltage of the second N-type transistor N2, the drain voltage of the first N-type transistor N1 is smaller than the drain voltage of the second N-type transistor N2.
In some embodiments, the body bias adjustment module 100 includes a first adjustment module 101, a first input of the first adjustment module 101 coupled to a second input I2 of the body bias adjustment module 100, a second input of the first adjustment module 101 coupled to a first input I1 of the body bias adjustment module 100, an output of the first adjustment module 101 coupled to a first output of the body bias adjustment module 100, and a control of the first adjustment module 101 coupled to an enable signal. The first adjustment module 101 compensates for a difference between the threshold voltage of the first N-type transistor N1 and the threshold voltage of the second N-type transistor N2 in response to the enable signal after receiving the enable signal. When the drain voltage of the first N-type transistor N1 is greater than the drain voltage of the second N-type transistor N2, the first adjusting module 101 decreases the body voltage of the first P-type transistor P1 according to the voltage difference between the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2, and decreases the absolute value of the threshold voltage of the first P-type transistor P1. When the absolute value of the threshold voltage of the first P-type transistor P1 decreases, the drain voltage of the first P-type transistor P1 decreases and the drain voltage of the first N-type transistor N1 decreases when the source-drain voltage of the first P-type transistor P1 increases. Therefore, after the body voltage of the first P-type transistor P1 is adjusted, the drain voltage variation trend of the first N-type transistor N1 is opposite to the drain voltage variation trend of the first N-type transistor N1 before adjustment, so as to achieve the effect of compensating the threshold voltage of the first N-type transistor N1, i.e. achieve the effect of reducing the threshold voltage of the first N-type transistor N1.
The body bias adjustment module 100 further includes a second adjustment module 102, a first input of the second adjustment module 102 is coupled to the first input I1 of the body bias adjustment module 100, a second input of the second adjustment module 102 is coupled to the second input I2 of the body bias adjustment module 100, an output of the second adjustment module 102 is coupled to the second output of the body bias adjustment module 100, and a control of the second adjustment module 102 is coupled to the enable signal. The second adjustment module 102 compensates for a difference between the threshold voltage of the first N-type transistor N1 and the threshold voltage of the second N-type transistor N1 in response to the enable signal after receiving the enable signal. When the drain voltage of the first N-type transistor N1 is smaller than the drain voltage of the second N-type transistor N2, the body voltage of the second P-type transistor P2 is reduced according to the voltage difference between the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2, and the absolute value of the threshold voltage of the second P-type transistor P2 is reduced. When the absolute value of the threshold voltage of the second P-type transistor P2 decreases, the source-drain voltage of the second P-type transistor P2 decreases, and the drain voltage of the second N-type transistor N2 decreases. Therefore, after the body voltage of the second P-type transistor P2 is adjusted, the drain voltage variation trend of the second N-type transistor N2 is opposite to the drain voltage variation trend of the second N-type transistor N2 before adjustment, so as to achieve the effect of compensating the threshold voltage of the second N-type transistor N2, i.e. achieve the effect of reducing the threshold voltage of the second N-type transistor N2.
As one implementation, when the threshold voltage of the first N-type transistor N1 is greater than the threshold voltage of the second N-type transistor N2, the drain voltage of the first N-type transistor N1 is greater than the drain voltage of the second N-type transistor N2, the first adjusting module 101 decreases the body voltage of the first P-type transistor P1 according to the voltage difference between the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2, and the second adjusting module 102 increases the body voltage of the second P-type transistor P2 according to the voltage difference between the drain voltage of the first N-type transistor N2 and the drain voltage of the second N-type transistor N1. The absolute value of the threshold voltage of the first P-type transistor P1 decreases, the drain voltage decreases, the absolute value of the threshold voltage of the second P-type transistor P2 increases, the drain voltage increases, and the efficiency of compensating the threshold voltage of the first N-type transistor N1 increases.
When the threshold voltage of the first N-type transistor N1 is smaller than the threshold voltage of the second N-type transistor N2, the drain voltage of the first N-type transistor N1 is smaller than the drain voltage of the second N-type transistor N2, the first adjusting module 101 increases the body voltage of the first P-type transistor P1 according to the voltage difference between the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2, and the second adjusting module 102 decreases the body voltage of the second P-type transistor P2 according to the voltage difference between the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2. The absolute value of the threshold voltage of the first P-type transistor P1 increases, the absolute value of the threshold voltage of the second P-type transistor P2 decreases, the drain voltage decreases, and the efficiency of compensating the threshold voltage of the second N-type transistor N2 increases.
In some embodiments, the first adjustment module 101 includes a first comparator A1, where a non-inverting input of the first comparator A1 is coupled to the second input I2 of the body bias adjustment module 100, a inverting input is coupled to the first input I1 of the body bias adjustment module 100, and an output is provided as a first output of the body bias adjustment module 100, and a control is coupled to an enable signal. The first comparator A1 has its unidirectional input coupled to the drain of the second N-type transistor N2 and its reverse input coupled to the drain of the first N-type transistor N1. The first comparator A1 is thus able to detect the voltage difference between the drain-source voltage of the second N-type transistor N2 and the drain-source voltage of the first N-type transistor N1.
When the first comparator A1 detects that the drain voltage of the second N-type transistor N2 is smaller than the drain voltage of the first N-type transistor N1, a feedback voltage is output according to the voltage difference between the drain-source voltage of the second N-type transistor N2 and the drain-source voltage of the first N-type transistor N1, the body end voltage of the first P-type transistor P1 is reduced by using the feedback voltage, the absolute value of the threshold voltage of the first P-type transistor P1 is reduced, the drain voltage of the first P-type transistor P1 is reduced, and the effect of compensating the threshold voltage of the first N-type transistor N1 is achieved.
The second adjusting module 102 includes a second comparator A2, where a non-inverting input terminal of the second comparator A2 is coupled to the first input terminal I1 of the body bias adjusting module 100, a inverting input terminal of the second comparator A2 is coupled to the second input terminal I1 of the body bias adjusting module 100, an output terminal is used as a second output terminal of the body bias adjusting module 100, and a control terminal is coupled to an enable signal. The second comparator A2 has a common input coupled to the drain of the first N-type transistor N1 and an opposite input coupled to the drain of the second N-type transistor N2, so that the second comparator A2 is capable of detecting a voltage difference between the drain-source voltage of the first N-type transistor N1 and the drain-source voltage of the second N-type transistor N2.
When the second comparator A2 detects that the drain voltage of the first N-type transistor N1 is smaller than the drain voltage of the second N-type transistor N2, a feedback voltage is output according to the voltage difference between the drain-source voltage of the first N-type transistor N1 and the drain-source voltage of the second N-type transistor N2, the body end voltage of the second P-type transistor P2 is reduced by using the feedback voltage, the absolute value of the threshold voltage of the second P-type transistor P2 is reduced, the drain voltage of the second P-type transistor P2 is reduced, and the effect of compensating the threshold voltage of the second N-type transistor N2 is achieved.
When the first comparator A1 and the second comparator A2 detect that the drain voltage of the first N-type transistor N1 is greater than the drain voltage of the second N-type transistor N2, the first comparator A1 outputs a first feedback voltage according to the voltage difference between the drain voltage of the second N-type transistor N2 and the drain voltage of the first N-type transistor N1, the body voltage of the first P-type transistor P1 is reduced by using the first feedback voltage, and the second comparator A2 outputs a second feedback voltage according to the voltage difference between the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2, and the body voltage of the second P-type transistor P2 is raised by using the second feedback voltage. The absolute value of the threshold voltage of the first P-type transistor P1 decreases, the drain voltage decreases, the absolute value of the threshold voltage of the second P-type transistor P2 increases, and the drain voltage increases to compensate the threshold voltage of the first N-type transistor N1.
When the first comparator A1 and the second comparator A2 detect that the drain voltage of the first N-type transistor N1 is smaller than the drain voltage of the second N-type transistor N2, the first comparator A1 outputs a third feedback voltage according to the voltage difference between the drain voltage of the second N-type transistor N2 and the drain voltage of the first N-type transistor N1, the body voltage of the first P-type transistor P1 is raised by using the third feedback voltage, and the second comparator A2 outputs a fourth feedback voltage according to the voltage difference between the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2, and the body voltage of the second P-type transistor P2 is lowered by using the fourth feedback voltage. The absolute value of the threshold voltage of the first P-type transistor P1 increases, the absolute value of the threshold voltage of the second P-type transistor P2 decreases, and the drain voltage decreases to compensate the threshold voltage of the second N-type transistor N2.
Fig. 4 is a schematic cross-sectional structure of a P-type transistor, as shown in fig. 4, in which a deep N-well is formed in a P-type semiconductor substrate P-sub by N-type ion implantation, and two P-type heavily doped regions are formed in the deep N-well to serve as a source region and a drain region of the P-type transistor, respectively, wherein the source region is connected to a source terminal, and the drain region is connected to a drain terminal. An N-type heavy doping region is formed in the deep N-well, the N-type heavy doping region is connected with a body end, a gate region is formed on the surface of the deep N-well between the two p-type heavy doping regions, and the gate region is connected with the gate end. Fig. 5 is a circuit schematic diagram of a P-type transistor, where, as shown in fig. 5, a source terminal, a drain terminal, and a gate terminal are respectively connected to high potentials Vs, vd, and Vg, a substrate terminal is grounded, a diode D1 is a PN junction formed at a source terminal, a diode D2 is a PN junction formed at a drain terminal, and a diode D3 is a PN junction formed at a body terminal. In order to ensure the normal operation of the transistor, PN junction reverse bias is needed, the body voltage Vb is larger than the source voltage Vs, the body voltage Vb is larger than the drain voltage Vd, the body voltage Vb is larger than zero, the adjustable range of the body voltage Vb is obtained as (VDD, VPP), VPP is the maximum supply voltage, and VDD is the normal operation voltage.
For the convenience of understanding the technical scheme of the present disclosure, taking the example that the threshold voltage of the first N-type transistor N1 is smaller than the threshold voltage of the second N-type transistor N2, referring to fig. 2, the bit line BL and the complementary bit line BLB are precharged to the same voltage, the first control signal SAP and the second control signal SAN are in the active on state, and the enable signal EN is also in the active on state, and the technical scheme of the present disclosure is described in detail.
The sense bit line current ISABL of the sense amplifier is:
wherein u is n Representing the mobility of the carriers;
c ox representing the capacitance value of the gate oxide layer in unit area;
representing the width to length ratio of the channel of the second N-type transistor N2;
V gsn2 a gate-source voltage of the second N-type transistor N2;
V thn represents the threshold voltage V of the first N-type transistor N1 thn1 Is herein understood to be V thn1 ；
ΔV thn2 Expressed in V thn When the threshold voltage of the first N-type transistor N1 and the threshold voltage of the second N-type transistor N2 deviate due to fluctuation of process manufacture, different PVT (Process, voltage, temperature) conditions, different channel length-to-width ratios and the like, and can be expressed as-V thn2 -V thn1 。
Complementary sense bit line current isabelb of sense amplifier:
wherein,,representing the width-to-length ratio of the channel of the first N-type transistor N1;
V gsn1 The gate-source voltage of the first N-type transistor N1 is shown.
The bit line BL and the complementary bit line BLB are precharged to the same voltage, the gate of the first N-type transistor N1 is connected with the bit line BL, the gate of the second N-type transistor N2 is connected with the complementary bit line BLB, the source of the first N-type transistor N1 is connected with the source of the second N-type transistor N2, the gate-source voltage of the first N-type transistor N1 is equal to the gate-source voltage of the second N-type transistor N2, and the readout bit line current ISABL of the sense amplifier is smaller than the complementary readout bit line current ISABLB of the sense amplifier.
The first comparator A1 detects a first voltage difference between the drain-source voltage of the second N-type transistor N2 and the drain-source voltage of the first N-type transistor N1 and outputs a first feedback voltage V according to the first voltage difference b1 ：
V b1 ＝A(V dsn2 -V dsn1 ) (3)
The second comparator A2 detects a second voltage difference between the drain-source voltage of the first N-type transistor N1 and the drain-source voltage of the second N-type transistor N2 and outputs a second feedback voltage V according to the second voltage difference b2 ：
V b2 ＝A(V dsn1 -V dsn2 ) (4)
Wherein,,
wherein VPP represents the maximum supply voltage, VDD represents the normal operating voltage, V In the same direction Is the voltage value of the same-direction input end of the comparator, V Reverse direction Is the voltage at the inverting input of the comparator, and the value of a is only easy to understand, but in one embodiment, may be adjusted with other values.
Then, according to equations (3) and (5), when the drain-source voltage of the first N-type transistor N1 is smaller than the drain-source voltage of the second N-type transistor N2, the first comparator A1 outputs a first feedback voltage according to the first voltage difference:
V b1 ＝VPP(V dsn2 -V dsn1 ) (6)
as can be seen from the formulas (4) and (6), when the drain-source voltage of the first N-type transistor N1 is smaller than the drain-source voltage of the second N-type transistor N2, the second comparator A2 outputs the second feedback voltage according to the second voltage difference:
V b2 ＝-VDD(V dsn1 -V dsn2 ) (7)
then the first feedback voltage V b1 Greater than the second feedback voltage V b2 。
Then go through the first feedback voltage V b1 The first P-type transistor P1 is in a saturation region after adjustment; and the working current ISABL' of the first P-type transistor P1 is:
wherein,,
V′ thp1 representing the threshold voltage of the first P-type transistor P1 after the first feedback voltage adjustment; phi F is the flatband voltage, representing silicon to twoThe difference of the work functions of the silicon oxide, namely the potential when the needed external voltage is leveled on the surface energy band of the semiconductor in the MOS tube; r represents a body effector; v (V) sb1 Representing the bias voltage between the source and body terminals of the first P-type transistor.
According to the second feedback voltage V b2 The body voltage of the second P-type transistor P2 is reduced, the absolute value of the threshold voltage of the second P-type transistor P2 is reduced, the drain voltage of the second P-type transistor P2 is reduced, and the second P-type transistor P2 is in a linear region and passes through a second feedback voltage V b2 The regulated operating current ISABL' of the second P-type transistor P2 is:
wherein,,
V′ thp2 representing the threshold voltage of the second P-type transistor P2 after the second feedback voltage adjustment; v (V) sb2 Representing the bias voltage between the source and body terminals of the second P-type transistor.
Since the threshold voltage of the first N-type transistor N1 is smaller than the threshold voltage of the second N-type transistor N2, the gate-source voltage of the first N-type transistor N1 is smaller than the gate-source voltage of the second N-type transistor N2. According to the formula (6) and the formula (7), the second feedback voltage is smaller than the first feedback voltage, and according to the formula (9) and the formula (11), the absolute value of the threshold voltage of the first P-type transistor P1 is larger than the absolute value of the threshold voltage of the second P-type transistor P2 after adjustment. Therefore, according to the formula (8) and the formula (9), the operating current of the first P-type transistor P1 after the first feedback voltage adjustment is smaller than the operating current of the second P-type transistor P2 after the second feedback voltage adjustment, i.e. ISABL '> isabelb'.
After the threshold voltage of the first P-type transistor P1 and the threshold voltage of the second P-type transistor P2 are adjusted, the first N-type transistor N1 and the second N-type transistor N2 are both in a critical saturation region, and the gate-source voltage of the adjusted second N-type transistor N2 is:
The gate-source voltage of the adjusted first N-type transistor N1 is:
due to the first feedback voltage V b1 Greater than the second feedback voltage V b2 And the first and second P-type transistors share the source terminal, the bias voltage V between the source terminal and the body terminal of the second P-type transistor sb2 Greater than the bias voltage V between the source and body terminals of the first P-type transistor sb1 The drain voltage of the adjusted first N-type transistor N1 is greater than the drain voltage of the second N-type transistor N2. Therefore, the drain voltage variation trend of the first N-type transistor N1 after adjustment is opposite to the drain voltage variation trend of the first N-type transistor N1 before adjustment, and the drain voltage variation trend of the second N-type transistor N2 after adjustment is opposite to the drain voltage variation trend of the second N-type transistor N2 before adjustment, so as to achieve the effect of compensating the threshold voltage of the first N-type transistor N1.
Thus, the sense amplifier provided by the present disclosure can compensate the threshold voltage of the first N-type transistor or the threshold voltage of the second N-type transistor, reduce the mismatch of the threshold voltage of the first N-type transistor and the threshold voltage of the second N-type transistor by adjusting the threshold voltage of the first P-type transistor P1 and/or adjusting the threshold voltage of the second P-type transistor by the body bias adjusting module,
As shown in fig. 2, the sense amplifier includes a control unit 200, and the control unit 200 is capable of stabilizing voltages of the bit line BL and the complementary bit line BLB of the memory cell and the sense bit line SABL and the complementary sense bit line SABLB of the sense amplifier at 0.5Vcc in a precharge phase. In some embodiments, control unit 200 is used to control the coupling between the bit line and the first N-type transistor N1, and also to control the coupling between the complementary bit line BL and the second N-type transistor N2. After receiving the OC (Offset Cancellation ) signal, the control unit 200 controls the drain of the first N-type transistor N1 to be coupled to the bit line BL and controls the drain of the second N-type transistor N2 to be coupled to the complementary bit line BLB. The bit line BL is also coupled to the gate of the first N-type transistor N1, thereby coupling the gate and drain of the first N-type transistor N1, and the complementary bit line BLB is also coupled to the gate of the second N-type transistor N1, thereby coupling the gate and drain of the second N-type transistor N2.
In some embodiments, the control unit 200 includes a first control unit 201, a first terminal of the first control unit 201 is coupled to the bit line BL, a second terminal of the first control unit 201 is coupled to a drain of the first N-type transistor N1, and the first control unit 201 is capable of controlling the coupling of the bit line BL and the first N-type transistor N1. The first control unit 201 may include a first control transistor N3, a source of the first control transistor N3 is used as a first terminal of the first control unit 201, a bit line is coupled, a drain of the first control unit 201 is used as a second terminal of the first control unit 201, and a drain of the first N-type transistor N1 is coupled, so that the first control transistor N3 can control coupling of the bit line BL and the first N-type transistor N1.
The control unit 200 includes a second control unit 202, a first terminal of the second control unit 202 is coupled to the complementary bit line BLB, a second terminal of the second control unit 202 is coupled to a drain of the second N-type transistor N2, and the second control unit 202 is capable of controlling the coupling of the complementary bit line BLB and the second N-type transistor N2. The second control unit 202 may include a second control transistor N4, where a source of the second control transistor N4 is used as a first terminal of the second control unit 202, coupled to the complementary bit line BLB, a drain of the second control transistor N4 is used as a second terminal of the second control unit 202, coupled to a drain of the second N-type transistor N2, and the second control transistor N4 is capable of controlling coupling of the complementary bit line BLB and the second N-type transistor N2.
It should be noted that the scheme of the present disclosure may be used alone, where the OC signal is used to control the gate and drain coupling of the first control transistor N3, and the gate and drain coupling of the fourth control transistor N4 is also used to reduce the mismatch between the threshold voltage of the first N-type transistor N1 and the threshold voltage of the second N-type transistor N2. However, in combination with the scheme of the present disclosure and using OC signals to control the gate and drain coupling of the first control transistor N3 and the gate and drain coupling of the fourth control transistor N4, the mismatch problem can be better solved.
In some embodiments, the sense amplifier includes a third control unit 300, a first terminal of the third control unit 300 is coupled to the first power supply terminal VDD, and a second terminal of the third control unit 300 is coupled to a source of the first P-type transistor P1 for controlling whether to supply the voltage. The third control unit 300 may include a third control transistor P0, a source of the third control transistor P0 being coupled to the first terminal of the third control unit 300, a drain of the third control transistor P0 being coupled to the second terminal of the third control unit 300, a source of the first P-type transistor P1, the third control transistor P0 being configured to control the turn-off of the first power terminal VDD in response to the first control signal SAP, for controlling whether to supply the voltage.
The sense amplifier includes a fourth control unit 400, a first end of the fourth control unit 400 is coupled to the second power supply terminal VSS, a second end of the fourth control unit 400 is coupled to the source of the first N-type transistor N1, and the fourth control unit 400 is configured to control the second power supply terminal VSS to be turned off, and to control whether to supply a voltage. The fourth control unit 400 includes a fourth control transistor N0, a source of the fourth control transistor N0 is coupled to the first terminal of the fourth control unit 400, the second power terminal VSS is coupled, a drain of the fourth control transistor N0 is coupled to the second terminal of the fourth control unit 400, a source of the first N-type transistor N1 is coupled, and the fourth control transistor N0 is configured to control whether the voltage is supplied in response to the second control signal SAN.
According to the sense amplifier provided by the disclosure, the body bias adjusting module is used for adjusting the threshold voltage of the first P-type transistor P1 and/or adjusting the body terminal voltage of the second P-type transistor P1 so as to adjust the threshold voltage of the first P-type transistor P1 and/or adjust the threshold voltage of the second P-type transistor P1, so that the threshold voltage of the first N-type transistor or the threshold voltage of the second N-type transistor is compensated, the mismatch between the threshold voltage of the first N-type transistor and the threshold voltage of the second N-type transistor is reduced, and the accuracy of data reading is improved.
An embodiment of the present disclosure further provides a semiconductor memory device including the above sense amplifier.
The semiconductor memory further includes a plurality of memory cells, a portion of the memory cells constituting a first memory array and a portion of the memory cells constituting a second memory array. Each memory cell in the first memory array is connected to a bit line of the first memory array, and each memory cell in the second memory array is connected to a bit line of the second memory array.
The sense amplifier is positioned between the first storage array and the second storage array, the first end of the sense amplifier is connected with the first power supply end, the second end of the sense amplifier is connected with the second power supply end, the third end of the sense amplifier is connected with the bit line of the first storage array, and the fourth end of the sense amplifier is connected with the bit line of the second storage array.
Each memory cell is used for storing one bit of data, the bit line of the first memory array is used for accessing the data stored in each memory cell in the first memory array, and the bit line of the second memory array is used for accessing the data stored in each memory cell in the second memory array. The sense amplifier is used to amplify the stored data in each memory cell and is present on the bit line of the first memory array and the bit line of the second memory array.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. Exemplary embodiments of the present disclosure relate to, but are not limited to, a sense amplifier and a semiconductor memory.

Claims (15)

1. A sense amplifier, comprising:
a first P-type transistor, the source of which is coupled to the first power terminal;
a second P-type transistor having a source coupled to the source of the first P-type transistor, a gate coupled to the drain of the first P-type transistor, and a drain coupled to the gate of the first P-type transistor;
a first N-type transistor, the drain electrode of which is coupled with the drain electrode of the first P-type transistor, and the source electrode of which is coupled with a second power supply end;
a second N-type transistor having a drain coupled to the drain of the second P-type transistor and a source coupled to the source of the first N-type transistor;
and the body bias adjusting module is used for responding to the enabling signal to compensate the difference of threshold voltages between the second N-type transistor and the first N-type transistor.
2. The sense amplifier of claim 1 wherein the body bias adjustment module comprises:
The first input end of the first adjusting module is coupled with the second input end of the body bias adjusting module, the second input end of the first adjusting module is coupled with the first input end of the body bias adjusting module, the output end of the first adjusting module is the first output end of the body bias adjusting module, and the control end of the first adjusting module is coupled with the enabling signal;
the method is used for reducing the body terminal voltage of the first P-type transistor when the drain voltage of the first N-type transistor is larger than the drain voltage of the second N-type transistor so as to compensate the threshold voltage of the first N-type transistor.
3. The sense amplifier of claim 2 wherein the first adjustment module comprises:
the first comparator is coupled with the second input end of the body bias adjusting module at the same direction input end, is coupled with the first input end of the body bias adjusting module at the opposite direction input end, is coupled with the first output end of the body bias adjusting module at the output end, and is coupled with the enabling signal at the control end.
4. The sense amplifier of claim 1 wherein the body bias adjustment module comprises:
the first input end of the second adjusting module is coupled with the first input end of the body bias adjusting module, the second input end of the second adjusting module is coupled with the second input end of the body bias adjusting module, the output end of the second adjusting module is the second output end of the body bias adjusting module, and the control end of the second adjusting module is coupled with the enabling signal;
The method is used for reducing the body terminal voltage of the second P-type transistor when the drain voltage of the first N-type transistor is smaller than the drain voltage of the second N-type transistor so as to compensate the threshold voltage of the second N-type transistor.
5. The sense amplifier of claim 4 wherein the second adjustment module comprises:
and the second comparator is coupled with the drain electrode of the first P-type transistor at the same direction input end, the drain electrode of the second P-type transistor at the opposite direction input end, the body end of the second P-type transistor at the output end and the enabling signal at the control end.
6. The sense amplifier of claim 1, further comprising:
and a control unit for controlling coupling between the bit line and the first N-type transistor and coupling between the complementary bit line and the second N-type transistor.
7. The sense amplifier of claim 6 wherein the control unit comprises a first control unit having a first terminal coupled to the bit line and a second terminal coupled to the drain of the first N-type transistor.
8. The sense amplifier of claim 7 wherein the first control unit comprises a first control transistor;
The source electrode of the first control transistor is used as the first end of the first control unit and is coupled with a bit line;
the drain of the first control transistor is used as a second end of the first control unit and is coupled with the drain of the first N-type transistor.
9. The sense amplifier of claim 6 wherein the control unit comprises a second control unit having a first terminal coupled to the complementary bit line and a second terminal coupled to the drain of the second N-type transistor.
10. The sense amplifier of claim 9, wherein the second control unit comprises a second control transistor;
the source electrode of the second control transistor is used as a first end of the second control unit and is coupled with the complementary bit line;
the drain electrode of the second control transistor is used as a second end of the second control unit and is coupled with the drain electrode of the second N-type transistor.
11. The sense amplifier of claim 1, further comprising:
and a third control unit, a first end of which is coupled with the first power supply end, and a second end of which is coupled with the source electrode of the first P-type transistor and is used for supplying voltage.
12. The sense amplifier of claim 11, wherein the third control unit comprises a third control transistor;
The source electrode of the first P-type transistor is used as the first end of the third control unit, the first power end is coupled, the drain electrode of the first P-type transistor is used as the second end of the third control unit, and the source electrode of the first P-type transistor is coupled.
13. The sense amplifier of claim 1, further comprising:
and a fourth control unit, the first end of which is coupled with the second power supply end, and the second end of which is coupled with the source electrode of the first N-type transistor and is used for supplying voltage.
14. The sense amplifier of claim 13 wherein the fourth control unit comprises a fourth control transistor;
the source electrode of the first N-type crystal is used as the first end of the fourth control unit, the second power end is coupled, the drain electrode of the first N-type crystal is used as the second end of the fourth control unit, and the source electrode of the first N-type crystal is coupled.
15. A semiconductor memory device, comprising: a sense amplifier as claimed in any one of claims 1 to 14.
CN202210284403.8A 2022-03-22 2022-03-22 Sense amplifier and semiconductor memory Pending CN116825162A (en)

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CN117174137A (en) * 2023-10-31 2023-12-05 长鑫存储技术有限公司 Sense amplifier, repair method thereof and memory

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US8018253B2 (en) * 2009-08-28 2011-09-13 Advanced Micro Devices, Inc. Sense amplifier circuit and related configuration and operation methods
US9088280B2 (en) * 2013-10-30 2015-07-21 Freescale Semiconductor, Inc. Body bias control circuit
US9319013B2 (en) * 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
CN113470705B (en) * 2020-03-30 2024-05-14 长鑫存储技术有限公司 Sense amplifier, memory and data reading method
CN111863054B (en) * 2020-08-13 2022-11-01 安徽大学 Sense amplifier, memory and control method of sense amplifier
CN112767975B (en) * 2021-02-10 2022-04-12 长鑫存储技术有限公司 Sense amplifier and control method thereof

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CN117174137A (en) * 2023-10-31 2023-12-05 长鑫存储技术有限公司 Sense amplifier, repair method thereof and memory
CN117174137B (en) * 2023-10-31 2024-02-06 长鑫存储技术有限公司 Sense amplifier, repair method thereof and memory

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