CN116738899B

CN116738899B - Transcoding device and method for hardware intellectual property block

Info

Publication number: CN116738899B
Application number: CN202311020799.6A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2023-08-14
Filing date: 2023-08-14
Publication date: 2023-10-31
Anticipated expiration: 2043-08-14
Also published as: CN116738899A

Abstract

The application relates to the field of intellectual property block design, and discloses a transcoding device and method of a hardware intellectual property block, wherein the method comprises the following steps: determining logic node information based on module information obtained by extracting hardware description language codes of intellectual property blocks, wherein the logic node information represents that the hardware description language codes are abstracted into information corresponding to logic nodes; constructing a tree-type data structure based on the logic node information; and determining the hardware structure mark language code of each logic node based on the tree data structure and the logic node information so as to obtain the hardware structure mark language code of the intellectual property block. The embodiment of the application can convert the hardware description language code of the intellectual property block into the hardware structure marking language code, thereby being beneficial to improving the development efficiency.

Description

Transcoding device and method for hardware intellectual property block

Technical Field

The present application relates to the field of intellectual property block design, and in particular, to a transcoding device and method for an intellectual property block.

Background

In the chip design development process, hardware description language (Hardware Description Language, abbreviated to HDL) is a common language, such as VHDL (Verilog Hardware Description Language).

It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.

Disclosure of Invention

The applicant finds that the hardware description language is inconvenient for a developer to read, and the developer has difficulty in quickly knowing the hardware structure of the hardware described by the hardware description language code, and has difficulty in quickly finding out the "performance bottleneck" of the hardware, so that development efficiency is affected.

Aiming at least one of the problems or similar problems, the embodiment of the application provides a code conversion device and a code conversion method of an intellectual property block, which convert hardware description language codes into markup language codes of a hardware structure, improve the readability of hardware IP codes and improve the development efficiency.

The embodiment of the application provides a code conversion method of an intellectual property block, which comprises the following steps:

determining logic node information based on module information obtained by extracting hardware description language codes of intellectual property blocks, wherein the logic node information represents that the hardware description language codes are abstracted into information corresponding to logic nodes;

Based on the logic node information, a tree-type data structure is constructed, wherein nodes of the tree-type data structure correspond to logic nodes one by one;

and determining the hardware structure mark language code of each logic node based on the tree data structure and the logic node information so as to obtain the hardware structure mark language code of the intellectual property block.

In one possible implementation, determining a hardware structure markup language code for each logical node based on the tree data structure and the logical node information includes:

traversing the tree data structure in a depth-first mode, and determining a hardware structure mark language code of each logic node according to the logic node information; or,

and determining the hardware structure mark language codes of the corresponding logic nodes of the target node according to the logic node information, wherein the target node is any node of the tree data structure.

In one possible implementation, determining the hardware structural markup language code of each logical node includes:

Determining an input signal of a logic node in response to the type of the logic node being a sub-module logic node;

capturing input logic nodes corresponding to each input signal;

determining a hardware structure markup language code of the logical node based on all input logical nodes and all sub-logical nodes of the logical node,

the sub-module logical nodes are logical nodes comprising sub-logical nodes.

In one possible implementation, the input signal of the logical node is determined based on at least one of an input of the target module, an output of the target module, a register level signal of the target module, an input of a sub-module of the target module, and an output of a sub-module of the target module,

the target module is a top module of the intellectual property block when the logical node is a top logical node, and is a module corresponding to a parent logical node of the logical node when the logical node is a non-top logical node.

responding the type of the logic node as a non-sub-module logic node, determining the output signal of the logic node, grabbing the non-sub-module logic node corresponding to the output signal to determine the hardware structure mark language code of the logic node,

The non-sub-module logic nodes are logic nodes which do not comprise sub-logic nodes.

In one possible implementation, the output signal includes an output or register level signal of a parent logical node corresponding module of the logical node, and the non-child logical node includes a non-child logical node determined based on the output and/or a non-child logical node determined based on the register level signal.

In one possible implementation, the target logic node obtained by grabbing includes a combination logic generating a target signal and all signals participating in the combination logic,

wherein, the target signal is an input signal of a logic node when the target logic node is an input logic node, and is an output signal of a logic node when the target logic node is a non-sub-module logic node.

In one possible implementation, the target logical node is added to the hardware structure markup language code of the logical node including the target logical node in a code reference or direct call manner.

In one possible implementation manner, the logical node information includes a code block corresponding to each logical node, where the building a tree-type data structure based on the logical node information includes:

Determining hierarchy information among code blocks corresponding to different logic nodes based on the logic node information;

based on the hierarchical information, a tree-type data structure is constructed.

In one possible implementation, the tree data structure includes a top level node, wherein the hardware structural markup language code of the intellectual property block is determined based on the hardware structural markup language code of the corresponding logical node of the top level node.

In one possible implementation, the hardware description language code is generated based on high-level programming language code of the intellectual property block.

The embodiment of the application also provides a transcoding device of the intellectual property block, which comprises:

the extraction module is used for determining logic node information based on module information obtained by extracting the hardware description language codes of the intellectual property blocks, wherein the logic node information represents that the hardware description language codes are abstracted into information corresponding to the logic nodes;

the first determining module is used for constructing a tree-type data structure based on the logic node information, wherein nodes of the tree-type data structure correspond to the logic nodes one by one;

and the second determining module is used for determining the hardware structure marking language code of each logic node based on the tree data structure and the logic node information so as to obtain the hardware structure marking language code of the intellectual property block.

In one possible implementation manner, the second determining module is configured to:

capturing input logic nodes corresponding to each input signal;

the sub-module logical nodes are logical nodes comprising sub-logical nodes.

In one possible implementation manner, the first determining module is configured to:

The embodiment of the application also provides a chip development system, which comprises the code conversion device in any embodiment.

The embodiment of the application also provides computer equipment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the method when executing the computer program.

Embodiments of the present application also provide a computer-readable storage medium storing a computer program which, when executed by a processor, implements the above-described method.

Embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the above method.

One of the beneficial effects of the embodiment of the application is that: the hardware description language codes of the intellectual property blocks are converted into the hardware structure marking language codes, so that the readability of the hardware IP codes is improved, and the development efficiency is improved.

Specific embodiments of the application are disclosed in detail below with reference to the following description and drawings, indicating the manner in which the principles of the application may be employed. It should be understood that the embodiments of the application are not limited in scope thereby. The embodiments of the application include many variations, modifications and equivalents within the spirit and scope of the appended claims. Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, proportional sizes, and the like of the respective components in the drawings are merely illustrative for aiding in understanding the present application, and are not particularly limited. Those skilled in the art with access to the teachings of the present application can select a variety of possible shapes and scale sizes to practice the present application as the case may be.

Fig. 1 shows a schematic diagram of a transcoding method of an intellectual property block according to an embodiment of the present application.

Fig. 2 shows a schematic diagram of the modules comprised by an intellectual property block of an embodiment of the present application.

FIG. 3 shows a schematic diagram of a tree data structure of an embodiment of the present application.

FIG. 4 is a flow chart of constructing a tree-type data structure according to an embodiment of the present application.

Fig. 5 shows a schematic diagram of a transcoding device according to an embodiment of the second aspect of the present application.

FIG. 6 shows a schematic diagram of a chip development system in accordance with an embodiment of the application.

Detailed Description

The technical solution of the present application will be described in detail below with reference to the attached drawings and specific embodiments, it should be understood that these embodiments are only for illustrating the present application and not for limiting the scope of the present application, and various modifications of equivalent forms of the present application will fall within the scope of the appended claims after reading the present application.

In the embodiments of the present application, the terms "first," "second," and the like are used to distinguish between different elements from each other by name, but do not indicate spatial arrangement or time sequence of the elements, and the elements should not be limited by the terms. The term "and/or" includes any and all combinations of one or more of the associated listed terms. The terms "comprises," "comprising," "including," "having," and the like, are intended to reference the presence of stated features, elements, components, or groups of components, but do not preclude the presence or addition of one or more other features, elements, components, or groups of components.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

Example of the first aspect

Fig. 1 shows a schematic diagram of a transcoding method of an intellectual property block according to an embodiment of the present application. In one possible implementation, the execution subject of the method of transcoding the intellectual property block may be a device of transcoding the intellectual property block, for example, the method of transcoding the intellectual property block may be executed by a terminal device or a server or other electronic device. The terminal device may be a User Equipment (UE), a mobile device, a User terminal, a computing device, or the like. In some possible implementations, the transcoding method of the intellectual property block may be implemented by way of a processor invoking computer readable instructions stored in a memory. As shown in fig. 1, the method includes:

In step S11, logic node information is determined based on module information obtained by extracting the hardware description language code of the intellectual property block, wherein the logic node information represents that the hardware description language code is abstracted into information corresponding to the logic node;

in step S12, a tree-type data structure is constructed based on the logical node information, wherein nodes of the tree-type data structure are in one-to-one correspondence with the logical nodes;

in step S13, a hardware structure markup language code of each logical node is determined based on the tree data structure and the logical node information, so as to obtain the hardware structure markup language code of the intellectual property block.

In this way, the hardware description language code of the intellectual property block can be converted into the hardware structure marking language code of the intellectual property block, the hardware description language code with lower readability of the intellectual property block can be converted into the hardware structure marking language code with higher readability, the readability of the code of the intellectual property block is improved, and the development efficiency is improved.

The intellectual property block may represent a circuit block design with independent functions in a chip, and may also be referred to as an intellectual property core or an IP core. In the present application, the intellectual property block may comprise at least one intellectual property sub-block, e.g. each intellectual property sub-block may correspond to a sub-function. The intellectual property block can also be used as an intellectual property sub-block of other intellectual property blocks, the intellectual property block or any intellectual property sub-block of the intellectual property block can be called by other intellectual property blocks, and the intellectual property block or any intellectual property sub-block of the intellectual property block can also call other intellectual property blocks, and the disclosure is not limited to this. Illustratively, an intellectual property block may correspond to a top-level module (or master module) that may invoke at least one sub-module, each of which may correspond to an intellectual property sub-block.

In the embodiment of the present application, the module information may be various kinds of information for describing the module corresponding to the intellectual property block, and may include information such as a type of the module, a name of the module, etc., and the module information may further include logic node information or may be used to confirm the logic node information, and the module information may be used to confirm the logic node information of at least one logic node. The hardware description language code can be obtained by abstracting the intellectual property block into logic nodes, wherein the logic nodes can be understood as nodes obtained by abstracting and expressing modules included in the hardware description language code of the intellectual property block, and different logic nodes can be obtained in different abstract modes. The logical node information may be extracted and determined based on module information of hardware description language codes of the intellectual property blocks. The hardware description language code can be generated based on the advanced programming language code of the intellectual property block, or can be obtained and written code, and the determination mode and form of the hardware description language code are not limited in the disclosure.

In some alternative embodiments, the hardware description language code may be a code file, including a file list of all hardware description language code, a file list of corresponding parameter packages, and so forth.

In an embodiment of the present application, the code file may be a preliminarily compiled file, for example, by a hardware description language compiler (VCS, synopsys) ^TM Etc.) is preliminarily compiled. The code file may be a code file with errors being located and corrected, so that the occurrence probability of an abnormality in the conversion process or the occurrence probability of errors contained in the converted hardware structure markup language code can be reduced.

In some alternative embodiments, the plurality of logical nodes of the hardware description language code abstraction of the intellectual property block have a hierarchical relationship that may characterize instantiated relationships between different ones of the plurality of logical nodes. For any one logical node, the logical node may or may not instantiate one or more other logical nodes. The logical node is the parent logical node of the other logical nodes it instantiates, and the other logical nodes instantiated are child logical nodes of the logical node. Illustratively, the hardware description language code of the intellectual property block may correspond to one top level module (e.g., the top level module may correspond to a top level logical node corresponding to a top level node of the tree data structure), where the top level logical node is a first level and its instantiated other sub-logical nodes (e.g., the logical nodes corresponding to the sub-modules of the top level module) are a second level. The other logical nodes instantiated by the logical nodes of the second level are the logical nodes of the third level, and so on. And determining that all logical nodes may include a top-level logical node and non-top-level logical nodes other than the top-level logical node based on whether the logical nodes are logical nodes corresponding to the top-level modules.

The logic node information represents information corresponding to the hardware description language code and is abstracted into logic node, the logic node information can be used for determining code blocks, parameters, functions and the like included in the logic node, can also be used for determining hierarchical relations among different logic nodes, types of the logic node, can also be used for determining input signals, output signals, processing logic, signal connection among different processing logic and combination logic of the logic node, and the like of the logic node, wherein the processing logic can be understood as logic from the input signals to the output signals, the combination logic can be processing logic related to the input signals and the output signals, for example, can be processing logic determined based on one output signal and involved in all input signals corresponding to the output signal, and can also be processing logic determined based on one input signal and involved in all signals corresponding to the generated input signal. The present disclosure is not limited to the representation of combinational logic, and may be, for example, combinational logic represented by means including, but not limited to, functions, parameters, and the like.

In some alternative embodiments, the input signal of the logical node is determined based on at least one of an input of the target module, an output of the target module, a register level signal of the target module, an input of a sub-module of the target module, and an output of a sub-module of the target module,

For example, in the case where the logical node is a top-level logical node corresponding to a top-level module of an intellectual property block, the input signal of the logical node may be determined based on the input of the top-level module. When the logical node is a non-top logical node, the target module may be a module corresponding to a parent logical node of the logical node. For example, the input signal of the logical node of the second hierarchy may be determined based on at least one of an input of the top-level module, an output of the top-level module, a register level signal of the top-level module, an input of a sub-module of the top-level module, and an output of a sub-module of the top-level module.

In some alternative embodiments, the output signal of a logical node may be the output and/or register level signal of a parent logical node corresponding module of that logical node. The register level signal may be a signal of storing data in a module corresponding to a parent logical node of the logical node.

It should be noted that, the logical node information may represent information corresponding to at least one logical node, and the disclosure does not limit content, form, category, number and use included in the logical node information.

In the embodiment of the disclosure, the module information for determining the logic node information of the hardware description language code of the intellectual property block may be obtained by scanning and analyzing the hardware description language code of the intellectual property block, where the logic node information obtained by scanning and analyzing may include information corresponding to all logic nodes. The logical node information characterizes the hardware description language code to be abstracted into information corresponding to the logical node,

for example, the hardware description language code of the intellectual property block may be scanned, parsed, module information obtained, and the logical nodes included in the module may be determined based on the module information, and for any one logical node, other logical nodes instantiated for that logical node may be searched or located. For example, the present disclosure is not limited in the manner in which logical node information of hardware description language code of an intellectual property block is determined by identifying a particular key (e.g., module) in the hardware description language code to search or locate to the logical node.

In the embodiment of the disclosure, based on the logic node information, a tree-type data structure is constructed, the nodes of the tree-type data structure are in one-to-one correspondence with the logic nodes, and the hierarchical relationship between all logic nodes obtained by abstracting the intellectual property blocks and different logic nodes can be determined based on the logic node information so as to construct the tree-type data structure, wherein the nodes of the tree-type data structure are in one-to-one correspondence with the logic nodes.

The logical node information may directly include a hierarchical relationship between different logical nodes, for example, in the process of determining the logical node information described above, the hierarchical relationship has been directly extracted, for example, a parent logical node of the logical node B includes a logical node a, the logical node B is a logical node of the same hierarchy as the logical node A1, the logical node A2, and the logical node A3, and a parent logical node of the logical node C includes a logical node B. The logical node information may not directly include the hierarchical relationship between different logical nodes, but further determine the hierarchical relationship between different logical nodes through the information included in the logical node information, for example, the code block corresponding to each logical node, and the method for constructing the tree-type data structure based on the logical node information is not limited in this disclosure.

Illustratively, each logical node may include a corresponding code block, the hierarchical relationship between the logical nodes may be embodied in the code blocks, the extracted logical node information includes the code blocks corresponding to the logical nodes, and the hierarchical information between the code blocks corresponding to different logical nodes may be determined by parsing and executing the codes of the code blocks. For example, a code block may represent an input signal, an output signal, and may determine a parent logical node and a child logical node of a current logical node based on the input signal, the output signal, and thus determine a tree data structure of the current logical node.

The parameters (e.g., input signals, output signals) included in the logic nodes can be calculated to obtain corresponding parameter values through a parameter extraction operation. The parameter extraction operation may be, for example, obtaining a path of a file where a corresponding code block of a top-level logical node (corresponding to a top-level module) is located according to a hardware description language code and a corresponding file list file, so as to obtain a corresponding code file, where the code file may be used to determine information related to a next-level logical node. For example, information about the next-level logical node may be obtained from a code file of any current-level logical node, for example, a code path of the next-level logical node, the number of instantiated next-level logical nodes, and the like, so that the next-level logical node may be obtained, and thus level information indicating a level relationship between the logical nodes may be obtained.

In the embodiment of the application, the input signal and the output signal of the logic node can be understood as parameters of the logic node, and the name of the parameters, the value of the parameters and the path of the parameters in the whole code file are focused in the hardware structure mark language. In addition, parameters in the markup language code can also include information such as the number of sub-logic node instantiations, interface bit width, code cycle number and the like, and in the embodiment of the application, the various parameters and the information related to the parameters can be obtained through analysis and calculation of the hardware description language code.

In this way, a tree data structure comprising nodes corresponding to the logic nodes one by one can be constructed, so as to further realize the conversion from the hardware description language code to the hardware structure markup language code.

In the embodiment of the disclosure, based on the tree data structure and the logic node information, determining a hardware structure markup language code of each logic node to obtain the hardware structure markup language code of the intellectual property block, which may be sequentially determining the hardware structure markup language code of each logic node, and determining the hardware structure markup language code of the logic node corresponding to the top node of the tree data structure, which is finally determined, as the hardware structure markup language code of the intellectual property block.

In some alternative embodiments, it may also be that a hardware structure markup language code corresponding to a logical node of at least a part of leaf nodes in a tree data structure is determined, and a hardware structure markup language code corresponding to a logical node of a non-leaf child node is determined, where determining a hardware structure markup language code corresponding to a logical node of at least a part of leaf nodes in a tree data structure may be parallel operation or serial operation, and the method of determining a hardware structure markup language code of each logical node based on the tree data structure and the logical node information is not limited in this disclosure.

In one possible implementation manner, the determining, based on the tree data structure and the logical node information, a hardware structure markup language code of each logical node may include:

In some alternative embodiments, the tree data structure may be traversed in a depth-first manner, and the hardware structure markup language code of each logical node is determined according to the logical node information, and it should be understood that the finally determined hardware structure markup language code of the logical node corresponding to the top node of the tree data structure may be directly determined as the hardware structure markup language code of the intellectual property block.

Traversing the tree data structure in a depth-first mode can ensure that the hardware structure markup language codes of each logic node are generated, and improves the accuracy of code conversion.

In some optional embodiments, it may also be that, in response to all the child nodes of the target node corresponding to the logical nodes having been generated or the target node being a leaf node, the hardware structure markup language code of the target node corresponding to the logical nodes is determined according to the logical node information, where the target node is any node of the tree data structure.

In this way, the generation process may be performed in parallel or in series, so that the hardware structural markup language code of each logical node may be more flexibly determined.

As previously described, the hardware structural markup language code of the intellectual property block may be determined based on the hardware structural markup language code of the corresponding logical node of the top level node of the tree data structure.

In the embodiment of the present disclosure, the logical nodes may include multiple types, for example, the types may include sub-module logical nodes and non-sub-module logical nodes, where a sub-module logical node may be understood as a logical node including sub-logical nodes, and the present disclosure does not limit the number of sub-logical nodes included in one sub-module logical node. Wherein a non-sub-module logical node may refer to an output of an intellectual property block based module and/or a register level signal determination that does not include any sub-logical nodes. It should be noted that, for the sub-module logical node, the type of the sub-module logical node included in the sub-module logical node may be a sub-module logical node, or may be a non-sub-module logical node. The type of logical node may be determined based on logical node information and/or tree data structures.

In the embodiment of the disclosure, the non-submodule logic node may further include a non-submodule output logic node and a non-submodule register logic node based on different types of output signals. For example, the logical node determined for the output signal based on the output of the module is a non-sub-module output logical node, and the logical node determined for the output signal based on the register level signal of the module is a non-sub-module register logical node.

It should be noted that, the manners of determining the hardware structural markup language codes of the different types of logical nodes may be different or the same, for example, the manners of determining the hardware structural markup language codes of the sub-module logical nodes and the non-sub-module logical nodes may be different. The determination mode of the hardware structure mark language codes of the non-submodule output logic node and the non-submodule register logic node can be the same. The hardware structural markup language code of the logical node may also be determined by a unified method without distinguishing types, which is not limited in this disclosure.

In one possible implementation, determining the hardware structural markup language code of each logical node may include:

Capturing input logic nodes corresponding to each input signal;

the sub-module logical nodes are logical nodes comprising sub-logical nodes.

For example, in case that the type of the logical node is determined to be a sub-module logical node according to the logical node information, for example, the logical node information includes the type of the logical node, or the logical node information may characterize that the logical node includes a sub-logical node, or in case that the sub-module logical node is determined to include a sub-logical node according to the tree data structure, the sub-logical node included in the logical node may be determined. For example, based on the tree data structure and/or the logical node information, it may be determined that the logical node is all child logical nodes corresponding to the parent logical node.

For example, the logical node may be a top-level logical node, which is a logical node of a first level, all logical nodes of a second level determined based on a tree data structure are child logical nodes of the top-level logical node, and the top-level logical node is a child module logical node including the child logical node.

For example, in case the logical node is a sub-module logical node, it may further comprise an input signal, which may be determined. For example, the input signal of the logical node may be determined based on the tree data structure and/or the logical node information.

The input logic nodes corresponding to each input signal can be captured, and the input logic nodes corresponding to the input signals of the logic nodes one by one are obtained. For example, each input signal may be generated from combinational logic based on one or more signals (e.g., an output signal of a parent logical node of a logical node, an input of a parent logical node corresponding module of a logical node, etc.), and an input logical node that grabs an input signal may be understood to grab combinational logic that generates the input signal and the corresponding one or more signals. For example, a combinational logic tree corresponding to each input signal may be constructed, and the input logic node corresponding to the input signal may be determined based on the combinational logic tree.

The hardware structure markup language code of the logical node may be determined based on all input logical nodes included by the logical node and all sub-logical nodes of the logical node. It should be understood that the hardware structure markup language code of all the sub-logic nodes of the logic node is a generated hardware structure markup language code by using a similar method, and the input logic node can be added into the hardware structure markup language code of the logic node by using a code reference or direct calling mode.

In this way, the hardware structure markup language code of the logical node with the type of the sub-module logical node can be efficiently and accurately generated, and the code storage space is saved.

It should be noted that, the input logical node may be obtained by grabbing during the process of determining the hardware structure markup language code of the logical node, and may not participate in the construction of the tree-type data structure.

For example, in a case that the type of the logical node is determined to be a non-sub-module logical node according to the logical node information, for example, the logical node information includes the type of the logical node, or the logical node information may indicate that the logical node does not include a sub-logical node, or in a case that the logical node is determined to not include a sub-logical node according to the tree data structure, for example, in a case that the logical node corresponds to a leaf node, the non-sub-module logical node corresponding to the output signal of the logical node is grabbed.

In the embodiment of the application, all the combination logics corresponding to the output signals can be grabbed, all the input signals corresponding to the combination logics are grabbed, and the output signals, the input signals and the combination logics are determined to be non-submodule logic nodes corresponding to the output signals. For example, a combinational logic tree corresponding to an output signal may be constructed, and a non-sub-module logic node corresponding to the output signal may be determined based on the combinational logic tree.

In this way, the non-sub-module logic node corresponding to the output signal of the logic node can be grabbed to determine the hardware structure markup language code of the logic node, and based on the hardware structure markup language code, the conversion from the hardware description language code to the hardware structure markup language code is realized.

For example, in grabbing an input logical node, the grabbing of the combinational logic that generated the input signal and all signals that participate in the combinational logic (e.g., including the input signal itself and one or more signals used to generate the input signal) may be determined as the input logical node. In the process of grabbing the non-sub-module logic node, the combinational logic corresponding to the grabbed output signals and all signals participating in the combinational logic (including, for example, the output signal itself and the input signal for generating the output signal) may be determined as the non-sub-module logic node.

In the process of grabbing the target logic node, the combination logic for generating the target signal can be determined by analyzing the corresponding hardware description language code. For example, the analysis of package, parameter, function and the like are performed to calculate and analyze the calculated parameters and the like, and the functions and the like are translated into the combinational logic of the target logical node.

In this way, the input logical nodes and/or the non-sub-module logical nodes may be determined to determine the hardware structural markup language code of the logical nodes.

In one possible implementation, the target logical node may be added to the hardware structure markup language code of the logical node including the target logical node in a code reference or direct call manner.

For example, in the case of grabbing a target logical node, it may be added to the hardware structure markup language code comprising the target logical node in a code reference or direct call manner. For example, the hardware description language code includes a code index therein, which may be used to locate code blocks and/or code lines. As described above, the grabbing obtaining the target logical node includes all signals participating in the combinational logic and the combinational logic, where the combinational logic and the code indexes corresponding to all signals participating in the combinational logic may be added to the hardware structure markup language code of the logical node including the target logical node by adopting a code referencing method. The direct call mode may be understood as copying and pasting code into the hardware structural markup language code of the logical node including the target logical node.

The fetched target logic node is stored in a code reference or direct calling mode without adding the target logic node into the hardware structure markup language code, so that the space and the storage space of the hardware structure markup language code are reduced, the code storage space can be effectively saved, and the flexibility is improved.

In the embodiment of the present application, in addition to the input signal and the output signal corresponding to the combinational logic, the hardware structure markup language code block may further include information of the logic node, for example, type information of the logic node, identification information of the logic node, and the like, which is not limited in this disclosure.

Fig. 2 shows a schematic diagram of the modules comprised by an intellectual property block of an embodiment of the present application. FIG. 3 shows a schematic diagram of a tree data structure of an embodiment of the present application. For ease of understanding, the transcoding method of the embodiments of the present disclosure is illustrated below with reference to fig. 2 and 3.

As shown in fig. 2, block a has an input 1, an output 1, a register stage signal d (register stage d for short), a register stage signal f (register stage f for short), and a sub-block (e.g., block B). The module B has an input 1, an input 2, an output 1, an output 2, a register stage signal C (register stage C for short) and a sub-module (e.g., module C). Wherein the input, output, etc. information of the module C is not shown.

Taking the module B as an example, it is a sub-module of the module a and is a parent module of the module C. Correspondingly, the logical node corresponding to the module B (logical node B) is a child logical node of the logical node corresponding to the module A (logical node A), and the logical node B is a father logical node of the logical node corresponding to the module C (logical node C). The logic node B is a sub-module logic node including sub-logic nodes, and based on the two outputs included in the module B and the register level signal c, three output signals of the logic node B and non-sub-module logic nodes corresponding to each output signal can be determined. The child logical nodes of logical node B may include logical node C and the three non-child logical nodes described above.

Accordingly, it may be determined that the sub-logical nodes included in the logical node a may be the logical node B and three non-sub-module logical nodes corresponding to the output 1, the register level d, and the register level signal f of the logical node a, respectively.

Based on this, the hierarchical relationship of the different logical nodes can be determined and the corresponding tree-type data structure constructed. As shown in fig. 3, the tree data structure in the figure includes a plurality of nodes, each corresponding to a logical node. For ease of understanding, the nodes of the tree data structure shown in FIG. 3 are labeled with information of the corresponding logical nodes of the nodes. As shown in fig. 3, the logical nodes corresponding to the nodes of the tree data structure include a logical node a, a non-sub-module output logical node A1, a non-sub-module register logical node A2, a non-sub-module register logical node A3, a logical node B, a logical node C, a non-sub-module output logical node B1, a non-sub-module output logical node B2, and a non-sub-module register logical node B3.

The non-submodule output logic node A1, the non-submodule register logic node A2, the non-submodule register logic node A3 and the logic node B are respectively child logic nodes of the logic node A, and the logic node A further comprises an input logic node x determined based on the input 1 of the module A.

The logic node C, the non-sub-module output logic node B1, the non-sub-module output logic node B2 and the non-sub-module register logic node B3 are respectively sub-logic nodes of the logic node B.

The type of the logic node B is a sub-module logic node, and the process of determining the hardware structure markup language code of the logic node with the type of the sub-module logic node comprises capturing an input logic node corresponding to an input signal of the logic node. As described above, the determining logic node B includes two input signals, and each input signal is captured by a corresponding input logic node. The y, z shown in fig. 3 can be understood as two input logical nodes corresponding to logical node B, respectively.

The following exemplarily describes a method of constructing a tree-type data structure, and it should be understood that the embodiments of the present disclosure do not limit the number of logical nodes, hierarchical relationships between logical nodes, and a method of constructing a tree-type data structure.

In the embodiment of the application, all relevant information corresponding to the top-level logical node can be determined based on the extracted logical node information, and the top-level node (or called a master root node) serving as a tree data structure is connected to a tree. The relevant total information corresponding to the top-level logical node may include a code block corresponding to the top-level logical node or any information related to the top-level logical node, for example, may include all sub-logical nodes included in the top-level logical node, an order of all sub-logical nodes, an input signal, an output signal, processing logic of the top-level logical node, information for indicating whether all sub-logical nodes of the logical node have been completely recorded (may be used to determine whether all sub-logical nodes are connected to a tree), such as a flag bit, so as to construct a complete and accurate tree-type data structure. In some optional embodiments, all relevant information determined by the logic node information may not include information for indicating whether all sub logic nodes of the logic node have been recorded, which may be a variable set in a tree data structure building method or program, and the disclosure does not limit types and numbers of relevant information corresponding to the top logic node.

For ease of understanding, the following description will be given by taking a flag bit as an example, for example, when the flag bit is a positive integer, there are child logical nodes that have not been recorded yet, and when the flag bit is 0, it is determined whether all the child logical nodes have been recorded completely, where the initialization value of the flag bit may be the number of child logical nodes included in the logical node.

FIG. 4 is a flow chart of constructing a tree-type data structure according to an embodiment of the present application. As shown in fig. 4, the build flow may include:

step 301, all relevant information of the master root node is acquired, connected to the tree, and then step 302 is entered.

Step 302, taking the current node as a temporary root node, reading all relevant information of the current node, and then entering step 303.

For example, when only the main root node is included in the tree, the main root node is set as a temporary root node, all information related to the main root node is read to perform the modularization processing of the main root node, and when the current node is a child node of the main root node, the child node is set as a temporary root node, all information related to the child node is read to perform the modularization processing of the child node. The modular processing of a node may represent the construction of code blocks called by the code blocks of the node on a tree-type data structure, see in particular the processing in steps 303, 304, 305, 306 and 308. The node modular processing may be used to construct a tree data structure.

Step 303, it is determined whether all the child nodes are operated, and if the determination result is that all the child nodes are not operated, step 304 is entered, otherwise step 309 is entered.

The operation in this step 303 indicates whether the child node representing the child module is connected to the tree, and may be confirmed by the flag bit information in the temporary root node, for example, when the flag bit is a positive integer, it is determined that all the child nodes are not operated, and when the flag bit is 0, it is determined that all the child nodes of the temporary root node have been operated, but the present application is not limited thereto, and the flag bit may also indicate whether all the child nodes are operated by other means.

In step 304, when it is determined that all the child nodes of the temporary root node are not operated, all the information related to the next child node is sequentially acquired according to the child node sequence of the temporary root node, and then step 305 is performed.

Step 305, determining whether the "next child node" obtained in step 304 is a leaf node, if yes, proceeding to step 306, otherwise proceeding to step 308.

Step 306, current child node information, i.e. child nodes connected to the tree as temporary root nodes, is recorded and leaf-nodelization is performed on the current child node, i.e. the current child node information does not include child node related information of the current child node, but only node information of the current child node itself, after which step 307 is entered.

Step 307, find the parent node of the current child node, update the parent node information, including updating the flag bit of the parent node, e.g., subtracting 1 from the value of the flag bit, and then return to step 302 until all child nodes of the temporary root node have been operated.

Step 308, record the current sub-node information, namely, the sub-node connected to the tree as the temporary root node, and perform intermediate nodelization on the current sub-node, that is, the current sub-node information includes the information related to the sub-node of the current sub-node, and then return to step 302 to perform the iterative construction process with the current sub-node as the temporary root node.

In step 309, if it is determined in step 303 that all child nodes of the temporary root node have been operated, it is determined whether the temporary root node is a master root node, if not, step 310 is entered, otherwise, the tree-type data structure construction flow is completed.

In step 310, if it is determined in step 309 that the temporary root node is not the master root node, a parent node of the temporary root node is found, and relevant information of the parent node is updated, for example, the flag bit is decremented by one, and then step 302 is returned, that is, the parent node found in step 310 is used as the temporary root node to perform the iterative construction process.

Taking the tree data structure shown in fig. 3 as an example, the logical nodes represented by A, B, C, B1, B2, B3, A1, A2 and A3 can be connected to the tree, so as to establish the tree data structure shown in fig. 3, wherein the nodes are in one-to-one correspondence with the logical nodes, each node is used for storing modularized information of hardware description language codes of the corresponding logical node, and the modularized information can be all relevant information corresponding to the logical node, which is determined based on the logical node information.

However, the present application is not limited thereto, and the tree data structure shown in fig. 3 may be constructed in other ways, for example, by connecting the nodes represented by the modules A, B, A1, A2, A3, C, B1, B2, and B3 to the tree in a breadth-first manner.

The manner in which the hardware structural markup language code of each logical node is determined based on the tree data structure and the logical node information to obtain the hardware structural markup language code of the intellectual property block will be exemplarily described below with reference to fig. 3.

For example, the tree data structure may be traversed in a depth-first manner, the hardware structural markup language codes of the corresponding logical nodes are generated in the order C, B, B2, B3, B, A1, A2, A3, a according to the logical node information, and the hardware structural markup language codes of the logical node a are determined as the hardware structural markup language codes of the intellectual property blocks. It may also be to generate hardware structure markup language code of the corresponding logical node according to C, B1, B2, B3, A1, A2, A3, B, A, where at least part of the generating operations of C, B1, B2, B3, A1, A2, A3 may be parallel operations.

According to the embodiment of the disclosure, the hardware description language code of the intellectual property block can be converted into the hardware structure marking language code of the intellectual property block, the hardware description language code with lower readability of the intellectual property block can be converted into the hardware structure marking language code with higher readability, the readability of the code of the intellectual property block is improved, and development efficiency is improved.

In the embodiment of the application, through the steps, the logic nodes of the hardware description language code can be divided and stored in a structured mode, the conversion operation is respectively carried out on each logic node, and the conversion from the whole hardware description language code to the hardware structure markup language code can be realized.

It should be noted that, in the case of traversing the tree data structure in a depth-first manner to generate the hardware structure markup language code, since a recursive depth-first tree operation is performed, all the sub-logic nodes called by the current top-level logic node have been processed, that is, all the hardware description language codes corresponding to all the sub-logic nodes have been converted into the hardware structure markup language code, in other words, all the information corresponding to all the sub-logic nodes has been recorded to generate the hardware structure markup language code, so that, for the current logic node, after completing the conversion operation of the hardware description language code corresponding to the logic node itself, all the conversion operation of the hardware description language code corresponding to the current logic node is completed.

It should be noted that, in the embodiment of the present application, the calculation and extraction process of any parameter in the hardware description language may be performed by using a depth-first tree structure and a depth-first tree traversal method.

For example, a tree-type data structure of parameters can be constructed by using a depth-first construction method, for example, for any one parameter, a file path of the parameter is obtained by scanning and analyzing a hardware description language code and a corresponding file list file, a "next-level" parameter corresponding to the parameter is grabbed after the file path of the parameter is obtained, a code is calculated, or the code is directly defined, then the file path of the next-level parameter and the path of the next-level parameter are directly defined, until the direct numerical definition of the parameter is grabbed, and the tree-type data structure of the parameter can be constructed by using a breadth-first traversal method. The tree-type data structure of the parameter can be a signal connection diagram, and any node in the tree-type data structure of the parameter can store the following information: the name of the current parameter, the value corresponding to the current parameter, all the parameters of the "next stage" corresponding to the current parameter, and the calculation code (or calculation logic).

However, the present application is not limited thereto, and for example, it is also possible to store all information of the hardware description language code of the intellectual property block including hierarchical information and module information through only one tree-shaped data structure, for example, store the input/output logic of the module in other forms of data format, for example, in the form of a table, and the present application is not limited thereto and may be selected according to actual needs.

Embodiments of the second aspect

Embodiments of the second aspect of the present application provide a transcoding transpose for intellectual property blocks, the specific implementation of which may refer to the implementation of the method of the embodiment of the first aspect, since the principle of solving the problem by the device is similar to that of the embodiment of the first aspect, and the description is not repeated here.

As shown in fig. 5, the transcoding device includes:

an extraction module 21, configured to determine logic node information based on module information obtained by extracting a hardware description language code of an intellectual property block, where the logic node information characterizes that the hardware description language code is abstracted into information corresponding to a logic node;

a first determining module 22, configured to construct a tree-type data structure based on the logical node information, where nodes of the tree-type data structure correspond to the logical nodes one by one;

a second determining module 23, configured to determine, based on the tree data structure and the logical node information, a hardware structure markup language code of each logical node to obtain a hardware structure markup language code of the intellectual property block.

capturing input logic nodes corresponding to each input signal;

the sub-module logical nodes are logical nodes comprising sub-logical nodes.

Embodiments of the third aspect

Embodiments of the third aspect of the present application provide a chip development system comprising a transcoding device as described in the embodiments of the second aspect, the contents of which are incorporated herein, specific implementations may refer to the description of the embodiments of the second aspect, and the description of which is not repeated.

Fig. 6 shows a schematic diagram of a chip development system according to an embodiment of the present application, as shown in fig. 6, the chip development system 1000 includes a code conversion device 900, where the code conversion device 900 may also be called a hardware IP design system program, and may implement flexible conversion between a markup language, a high-level programming language, and a hardware description language, thereby automatically completing conversion between different language codes of a hardware IP according to a developer's needs, and contributing to improvement of IP development efficiency.

In one or more embodiments, as shown in FIG. 6, the chip development system 1000 may include hardware, applications, and interactive interfaces.

In at least one embodiment, the hardware may comprise at least a processor capable of running the application and implementing the interactive interface function, which may be a CPU or GPU, and further, the hardware may comprise an FPGA (ACAP: xilinx) ^TM ) Memory, interconnect bus, etc.

In an embodiment of the present application, the application may include the transcoding device 900, and in addition, the application may include an industrial common operating system, such as a centOS ^TM . In addition, applications may also include EDA tools commonly used in the industry, such as Synopsys ^TM Design Compiler of company ^TM , Synopsys VCS ^TM Etc. In the embodiment of the application, the operating system runs on hardware and is mainly responsible for executing the application and realizing the function of the interaction interface. And may include a program capable of performing a deep learning process to assist in the implementation of the aforementioned functions.

In at least one embodiment, the application may further include sketch/block diagram drawing design software, such as hardware IP sketch design software, which may be used to assist in hardware IP preliminary sketch design, and further, the application may include software that implements markup language translation describing abstract functions and hardware structures of hardware IP into 2d,3d module views, i.e., hardware IP function/structure schematic software, implements module view generation, browsing, etc.

In one or more embodiments, the interactive interface may include an input/output device and a display device, where the input/output device may be, for example, a keyboard, a mouse, a touch pad, and the display device may be a display, and the display device may include, for example, a plurality of auxiliary displays, and may also include a cloud server and a local area network, so as to perform communications between the system and the developer.

The embodiment of the application also provides computer equipment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the code conversion method when executing the computer program.

Embodiments of the present application also provide a computer-readable storage medium storing a computer program that when executed by a processor implements the above-described transcoding method.

Embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the above-described transcoding method.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any suitable combination thereof to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the application, and is not meant to limit the scope of the application, but to limit the application to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the application are intended to be included within the scope of the application.

Claims

1. A method of transcoding an intellectual property block, the method comprising:

determining a hardware structural markup language code of each logical node based on the tree data structure and the logical node information to obtain a hardware structural markup language code of the intellectual property block,

wherein determining hardware structure markup language code for each logical node comprises:

under the condition that the type of the logic node is a sub-module logic node, determining a hardware structure marking language code of the logic node based on an input signal of the logic node and all sub-logic nodes, wherein the sub-module logic node is a logic node comprising the sub-logic node;

and under the condition that the type of the logic node is a non-sub-module logic node, determining a hardware structure marking language code of the logic node based on an output signal of the logic node, wherein the non-sub-module logic node is a logic node which does not comprise a sub-logic node.

2. The method of claim 1, wherein determining hardware structure markup language code for each logical node based on the tree data structure and the logical node information comprises:

3. The method of claim 1, wherein determining hardware structural markup language code for each logical node comprises:

capturing input logic nodes corresponding to each input signal;

and determining the hardware structure marking language code of the logic node based on all the input logic nodes and all the sub logic nodes of the logic node.

4. The method of claim 3, wherein the input signal of the logical node is determined based on at least one of an input of the target module, an output of the target module, a register level signal of the target module, an input of a sub-module of the target module, and an output of a sub-module of the target module,

5. The method of claim 1, wherein determining hardware structural markup language code for each logical node comprises:

and responding to the type of the logic node as a non-sub-module logic node, determining an output signal of the logic node, and grabbing the non-sub-module logic node corresponding to the output signal to determine a hardware structure mark language code of the logic node.

6. The method of claim 5, wherein the output signal comprises an output or register level signal of a parent logical node corresponding module of the logical node, and wherein the non-sub-module logical node comprises a non-sub-module output logical node determined based on the output and/or a non-sub-module register logical node determined based on the register level signal.

7. The method according to any one of claims 3 to 6, wherein the grabbing the resulting target logical node comprises generating a combination logic of target signals and all signals participating in the combination logic,

8. The method of claim 7, wherein a target logical node is added to a hardware structural markup language code of a logical node including the target logical node in a code reference or direct call manner.

9. The method of claim 1, wherein the logical node information includes a code block corresponding to each logical node, wherein the constructing a tree-type data structure based on the logical node information includes:

10. The method of claim 1, wherein the tree data structure comprises a top level node, and wherein the hardware structural markup language code of the intellectual property block is determined based on the hardware structural markup language code of the corresponding logical node of the top level node.

11. The method of claim 1, wherein the hardware description language code is generated based on high-level programming language code of the intellectual property block.

12. A transcoding apparatus of an intellectual property block, the transcoding apparatus comprising:

the extraction module is used for extracting module information obtained by the hardware description language codes of the intellectual property blocks and determining logic node information, wherein the logic node information represents that the hardware description language codes are abstracted into information corresponding to the logic nodes;

a second determining module for determining a hardware structure markup language code of each logical node based on the tree data structure and the logical node information to obtain the hardware structure markup language code of the intellectual property block,

13. A chip development system, characterized in that the system comprises a transcoding device as claimed in claim 12.

14. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 11 when the computer program is executed.

15. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 11.