CN116737473A - Memory reading and writing methods for chip verification and related devices - Google Patents

Abstract

Embodiments of the present application provide a chip-verified memory reading and writing method and related devices, including: obtaining a data reading request, where the data reading request includes a first address of data to be obtained expressed in a first language. ; Use the interface function to convert the first address expressed in the first language into the second address expressed in the second language; use the second language to convert the second address, determine the memory and obtain the granular address; according to the granular address, call the processing command of the memory, and read the data to be obtained stored at the second address. The embodiments of this application can realize multiple complex operations on the basis of multi-language interoperability during the reading of backdoor access, expand the applicable scope of backdoor access in the SOC verification process, meet the needs of memory function verification, and improve the verification efficiency. efficiency and correctness.

Description

Memory reading and writing methods for chip verification and related devices

Technical field

The present disclosure relates to simulation verification of electronic systems, and in particular to memory reading and writing methods for chip verification and related devices.

Background technique

When processing large amounts of data in SOC, data storage and subsequent data comparison will consume a lot of simulation time, reducing the verification speed. In addition, in the SOC system, read and write operations are performed using the same access method. At this time, if there is a problem during the memory access process, it is extremely difficult to detect and verification vulnerabilities are prone to occur. In order to solve the above problems, a backdoor method of accessing memory was introduced.

However, the existing backdoor method of accessing memory is to call the internal function of the memory based on the physical address in the verification environment and write it directly. Its scope of use is relatively small and is only suitable for simple IP verification, but in actual large-scale SOC verification , the situation is much more complicated.

Therefore, how to expand the applicable scope of backdoor access in SOC verification, meet the needs of memory function verification, and improve the efficiency and accuracy of verification has become an urgent technical problem that technicians in this field need to solve.

Contents of the invention

In view of this, embodiments of the present application provide a memory access method to expand the applicable scope of backdoor access in SOC verification, meet the needs of memory function verification, and improve the efficiency and accuracy of verification.

To achieve the above objectives, embodiments of the present invention provide the following technical solutions:

Embodiments of the present application provide a memory reading method for chip verification, including:

Obtain a data reading request, the data reading request includes a first address of the data to be obtained expressed in a first language;

Use the interface function to convert the first address expressed in the first language into the second address expressed in the second language;

Convert the second address using a second language, determine the memory and obtain the granular address;

According to the granular address, the processing command of the memory is called to read the to-be-used data stored at the second address.

retrieve data.

Optionally, the first language includes a general programming language, and the second language includes a hardware description language.

Optionally, the general programming language includes C++ language, and the hardware description language includes SystemVerilog language. Optionally, the first address includes a first virtual address, the second address includes a second virtual address, and using a second language to convert the second address, determine the memory and obtain the granular address includes:

Use a second language to convert the second virtual address to obtain a physical address;

Convert the physical address to obtain a granular address;

The corresponding memory is determined according to the physical address.

Optionally, the memory includes volatile memory or non-volatile memory.

Optionally, the method further includes splicing the read data of the granular addresses.

Embodiments of the present application also provide a memory writing method for chip verification, including:

Obtain a data write request, the data write request including a first address expressed in a first language and data to be written;

Use an interface function to convert the first address of the memory expressed in the first language and the data to be written into the second address and the data to be written expressed in the second language;

Convert the second address using a second language, determine the memory and obtain the granular address;

According to the granular address, a processing command of the memory is called to write the data to be written into the memory.

Optionally, the first language includes a general programming language, and the second language includes a hardware description language.

Optionally, the general programming language includes C++ language, and the hardware description language includes SystemVerilog language. Optionally, the first address includes a first virtual address, the second address includes a second virtual address, and using a second language to convert the second address, determine the memory and obtain the granular address includes:

Use a second language to convert the second virtual address to obtain a physical address;

Convert the physical address to obtain a granular address;

The corresponding memory is determined according to the physical address.

Optionally, the memory includes volatile memory or non-volatile memory.

Optionally, before the step of calling a processing command of the memory and writing the data to be written to the memory according to the granular address, the step further includes splitting the data to be written.

An embodiment of the present application also provides a memory reading device for chip verification, including:

An address acquisition module, configured to acquire a data reading request, where the data reading request includes a first address of data to be acquired expressed in a first language;

The language conversion module is used to use the interface function to convert the first address expressed in the first language into the second address expressed in the second language;

Address operation module: used to convert the second address using a second language, determine the memory and obtain the granular address;

A data reading module is configured to call a processing command of the memory according to the granular address and read the data to be obtained stored at the second address.

Optionally, the first address includes a first virtual address, the second address includes a second virtual address, and the address operation module is used to convert the second address using a second language, determine the memory, and obtain particles. address, including:

Use a second language to convert the second virtual address to obtain a physical address;

Convert the physical address to obtain a granular address;

The corresponding memory is determined according to the physical address.

Optionally, a data splicing module is also included, configured to splice the read data of the granular address.

An embodiment of the present application also provides a memory writing device for chip verification, including:

An address acquisition module, configured to acquire a data write request, where the data write request includes a first address expressed in a first language and data to be written;

A language conversion module, configured to use an interface function to convert the first address of the memory expressed in the first language and the data to be written into the second address expressed in the second language and the data to be written;

An address operation module, used to convert the second address using a second language, determine the memory and obtain the granular address;

A data writing module is configured to call a processing command of the memory according to the granular address, and write the data to be written into the memory.

Optionally, the first address includes a first virtual address, the second address includes a second virtual address, and the address operation module is configured to use a second language to convert the second address, determine memory and obtain granularity Address, including:

Use a second language to convert the second virtual address to obtain a physical address;

Convert the physical address to obtain a granular address;

The corresponding memory is determined according to the physical address.

Optionally, a data splitting module is also included for splitting the data to be written.

An embodiment of the present application further provides a chip configured as a chip-verified memory reading device or a chip-verified memory writing device as described above.

An embodiment of the present application also provides an electronic device, including the chip as described above.

An embodiment of the present application provides a memory reading method for chip verification, and obtains a data reading request. The data reading request includes the first address of the data to be obtained expressed in the first language; using the interface function, the first address of the data to be obtained is used. The first address expressed in one language is converted into the second address expressed in the second language; the second address is converted using the second language, the memory is determined and the granular address is obtained; according to the granular address, the memory is called Process the command to read the data to be obtained stored at the second address. In this way, during the SOC verification process, when using the backdoor to access and read the memory, the interface function is used to communicate with multiple languages. At the same time, in the second language, the address conversion and memory selection in the data path are performed. On the basis of multi-language interoperability, a variety of complex operations are realized, which expands the applicable scope of backdoor access in the SOC verification process, meets the needs of memory function verification, and improves the efficiency and correctness of verification.

Description of drawings

In order to explain the embodiments of the present application or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only This is an embodiment of the present application. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a memory access device for chip verification;

Figure 2 is a flow chart of a memory reading method for chip verification provided by an embodiment of the present application;

Figure 3 is a flow chart of the steps of determining the memory and obtaining the granular address of the memory reading method for chip verification provided by the embodiment of the present application;

Figure 4 is a flow chart of a memory writing method for chip verification provided by an embodiment of the present application;

Figure 5 is another flow chart of a memory writing method for chip verification provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of a memory reading device for chip verification provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a memory writing device for chip verification provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

In SOC (System-on-a-Chip, system-on-a-chip) verification, there are a large number of storage access operations. A storage access method includes the following steps: first, data is pre-stored, and the data obtained after simulating the memory operation of the DUT (Design under Test, device under test) is simulated; then the DUT performs actual memory operations; finally, the DUT performs actual memory operations. The data obtained from the operation is read and compared with the data obtained after simulating the DUT's memory operation to determine the correctness of the DUT's behavior.

The above method is a front-door access method for verifying memory operations. However, when processing a large amount of data, the pre-storage of data and the comparison of data after reading the data consume a lot of simulation time, resulting in a reduction in verification speed. In addition, in the SOC system, the verification of the memory is performed using the same access method. At this time, if there is a problem during the memory access process, it is extremely difficult to detect and verification loopholes are prone to occur.

To this end, you can use the backdoor method to access the memory. The backdoor access does not take up simulation time and can quickly operate the memory. When processing large amounts of data in memory access, the simulation efficiency is greatly improved and the verification speed is improved. In addition, by using front door access to write data and back door access to read data, or back door access to write data and front door access to read data, errors that occur in the front door operation can be detected, and the verification quality can be improved through a variety of verification methods. . However, for different types of storage, the backdoor access methods of the simulation models are also different, so there is no unified method that can be applied to most types of storage.

Figure 1 is a schematic structural diagram of a memory access device, including test terminal 1 and memory 2. When performing memory access verification, a backdoor method of accessing the memory is shown in Figure 1. Test terminal 1 calls the read and write functions in memory 2 , directly access the physical address in memory 2.

The above methods have limited functions and are only suitable for simple data comparison verification. However, actual large-scale SOC verification requires a large number of complex operations to be performed in sequence. The data needs to be processed multiple times during the verification, which involves issues such as virtual and real address conversion. If there are multiple storage devices, accessing the memory will involve the selection of storage devices. . In addition, in SOC verification, the verification language is a hardware description language, such as System Verilog or Verilog, and a general programming language, such as C language or C++ language, and simulation verification driver need to be used in the SOC. It can be seen that a variety of different methods need to be used in SOC verification. languages, and there is data interaction between these languages. Data interaction between these languages is also an important problem in SOC verification. Therefore, the existing technical solution cannot realize various complex data operations in SOC verification, and cannot realize interoperability between multiple languages. Therefore, the scope of backdoor access needs to be expanded.

In order to solve the aforementioned problems, embodiments of the present invention provide a memory reading method for chip verification. During the SOC verification process, when using backdoor access to read data, on the basis of multi-language interoperability, the address in the data path can be realized. The specific steps of this method are shown in Figure 2, including:

Step S11: Obtain a data reading request, where the data reading request includes a first address of the data to be obtained expressed in a first language.

Since data needs to be simulated and compared with actual operations in the test environment of SOC verification, in order to verify the memory function, a data read request needs to be obtained first.

In SOC verification, SOC-level stimulation requires the execution of a series of software operations. In order to access the memory, an address to access the memory needs to be generated. The data read request includes the first address of the data to be obtained.

Because during memory verification, the verification language is a hardware description language, while SOC verification requires the use of a general programming language to simulate the verification driver, so the languages of the two are different. Due to the limitation of the verification language of the backdoor verification method, the first address of the data to be obtained in the data reading request is expressed in the first language.

It is easy to understand that the first language is a language used for simulation verification driving, that is, a general programming language. A general programming language can achieve simulation verification driving more simply than a hardware description language.

Among them, the test environment refers to the hardware, software, equipment, data, etc. necessary to complete the test.

Step S12: Use the interface function to convert the first address expressed in the first language into the second address expressed in the second language.

As mentioned above, after obtaining the first address expressed in the first language, in order to implement the subsequent chip verification process, it needs to be converted into a second language that is convenient for verification.

Based on the foregoing description, it can be seen that the second language is a hardware description language. Compared with a general programming language, a hardware description language can more easily perform backdoor access to the memory and can directly operate the acquired data.

Specifically, the general programming language may include C++ language, and the hardware description language may be System Verilog language. System Verilog language, as a hardware description language, is also a verification language, so it can directly use the read memory data to perform verification operations. System Verilog language was designed with some concepts of C++ language and integrated object-oriented programming features. Therefore, C++ language is the best choice for use with System Verilog language.

language.

Through interface functions, data conversion between the two languages can be more easily achieved. In a specific implementation, the interface function includes a first language layer and a second language layer. Therefore, depending on the specific language used, the interface function with the corresponding two language layers can be replaced to perform communication between any two languages. Data conversion. It is easy to understand that when at least one of the first language or the second language changes, the interface function only needs to be replaced according to the type of language.

In an optional implementation, when the first language is the System Verilog language layer, the interface function may be a DPI (Direct Programming Interface, direct programming interface) interface function. DPI consists of two layers: the SystemVerilog layer and the second language layer. Both layers are isolated from each other. Which programming language is actually used in the second language layer has nothing to do with the System Verilog side of this interface, so the DPI interface can connect to the System Verilog language.

In an optional implementation, the interface function may include multiple instructions for calling functions with different names, where each instruction is used to call the execution of the corresponding function code.

Step S13: Use the second language to convert the second address, determine the memory and obtain the granular address.

In an optional implementation, the converted second address is a physical address expressed in the second language. In order to read the data, it is further necessary to determine the specific location of the data based on the second address.

As mentioned above, since computer equipment can often be provided with multiple memories of the same type or multiple different types, it is necessary to obtain the converted second address, that is, the physical address according to the obtained physical address. Determine the memory that needs to be accessed.

It is easy to understand that when the memory type is a memory, the memory is provided with multiple storage particles, and the storage particles are also called memory chips. These storage particles are composed of multiple storage matrices (Banks), also called Logical Banks. The structure of each Bank is similar to a large square grid array, and the number of grids in each Bank is the same. These grid arrays have many columns (Column) and many rows (Row), so that when accessing data in a certain grid, the position can be determined through the row and column information. Therefore, after obtaining the second address, the address needs to be converted into a granular address composed of the above bank, row, and column information that can access the granular memory before the data in the storage granule can be operated.

Please refer to Figure 3. In a specific implementation, in order to achieve verification of the chip when the obtained first address is a virtual address, that is, the first address includes the first virtual address, the first address obtained after conversion by the interface function is When the second address is also a second virtual address, step S13 of the memory reading method for chip verification provided by the embodiment of the present application may include:

Step S131: Use the second language to convert the second virtual address to obtain a physical address, and convert the physical address to obtain

Granular address.

The second language cannot directly use the second virtual address to directly access the memory. The virtual address needs to be converted into the physical address of the memory before it can continue to access the memory. Of course, the granular address also needs to be obtained through physical address conversion.

Step S132: Determine the corresponding memory according to the physical address.

After the physical address is obtained, the granular address and memory are further determined based on the physical address.

The specific method of determining the granular address will not be described again.

Since a computer device may often be provided with multiple memories of the same type or multiple different types, it is necessary to determine the memory to be accessed based on the obtained physical address after obtaining the physical address.

Step S14: According to the granular address, call the processing command of the memory to read the data to be obtained stored at the second address.

After obtaining the data, the second language can use the data for verification or cooperate with the SOC to perform other operations.

Since there are many types of memories, in order to adapt to the access needs of many different types of memories, the function that calls the internal commands of the memory can be changed, so that the internal commands of multiple types of memories can be called, which can be applied to multiple types of memory. memory.

Further, in an optional implementation, the memory includes volatile memory or non-volatile memory. Since the memory access method in the embodiment of the present application is to achieve backdoor access by calling the memory's own command, thereby realizing memory reading for chip verification, when the storage device is replaced, it is only necessary to change the calling function for different types of memory, and call The reading method of the corresponding memory is sufficient. Therefore, this method can be used not only for volatile memories such as memory as mentioned above, but also for non-volatile memories such as solid state drives.

The memory reading method for chip verification in the embodiment of the present application can use the interface function to realize the reading of backdoor access based on interoperability with multiple languages during the SOC verification process when using backdoor access to read the memory. At the same time, In the second language, address conversion and memory selection in the data path are performed, and in the reading of backdoor access, multiple complex operations can be performed on the basis of multi-language interoperability, which expands the scope of application of backdoor access. , to meet the needs of memory function verification and improve the efficiency and correctness of verification.

It should be noted that within the SOC, the SOC-level incentives are written using a general programming language, while actually performing the SOC verification operation requires the use of a special verification language, but usually the verification language is a hardware description language.

Therefore, in an alternative implementation, the first language is a general programming language and the second language is a hardware description language.

In an optional implementation, the general programming language is C++ language, and the hardware description language is SystemVerilog language.

Specifically, in SOC verification, because SOC-level incentives are implemented based on a set of simulation-driven software stacks in C++, the first language when initially obtaining and expressing the virtual address is preferably the C++ language. The second language is mainly used for memory access and virtual address translation. The preferred language at this time is SystemVerilog. SystemVerilog language is a hardware language that combines hardware description language (HDL) with modern high-level verification language (HVL). It is mainly used for chip implementation and verification processes. SystemVerilog has all the structures needed by chip design and verification engineers. It integrates features such as object-oriented programming, dynamic threads, and inter-thread communication, so it is easier to communicate with the C++ language and fully integrates the register transfer level circuit (Register Transfer level circuit). Level). Therefore, choosing the C++ language and SystemVerilog language to cooperate with the DPI interface function can make it easier to realize interoperability between the two languages and complete more complex transformation operations of virtual addresses.

In an optional implementation, as shown in Figure 2, step S14 may be followed by step S15: splicing the read data of the granular addresses.

When the data to be read is stored in multiple banks, the data is stored in a split state. Therefore, after reading the data in the storage particles, the data needs to be assembled into complete data before it can be transmitted and used. Follow-up operations.

Embodiments of the present invention also provide a memory writing method for chip verification, which can realize address conversion in the data path on the basis of multi-language interoperability when using backdoor access to write data during the SOC verification process, thereby realizing For memory verification, the specific steps of this method are shown in Figure 4, including:

Step S21: Obtain a data writing request, which includes a first address expressed in a first language and data to be written.

Since data needs to be simulated and compared with actual operations in the test environment of SOC verification, in order to verify the memory write function of chip verification, a data write request needs to be obtained first.

In SOC verification, the SOC level stimulus needs to perform a series of software operations, in which in order to access the memory, the address to access the memory needs to be generated, the first address included in the data write request. In order to write data, the write request also includes the data to be written.

Because during memory verification, the verification language is a hardware description language, while SOC verification requires the use of a general programming language to simulate the verification driver, so the languages of the two are different. Limited by the verification language of the backdoor verification method, the first address in the data writing request is expressed in the first language.

It is easy to understand that the first language is a language used for simulation verification driving, that is, a general programming language. A general programming language can achieve simulation verification driving more simply than a hardware description language.

Among them, the test environment refers to the hardware, software, equipment, data, etc. necessary to complete the test.

Step S22: Use an interface function to convert the first address of the memory expressed in the first language and the data to be written into the second address and the data to be written expressed in the second language.

As mentioned above, after obtaining the first address expressed in the first language, in order to implement the subsequent chip verification process, it needs to be converted into a second language that is convenient for verification.

Based on the foregoing description, it can be seen that the second language is a hardware description language, and a hardware description language can perform backdoor access to the memory more easily than a general-purpose programming language.

The language selection of the general programming language and the hardware description language is the same as the language selection in the memory reading method for chip verification provided by the embodiment of the present application, and will not be described again here. Through interface functions, data conversion between the two languages can be more easily achieved. In a specific implementation, the interface function includes a first language layer and a second language layer. Therefore, depending on the specific language used, the interface function with the corresponding two language layers can be replaced to perform communication between any two languages. Data conversion. It is easy to understand that when at least one of the first language or the second language changes, the interface function only needs to be replaced according to the type of language.

In an optional implementation, the same as the memory reading method for chip verification provided in the embodiment of the present application, when the required first language layer and second language layer are System Verilog language layer and C++ language layer, the The interface function is DPI.

In an optional implementation, the interface function may include multiple instructions for calling functions with different names, where each instruction is used to call the execution of the corresponding function code.

Step S23: Use the second language to convert the second address, determine the memory and obtain the granular address.

In an optional implementation, the converted second address is a physical address expressed in the second language. In order to write data, it is further necessary to determine the specific location where the data needs to be written based on the second address.

As mentioned above, since computer equipment can often be provided with multiple memories of the same type or multiple different types, it is necessary to obtain the converted second address, that is, the physical address according to the obtained physical address. Determine the memory that needs to be accessed.

Please refer to Figure 5. In a specific implementation, in order to realize the verification of the memory when the obtained first address is a virtual address, that is, the first address includes the first virtual address, the first address obtained after conversion by the interface function is When the second address is also a second virtual address, step S23 of the memory reading method for chip verification provided by the embodiment of the present application may include:

Step S231: Use the second language to convert the second virtual address to obtain a physical address, and convert the physical address to obtain a granular address;

The second language cannot directly use the virtual address to directly access the memory. The virtual address needs to be converted into the physical address of the memory before it can continue to access the memory, and the granular address also needs to be obtained through physical address conversion.

Step S232: Determine the corresponding memory according to the physical address.

After the physical address is obtained, the granular address and memory are further determined based on the physical address.

The specific method of determining the granular address will not be described again.

Since a computer device may often be provided with multiple memories of the same type or multiple different types, it is necessary to determine the memory to be accessed based on the obtained physical address after obtaining the physical address.

Step S24: According to the granular address, call the processing command of the memory to write the data to be written into the memory.

After the data is written, it can be verified by the second language or performed with the SOC to perform other operations.

Since there are many types of memories, in order to adapt to the access needs of many different types of memories, the function that calls the internal commands of the memory can be changed, so that the internal commands of multiple types of memories can be called, which can be applied to multiple types of memory. memory.

Further, in an optional implementation, the memory includes volatile memory or non-volatile memory. Since the memory access method in the embodiment of the present application is to achieve backdoor access by calling the memory's own command, thereby realizing memory reading for chip verification, when the storage device is replaced, it is only necessary to change the calling function for different types of memory, and call The reading method of the corresponding memory is enough. Therefore, this method can be used not only for volatile memories such as memory as mentioned above, but also for non-volatile memories such as solid state drives.

The memory writing method for chip verification in the embodiment of the present application can use the interface function to realize the writing of backdoor access based on the interoperability of multiple languages during the SOC verification process when using backdoor access to write to the memory. At the same time, In the second language, the address conversion in the data path is performed, and in the reading of backdoor access, multiple complex operations can be performed on the basis of multi-language interoperability, which expands the applicable scope of backdoor access and satisfies the memory function. The need for verification improves the efficiency and correctness of verification.

It should be noted that within the SOC, the SOC-level incentives are written using a general programming language, while actually performing the SOC verification operation requires the use of a special verification language, but usually the verification language is a hardware description language. Therefore, in an alternative implementation, the first language is a general programming language and the second language is a hardware description language.

In an optional implementation, the general programming language is C++ language, and the hardware description language is SystemVerilog language.

Specifically, in SOC verification, because SOC-level incentives are implemented based on a set of simulation driver software stacks in C++, the general programming language when initially obtaining and expressing the virtual address is preferably the C++ language. . Hardware description language is mainly used for memory access and virtual address translation. The preferred language at this time is System Verilog. System Verilog language is a hardware language that combines hardware description language (HDL) with modern high-level verification language (HVL). It is mainly used for chip implementation and verification processes. System Verilog has all the structures needed by chip design and verification engineers. It integrates features such as object-oriented programming, dynamic threads and inter-thread communication, so it is easier to communicate with the C++ language and comprehensively integrates the register conversion level circuit (Register Transfer Level). Therefore, choosing C++ language and System Verilog language can make it easier to realize interoperability between the two languages and complete more complex transformation operations of virtual addresses.

In an optional implementation, step S24 as shown in Figure 4 is preceded by step S25: splitting the data to be written.

In the memory device described in step S23, the data to be written needs to be split and stored in multiple banks. Therefore, before writing data to the storage particles, the data to be written needs to be split and corresponding bank, can be written to the memory granule.

In addition, the memory reading method and writing method for chip verification described in the embodiments of this application use the System Verilog language, so relying on its language characteristics that are suitable for a variety of different chip verification methodologies, this method can not only be used for SOC verification , can also be applied to monitors and can be directly used as a monitoring method to detect the correctness of memory data.

An embodiment of the present application also provides a memory reading device for chip verification, as shown in Figure 6, including:

Read data acquisition module 10: used to obtain data reading requests, the data reading requests include using the first language

Express the first address of the data to be obtained;

Language conversion module 11: used to use the interface function to convert the first address expressed in the first language into the second address expressed in the second language;

Data operation module 12: used to convert the second address using the second language, determine the memory and obtain the granular address;

Data reading module 13: configured to call the processing command of the memory according to the granular address and read the data to be obtained stored at the second address.

In a specific implementation, in order to realize the verification of the memory when the obtained first address is a virtual address, that is, the first address includes the first virtual address, and the second address obtained after conversion by the interface function is also the second address. When two virtual addresses are used, the memory reading device for chip verification provided by the embodiment of the present application may include:

Data operation module 12: used to convert the second address using the second language, determine the memory and obtain the granular address, including:

Use the second language to convert the second virtual address to obtain a physical address, convert the physical address to obtain a granular address; determine the corresponding memory according to the physical address.

After the physical address is obtained, the granular address and memory are further determined based on the physical address.

In an optional implementation, in the memory device as described above, the data to be read will be split and stored in multiple grids. Therefore, after reading the data in the storage particles, it is also necessary to These data are assembled into complete data before they can be transmitted and used for subsequent operations.

Therefore, as shown in FIG. 6 , the memory reading device for chip verification also includes a data splicing module 14 for splicing the read data of the granular address.

An embodiment of the present application also provides a memory writing device for chip verification, as shown in Figure 7, including:

Write data acquisition module 20: used to acquire a data write request, which includes a first address expressed in a first language and data to be written;

Language conversion module 21: used to use the interface function to convert the first address expressed in the first language into the second address expressed in the second language;

Data operation module 22: used to convert the second address using the second language, determine the memory and obtain the granular address;

Data writing module 23: According to the granular address, call the processing command of the memory to write the data to be written into the memory.

In a specific implementation, in order to realize the verification of the memory when the obtained first address is a virtual address, that is, the first address includes the first virtual address, and the second address obtained after conversion by the interface function is also the second address. When two virtual addresses are used, the memory writing device for chip verification provided by the embodiment of the present application may include:

The data operation module 22 is used to convert the second address using the second language, determine the memory and obtain the granular address, including:

Use the second language to convert the second virtual address to obtain a physical address, convert the physical address to obtain a granular address; determine the corresponding memory according to the physical address.

After the physical address is obtained, the granular address and memory are further determined based on the physical address.

In an optional implementation, in the memory device as described above, the data to be written needs to be split and stored in multiple grids. Therefore, as shown in Figure 7, when the data is written to the storage granule Before, a data splitting module 24 is also included, which is used to split the data to be written.

In particular, the above two memory access devices can be combined into one device, including all the above modules.

An embodiment of the present application also provides a chip. In the embodiment of the present application, the chip can be configured with any one or more of the above memory access devices.

An embodiment of the present application also provides an electronic device. In the embodiment of the present application, the electronic device can be configured with the above-mentioned chip.

Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims (20)

1. A memory read method for chip verification, comprising:

acquiring a data reading request, wherein the data reading request comprises a first address of data to be acquired expressed in a first language;

converting a first address expressed in a first language into a second address expressed in a second language using an interface function;

converting the second address by using a second language, determining a memory and obtaining a granular address;

and according to the granulating address, calling a processing command of the memory, and reading the data to be acquired stored in the second address.

2. The chip-authenticated memory reading method according to claim 1, wherein said first language includes a general-purpose programming language and said second language includes a hardware description language.

3. The chip-verified memory reading method of claim 2, wherein the general programming language comprises a c++ language and the hardware description language comprises a System Verilog language.

4. The chip-verified memory reading method of claim 1, wherein the first address comprises a first virtual address, the second address comprises a second virtual address, the converting the second address in the second language, determining the memory and obtaining the granular address, comprising:

translating the second virtual address using a second language to obtain a physical address;

converting the physical address to obtain a granular address;

and determining a corresponding memory according to the physical address.

5. The memory reading method of chip authentication of claim 1, wherein the memory comprises a volatile memory or a nonvolatile memory.

6. The method for reading a memory for chip verification according to claim 1, further comprising splicing the read data of the granular address.

7. A memory write method for chip verification, comprising:

acquiring a data writing request, wherein the data writing request comprises a first address expressed by using a first language and data to be written;

converting a first address of a memory expressed in a first language and the data to be written into a second address expressed in a second language and the data to be written by using an interface function;

converting the second address by using a second language, determining a memory and obtaining a granular address;

and according to the granulating address, calling a processing command of the memory, and writing the data to be written into the memory.

8. The chip-authenticated memory writing method according to claim 7, wherein said first language includes a general-purpose programming language and said second language includes a hardware description language.

9. The memory writing method of chip authentication of claim 8, wherein the general programming language comprises c++ language and the hardware description language comprises System Verilog language.

10. The chip-verified memory writing method of claim 7, wherein the first address comprises a first virtual address and the second address comprises a second virtual address, the translating the second address in the second language, determining memory and obtaining a granular address, comprising:

translating the second virtual address using a second language to obtain a physical address;

converting the physical address to obtain a granular address;

and determining a corresponding memory according to the physical address.

11. The memory writing method of chip authentication of claim 7, wherein the memory comprises a volatile memory or a nonvolatile memory.

12. The method for writing a memory for chip verification according to claim 7, wherein said step of calling a process command of said memory according to said granulated address to write data to be written into said memory further comprises splitting said data to be written into.

13. A memory read device for chip verification, comprising:

an address acquisition module for acquiring a data reading request including a first address of data to be acquired expressed in a first language;

a language conversion module for converting a first address expressed in a first language into a second address expressed in a second language using an interface function;

and the data operation module is used for: for translating the second address using a second language, determining a memory and obtaining a granular address;

and the data reading module is used for calling a processing command of the memory according to the granulating address and reading the data to be acquired stored in the second address.

14. The chip-authenticated memory reading device according to claim 13, wherein said first address comprises a first virtual address and said second address comprises a second virtual address, said data manipulation module for translating said second address using a second language, determining memory and obtaining a granular address, comprising:

translating the second virtual address using a second language to obtain a physical address;

converting the physical address to obtain a granular address;

and determining a corresponding memory according to the physical address.

15. The chip-authenticated memory reading apparatus according to claim 13, further comprising: and the data splicing module is used for splicing the read data of the granulating addresses.

16. A memory writing device for chip verification, comprising:

the address acquisition module is used for acquiring a data writing request, wherein the data writing request comprises a first address expressed by using a first language and data to be written;

the language conversion module is used for converting the first address of the memory expressed by using the first language and the data to be written into the second address expressed by using the second language and the data to be written by using the interface function;

the data operation module is used for converting the second address by using a second language, determining a memory and obtaining a granular address;

and the data writing module is used for calling a processing command of the memory according to the granulating address and writing the data to be written into the memory.

17. The chip-verified memory writing device of claim 16, wherein the first address comprises a first virtual address and the second address comprises a second virtual address, the data manipulation module: for translating the second address using a second language, determining a memory and obtaining a granular address, comprising:

translating the second virtual address using a second language to obtain a physical address;

converting the physical address to obtain a granular address;

and determining a corresponding memory according to the physical address.

18. The memory writing device of claim 16, further comprising a data splitting module for splitting the data to be written.

19. A chip, characterized in that the chip is configured as a chip-verified memory reading device according to any of claims 13-15 or as a chip-verified memory writing device according to any of claims 16-18.

20. An electronic device comprising the chip of claim 19.