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CN116705112A - Programmable logic unit in FPGA - Google Patents

Programmable logic unit in FPGA Download PDF

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Publication number
CN116705112A
CN116705112A CN202310807799.4A CN202310807799A CN116705112A CN 116705112 A CN116705112 A CN 116705112A CN 202310807799 A CN202310807799 A CN 202310807799A CN 116705112 A CN116705112 A CN 116705112A
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CN
China
Prior art keywords
switch
input
output
programmable logic
output end
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Pending
Application number
CN202310807799.4A
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Chinese (zh)
Inventor
曹正州
刘国柱
张艳飞
单悦尔
徐玉婷
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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Priority to CN202310807799.4A priority Critical patent/CN116705112A/en
Publication of CN116705112A publication Critical patent/CN116705112A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application discloses a programmable logic unit in an FPGA, which relates to the field of FPGAs, and adopts a COOL mode to realize programmable combination of different two-in-one selectors by using a switch, so that any logic circuit is realized by using any combination logic and register ratio, various core units in a sequential circuit and various common logic functions can be formed by programmable configuration, the functions are rich and excellent, the functions and the performances of the FPGA are improved, and the essential characteristics enable the FPGA to approach to basic ASIC units in fine granularity, thereby allowing a cell-based mapper similar to an ASIC to apply all optimization potentials of the ASIC.

Description

Programmable logic unit in FPGA
Technical Field
The application relates to the technical field of FPGA, in particular to a programmable logic unit in FPGA.
Background
FPGA (Field Programmable Gate Array ) has the advantages of abundant logic resources, high density, flexible programmability and the like, so that the FPGA is widely applied to the fields of signal processing, 5G communication, industrial control, artificial intelligence and the like.
PLE (Programmable Logic Element), a programmable logic unit, is core logic in an FPGA, where it is typically present in a matrix form. PLE is the most basic module unit for realizing the user programmable logic function in FPGA and has the highest logic resource quantity, so the function and performance of PLE directly determine the function and performance of FPGA, and the function and performance of PLE in FPGA are not good enough at present, and the performance of FPGA is limited.
Disclosure of Invention
The present inventors have proposed a programmable logic unit in an FPGA, aiming at the above problems and technical needs, and the technical scheme of the present application is as follows:
the programmable logic unit in the FPGA externally provides an input end X, an input end Y, an input end J, an input end K, an output end Z and an output end ZN, wherein the input end X is connected with a first signal processing circuit, the input end Y is connected with a second signal processing circuit, the input end J is connected with a third signal processing circuit, and the input end K is connected with a fourth signal processing circuit;
the output end of the first signal processing circuit is connected with the 1 end of the alternative selector MUX1, the 0 end of the MUX1 is connected with the output end ZN, and the output end of the third signal processing circuit is connected with the control end of the MUX 1;
The output end of the MUX1 is connected with the 1 end of the alternative selector MUX2 through a switch k12, and the input end X is also connected with the 1 end of the MUX2 through a first selection circuit; the input end X is also connected with the 0 end of the MUX2 through a second selection circuit, and the grounding end is also connected with the 0 end of the MUX2 through a third selection circuit; the output end of the second signal processing circuit is connected with the control end of the MUX 2;
the output end of the MUX2 is connected with the first input end of the NOR gate NOR, the output end of the third signal processing circuit is also connected with the second input end of the NOR gate NOR through a switch k20, the output end of the fourth signal processing circuit is also connected with the second input end of the NOR gate NOR through a switch k21, the output end of the NOR gate NOR is connected with the 1 end of the alternative selector MUX3 through a switch k30, and the output end of the NOR gate NOR is also connected with the 0 end of the MUX2 through an inverter NOT7 and a switch k19 in sequence;
the output end of the MUX1 is also connected with one end of a switch k25, the input end X is connected with one end of a switch k24, the other end of the switch k24 is connected with the other end of the switch k25 and is connected with the 0 end of the alternative selector MUX3 through a switch k32, the 0 end of the MUX3 is also connected with the grounding end through a switch k31, and the output end ZN is connected with the 0 end of the MUX3 through an inverter NOT9 and a switch k33 in sequence;
the input end X is also connected with a fourth selection circuit, the output end of the fourth selection circuit is connected with the 1 end of the MUX3 through a switch k29, the 1 end of the MUX3 is also connected with the grounding end through a switch k28, the output end of the MUX3 is connected with the 0 end of the alternative selector MUX4, and the output end of the second signal processing circuit is also connected with the control end of the MUX3 through an inverter NOT 10;
The output end of the fourth selection circuit is also connected with the 1 end of the MUX4 through a switch k26, the output end of the NOR gate NOR is also connected with the 1 end of the MUX4 through a switch k27, the output end of the third signal processing circuit is connected with the control end of the MUX4 through a switch k34, and the output end of the fourth signal processing circuit is connected with the control end of the MUX4 through a switch k 35;
the output end of the MUX4 is connected with the output end ZN through an inverter NOT11, and the output end of the inverter NOT11 is also connected with the output end Z through an inverter NOT 12;
each signal processing circuit is used for directly outputting an input signal or outputting an inverted signal of the input signal or continuously outputting a low-level signal, each selection circuit is used for directly outputting the input signal or outputting the inverted signal of the input signal, and each two-in-one selector gates a 1 end when the control end is a high-level signal and gates a 0 end when the control end is a low-level signal.
The beneficial technical effects of the application are as follows:
the application discloses a programmable logic unit in an FPGA, which also takes a two-in-one selector as a basic design unit, adopts a COOL mode to realize programmable combination of different two-in-one selectors by using a switch, thus realizing any logic circuit by using any combination logic and register ratio, and the essential characteristic enables the logic circuit to approach to a basic ASIC unit on fine granularity, thereby allowing an ASIC-like unit-based mapper to apply all optimization potentials. The programmable logic unit can be programmed and configured to form various core units and various common logic functions in the sequential circuit, including all LUT3 functions and part of LUT4 functions, and the latches, the D flip-flops and the clock trigger registers have rich functions and excellent performance, and are beneficial to improving the functions and the performances of the FPGA.
The Switch in the programmable logic unit is designed by using the sensor-Switch type pFASH, has the characteristics of no loss of power-down information, quick start of power-on and single-particle immunity, and meets the application of space environment and ground radiation environment.
Drawings
Fig. 1 is a circuit configuration diagram of a programmable logic unit in one embodiment of the present application.
Fig. 2 is a circuit diagram of a programmable logic cell configuration implemented as a D flip-flop with an enable and reset function in one embodiment of the application.
FIG. 3 is a circuit diagram of a programmable logic cell configuration implemented as a latch with enable in one embodiment of the application.
FIG. 4 is a circuit diagram of a programmable logic unit configuration implemented as a clocked register in one embodiment of the application.
Fig. 5 is a circuit diagram of a programmable logic cell configuration implemented as AND2 AND NAND2 in one embodiment of the application.
Fig. 6 is a circuit diagram of a programmable logic cell configuration implemented as AND3 AND NAND3 in one embodiment of the application.
Fig. 7 is a circuit diagram of a programmable logic cell configuration implemented as NOR2 and OR2 in one embodiment of the application.
Fig. 8 is a circuit diagram of a programmable logic cell configuration implemented as NOR3 and OR3 in one embodiment of the application.
Fig. 9 is a circuit diagram of a programmable logic unit configuration implemented as XOR2 in one embodiment of the application.
Fig. 10 is a circuit diagram of a programmable logic unit configuration implemented as XOR3 in one embodiment of the application.
Fig. 11 is a circuit diagram of a programmable logic cell configuration implementing a three-input exclusive or gate for generating a carry signal for a full adder in one embodiment of the application.
Fig. 12 is a circuit diagram of a programmable logic unit configuration implemented as INV in one embodiment of the application.
Fig. 13 is a circuit diagram of a programmable logic cell configuration implemented as AND4 AND NAND4 in one embodiment of the application.
Fig. 14 is a circuit diagram of a programmable logic cell configuration implemented as NOR4 and OR4 in one embodiment of the application.
Detailed Description
The following describes the embodiments of the present application further with reference to the drawings.
The application discloses a programmable logic unit in an FPGA, which is designed in a COOL (Choice Of Operational Logic) mode, wherein in Boolean logic operation, all logic operations can be realized through 2-input AND, OR and non-three most basic logic operations, and the total of 8 logic functions are obtained after degeneracy of any 2-input logic operation. In the COOL technology, the above three logic operations are replaced by the two-in-one selector, and the two-in-one selector can realize not only any logic operation with 2 inputs, but also 2 logic functions with outputs fixed to 0 (low level signal) or fixed to 1 (high level signal), so that 10 logic functions can be realized in total by the two-in-one selector. The application designs the programmable logic unit by combining the switch with the alternative selector to realize programmable combination, thereby expanding the functions and performances of the programmable logic unit.
In one embodiment, each Switch in the programmable logic unit designed by the application is realized by the sensor-Switch type pFASH, so that the requirements of large-scale logic resources of users can be met, a peripheral configuration memory is not needed, and the radiation resistance of the pFASH is obviously realized due to the SRAM unit, so that the programmable logic unit has the characteristics of high power-on starting speed, simple peripheral circuit, high resource density and good radiation resistance, and the FPGA has the advantages as a whole.
Referring to fig. 1, the programmable logic unit provides an input terminal X, an input terminal Y, an input terminal J, an input terminal K, an output terminal Z and an output terminal ZN to the outside.
In the programmable logic unit, an input end X is connected with a first signal processing circuit, an input end Y is connected with a second signal processing circuit, an input end J is connected with a third signal processing circuit, and an input end K is connected with a fourth signal processing circuit. The four signal processing circuits have the same circuit structure, and each signal processing circuit is used for directly outputting an input signal, outputting an inverted signal of the input signal, or continuously outputting a low-level signal.
In one embodiment, as shown in fig. 1, in the first signal processing circuit, one end of a switch k11 is connected to an input terminal of an inverter NOT3 and is connected to an input terminal X, an output terminal of the inverter NOT3 is connected to one end of a switch k10, one end of a switch k9 is connected to a ground terminal, and the other end of the switch k9, the other end of the switch k10, and the other end of the switch k11 are connected to an output terminal of the first signal processing circuit.
In the second signal processing circuit, one end of a switch k8 is connected with an input end of an inverter NOT2 and is connected with an input end Y, an output end of the inverter NOT2 is connected with one end of a switch k7, one end of a switch k6 is connected with a ground end, and the other end of the switch k6, the other end of the switch k7 and the other end of the switch k8 are connected and are connected with an output end of the second signal processing circuit.
In the third signal processing circuit, one end of a switch k5 is connected with an input end of an inverter NOT1 and is connected with an input end J, an output end of the inverter NOT1 is connected with one end of a switch k4, one end of the switch k3 is connected with a ground end, and the other end of the switch k3, the other end of the switch k4 and the other end of the switch k5 are connected with an output end of the third signal processing circuit.
In the fourth signal processing circuit, one end of a switch K2 is connected with an input end of an inverter NOT0 and is connected with an input end K, an output end of the inverter NOT0 is connected with one end of a switch K1, one end of the switch K0 is connected with a ground end, and the other end of the switch K0, the other end of the switch K1 and the other end of the switch K2 are connected and are connected with an output end of the fourth signal processing circuit.
The output end of the first signal processing circuit is connected with the 1 end of the alternative selector MUX1, the 0 end of the MUX1 is connected with the output end ZN, and the output end of the third signal processing circuit is connected with the control end of the MUX 1. The output end of the MUX1 is connected with the 1 end of the alternative selector MUX2 through a switch k12, and the input end X is also connected with the 1 end of the MUX2 through a first selection circuit; the input end X is also connected with the 0 end of the MUX2 through a second selection circuit, and the grounding end is also connected with the 0 end of the MUX2 through a third selection circuit; the output end of the second signal processing circuit is connected with the control end of the MUX 2.
The output end of the MUX2 is connected with the first input end of the NOR gate NOR, the output end of the third signal processing circuit is also connected with the second input end of the NOR gate NOR through a switch k20, the output end of the fourth signal processing circuit is also connected with the second input end of the NOR gate NOR through a switch k21, the output end of the NOR gate NOR is connected with the 1 end of the alternative selector MUX3 through a switch k30, and the output end of the NOR gate NOR is also connected with the 0 end of the MUX2 through an inverter NOT7 and a switch k19 in sequence.
The output end of the MUX1 is also connected with one end of a switch k25, the input end X is connected with one end of a switch k24, the other end of the switch k24 is connected with the other end of the switch k25 and is connected with the 0 end of the alternative selector MUX3 through a switch k32, the 0 end of the MUX3 is also connected with the grounding end through a switch k31, and the output end ZN is connected with the 0 end of the MUX3 through an inverter NOT9 and a switch k33 in sequence.
The input end X is also connected with a fourth selection circuit, the output end of the fourth selection circuit is connected with the 1 end of the MUX3 through a switch k29, the 1 end of the MUX3 is also connected with the grounding end through a switch k28, the output end of the MUX3 is connected with the 0 end of the alternative selector MUX4, and the output end of the second signal processing circuit is also connected with the control end of the MUX3 through an inverter NOT 10.
The output end of the fourth selection circuit is also connected with the 1 end of the MUX4 through a switch k26, the output end of the NOR gate NOR is also connected with the 1 end of the MUX4 through a switch k27, the output end of the third signal processing circuit is connected with the control end of the MUX4 through a switch k34, and the output end of the fourth signal processing circuit is connected with the control end of the MUX4 through a switch k 35.
The output terminal of the MUX4 is connected to the output terminal ZN through an inverter NOT11, and the output terminal of the inverter NOT11 is also connected to the output terminal Z through an inverter NOT 12.
In the above circuit configuration, each one-out-of-two selector gates the 1 terminal when the control terminal is a high level signal, and gates the 0 terminal when the control terminal is a low level signal.
The circuit structures of the selection circuits are the same, and each selection circuit is used for directly outputting an input signal or outputting an inverted signal of the input signal. In one embodiment, as shown in fig. 1, in the first selection circuit, one end of the switch k14 is connected to the input terminal of the inverter NOT4 and is connected to the input terminal X, the output terminal of the inverter NOT4 is connected to one end of the switch k13, and the other end of the switch k13 is connected to the other end of the switch k14 and is connected to the output terminal of the first selection circuit. In the second selection circuit, one end of a switch k18 is connected with an input end of an inverter NOT6 and is connected with an input end X, an output end of the inverter NOT6 is connected with one end of a switch k17, and the other end of the switch k17 is connected with the other end of the switch k18 and is connected with an output end of the second selection circuit. In the third selection circuit, one end of a switch k16 is connected with the input end of an inverter NOT5 and is connected with the ground end, the output end of the inverter NOT5 is connected with one end of a switch k15, and the other end of the switch k15 is connected with the other end of the switch k16 and is connected with the output end of the third selection circuit. In the fourth selection circuit, one end of a switch k23 is connected with an input end of an inverter NOT8 and is connected with an input end X, an output end of the inverter NOT8 is connected with one end of a switch k22, and the other end of the switch k22 is connected with the other end of the switch k23 and is connected with an output end of the fourth selection circuit.
Based on the programmable logic unit with the structure shown in fig. 1, the programmable logic unit can be configured to realize any logic function of three-input lookup table, four-input lookup table, D trigger with enabling and resetting functions, latch with enabling, clock trigger register and carry signal of full adder by controlling the on-off of each switch in the programmable logic unit, and the functions are rich. The programmable logic unit allows any logic circuit design to be implemented using any combinational logic to register ratio, an essential feature that makes it close to the basic ASIC (Application Specific Integrated Circuit) unit on a fine granularity, allowing ASIC-like cell-based mappers to apply all of their optimization potential.
Next, a method for implementing various logic functions by the programmable logic unit will be described by respective embodiments:
1. the programmable logic unit implements a D flip-flop with an enable and reset function.
In the sequential circuit, the D flip-flop DFF is a register with highest use frequency, and is a core unit of the sequential circuit, and as shown in fig. 2, the programmable logic unit is configured to implement the D flip-flop with the enabling and resetting functions by controlling the switch k1, the switch k5, the switch k8, the switch k10, the switch k12, the switch k19, the switch k21, the switch k27, the switch k30, the switch k33 and the switch k35 to be closed and controlling the other switches to be opened.
At this time, the input terminal X of the programmable logic unit is used as the input terminal D of the D flip-flop, the input terminal Y is used as the clock terminal CK of the D flip-flop, the input terminal J is used as the enable terminal EN of the D flip-flop, the input terminal K is used as the reset terminal R of the D flip-flop, the output terminal Z is used as the output terminal Q of the D flip-flop, and the output terminal ZN is used as the inverted output terminal QN of the D flip-flop.
2. The programmable logic unit implements a latch with enable.
Another important functional module in the sequential circuit is a LATCH, as shown in fig. 3, by controlling the switch k0, the switch k5, the switch k8, the switch k10, the switch k12, the switch k19, the switch k21, the switch k27, the switch k28, the switch k31 and the switch k34 to be closed and controlling the other switches to be opened, the programmable logic unit can be configured to implement the LATCH.
At this time, the input terminal X of the programmable logic unit is taken as the input terminal D of the latch, the input terminal Y is taken as the clock terminal CK of the latch, the input terminal J is taken as the enable terminal EN of the latch, and the output terminal Z is taken as the output terminal Q of the latch.
3. The programmable logic unit implements a clock triggered register.
The timing circuit is also provided with a register with special functions, namely a clock trigger register, which is applied to a timer and outputs a fixed logic signal through clock trigger. The input end of the DFF is grounded to obtain a low-level signal, so as to control the switch k1, the switch k5, the switch k8, the switch k9, the switch k12, the switch k19, the switch k21, the switch k27, the switch k30, the switch k33 and the switch k35 to be closed and control other switches to be opened, and the programmable logic unit can be configured to realize a clock trigger register as shown in fig. 4.
At this time, the input terminal Y of the programmable logic unit is used as the clock terminal CK of the clock trigger register, the input terminal J is used as the enable terminal EN of the clock trigger register, the input terminal K is used as the reset terminal R of the clock trigger register, the output terminal Z is used as the output terminal Q of the clock trigger register, and the output terminal ZN is used as the inverted output terminal QN of the clock trigger register. The input end of the clock trigger register is grounded by default, and the clock trigger register outputs a fixed logic signal under the triggering of a clock signal.
In summary, the control of the switches when the programmable logic unit configuration of the present application is implemented as various registers of the sequential circuit is as follows:
4. the programmable logic unit implements the logic function of a three-input look-up table (LUT 3).
In the combined logic operation, the inverter, the two-input AND gate and the NOR gate, and the three-input AND gate and the NOR gate are the most basic logic operation units, the application of the exclusive OR gate is also wider, and the exclusive OR gate can be used for realizing a parity generator, a controllable inverter, exclusive OR check and the like, and the logic function for realizing any 3-input can be configured by configuring different connection modes of one or two selectors in the programmable logic unit, and the method comprises the following steps:
(1) The configuration programmable logic unit is implemented as a two-input AND gate AND2 or a two-input NAND gate NAND2, as shown in fig. 5:
the control switches k3, k7, k23, k26, k29, k31 AND k34 are closed, AND the rest of the switches are opened, AND the programmable logic unit is implemented as a two-input AND gate AND2 or a two-input NAND gate NAND2.
When implemented as a two-input AND gate AND2, input X AND input Y are the two inputs of AND2, AND output Z is the output of AND2, where output z=x & Y of AND2.
When implemented as a two-input NAND gate NAND2, input X and input Y are the two inputs of NAND2, output ZN is the output of NAND2, at which time the output of NAND2
(2) The configuration programmable logic unit is implemented as a three-input AND gate AND3 or a two-input NAND gate NAND3, as shown in fig. 6:
the control switches k2, k4, k6, k14, k17, k20, k27, k28, k31 AND k35 are closed AND the rest are opened, AND the programmable logic unit is implemented as a three-input AND gate AND3 or a three-input NAND gate NAND3.
When implemented as a three-input AND gate AND3, input X, input Y, input K are the three inputs of AND3, AND output Z is the output of AND3, where output z=x & J & K of AND3.
When implemented as a three-input NAND gate NAND3, input X, input Y, input K are the three inputs of NAND3, output ZN is the output of NAND3, at which time the output of NAND3
(3) The configuration programmable logic unit is implemented as a two-input NOR gate NOR2 OR a two-input OR gate OR2 as shown in fig. 7.
The control switches k3, k8, k22, k29, k31 and k34 are closed, and the rest of the switches are opened, and the programmable logic unit is implemented as a two-input NOR gate NOR2 OR a two-input OR gate OR2.
When implemented as a two-input NOR gate NOR2, input X and input Y are the two inputs of NOR2 and output Z is the output of NOR2, at which time the output of NOR2
When implemented as a two-input OR gate OR2, input X and input Y are the two inputs of OR2, and output ZN is the output of OR2, at which point the output of OR2
(4) The configuration programmable logic unit is implemented as a three-input NOR gate NOR3 OR a three-input OR gate OR3 as shown in fig. 8.
The switches k1, k3, k7, k14, k15, k20, k27, k28, k31 and k35 are controlled to be closed, and the rest of the switches are controlled to be opened, so that the programmable logic unit is realized as a three-input NOR gate NOR3 OR a three-input OR gate OR3.
When implemented as a three-input NOR gate NOR3, input X, input Y, and input K are three inputs of NOR3, and output Z is an output of NOR3, at which time the output of NOR3
When implemented as a three-input OR gate OR3, input X, input Y, and input K are the two inputs of OR3, and output ZN is the output of OR3, where the output of OR3
(5) The configuration programmable logic unit is implemented as a two-input exclusive or gate XOR2, as shown in fig. 9.
Control switch k3, switch k7, switch k22, switch k24, switchk26, switch k29, switch k32 and switch k34 are closed, the remaining switches are controlled to be opened, the programmable logic unit is realized as a two-input exclusive-OR gate XOR2, the input end X and the input end Y are taken as two input ends of the XOR2, the output end Z is taken as the output end of the XOR2, and the output end of the XOR2 is taken as the output end of the XOR2
(6) The configuration programmable logic unit is implemented as a three-input exclusive or gate XOR3, as shown in fig. 10.
The control switches k0, k5, k8, k13, k18, k21, k24, k27, k30, k32 and k34 are closed, the rest of the switches are controlled to be opened, the programmable logic unit is realized as a three-input exclusive-OR gate XOR3, the input end X, the input end Y and the input end J are used as three input ends of the XOR3, the output end Z is used as the output end of the XOR3, and the output end of the XOR3 is used at the moment
(7) The programmable logic unit is configured to generate a carry signal for the full adder.
The three-input exclusive-or gate comparison is typically applied in adders, and can generate a summation signal in a 1-bit full adder, and a carry signal Co of the 1-bit full adder is represented by signals of two addend terminals X and Y and a carry signal K of a previous stage:
Co＝X&Y+X&K+Y&K；
the formula is converted and expressed in the form of a selector, and the conversion process is as follows:
based on this, as shown in fig. 11, by controlling the switch k2, the switch k3, the switch k7, the switch k13, the switch k16, the switch k20, the switch k23, the switch k27, the switch k29, the switch k31, and the switch k35 to be closed, the rest of the switches are controlled to be turned offThe programmable logic unit can be configured to generate the carry signal of the full adder. Input end X and input end Y are used as two addition ends of the full adder, input end K obtains the carry signal of the previous stage of the full adder, and output end Z outputs the carry signal of the full adder
(8) The configuration programmable logic unit is implemented as an inverter INV as shown in fig. 12.
The control switch k3, the switch k6, the switch k22, the switch k29, the switch k31 and the switch k34 are closed, the other switches are controlled to be opened, the programmable logic unit is realized as a NOT gate INV, the input end X is used as the input end of the INV, the output end Z is used as the output end of the INV, and the output end of the INV is used at the moment
In summary, the control of the switch when the configuration of the programmable logic unit of the present application is implemented as various logic functions of the three-input lookup table is as follows:
5. the programmable logic unit implements the logic function of a four-input look-up table.
The logic functions of the three-input lookup tables are realized by gating different switches, and the logic functions of more inputs can be decomposed into logic operations within three inputs. The four-input and gate and nor gate are often applied in address decoding circuits and digital timing detection, so that the programmable logic unit of the present application can also be configured to implement the functions of the four-input and gate and the four-input nor gate, and all four input terminals of the programmable logic unit are used at this time, which are respectively described as follows:
(1) The configuration programmable logic unit is implemented as a four-input AND gate AND4 or as a four-input NAND gate NAND4, as shown in fig. 13.
The switches k2, k4, k8, k13, k15, k20, k27, k28, k31 AND k35 are controlled to be closed, AND the rest of the switches are controlled to be opened, AND the programmable logic unit is implemented as a four-input AND gate AND4 or as a four-input NAND gate NAND4.
When the programmable logic unit is implemented as an AND4, the input terminal X, the input terminal Y, the input terminal J, AND the input terminal K are four input terminals of the AND4, the output terminal Z is an output terminal of the AND4, AND z=x & Y & J & K.
When the programmable logic unit is implemented as NAND4, input X, input Y, input J, and input K are the four inputs of NAND4, output ZN is the output of NAND4, and
on the basis of configuring the programmable logic unit to realize the logic function of the AND4 or the NAND4, the signal of the input end X is inverted by switching the on-off states of the switch K13 AND the switch K14, AND/or the signal of the input end Y is inverted by switching the on-off states of the switch K7 AND the switch K8, AND/or the signal of the input end J is inverted by switching the on-off states of the switch K4 AND the switch K5, AND/or the signal of the input end K is inverted by switching the on-off states of the switch K1 AND the switch K2, AND the AND4 AND the NAND4 comprising inverted signals are realized by expansion. Mainly comprising the following cases, which are not separately illustrated:
the control switches k2, k4, k8, k14, k15, k20, k27, k28, k31 AND k35 are closed, AND the rest of the switches are opened, AND the programmable logic unit is realized as a single inverting four-input AND gate AND4A or as a single inverting four-input NAND gate NAND4A, AND when realized as AND4A, the input ends X, Y AND J are input ends AND input terminal K as four input terminals of AND4A, output terminal Z as output terminal of AND4A, AND output terminal of AND4AWhen implemented as NAND4A, input X, input Y, input J, and input K are the four inputs of NAND4A, output ZN is the output of NAND4A, and output +.>
The control switch k2, the switch k4, the switch k7, the switch k14, the switch k15, the switch k20, the switch k27, the switch k28, the switch k31 AND the switch k35 are closed, AND the rest switches are controlled to be opened, AND the programmable logic unit is realized as a double-inverting four-input AND gate AND4B or as a double-inverting four-input NAND gate NAND4B. When implemented as an AND4B, input X, input Y, input J, AND input K are four inputs of AND4B, output Z is an output of AND4B, AND output z=x of AND4B&Y&J&K. When implemented as NAND4B, input X, input Y, input J, and input K are the four inputs of NAND4B, output ZN is the output of NAND4B, and the output of NAND4B
The control switch k2, the switch k5, the switch k7, the switch k14, the switch k15, the switch k20, the switch k27, the switch k28, the switch k31 AND the switch k35 are closed, AND the rest switches are controlled to be opened, AND the programmable logic unit is realized as a three-inverting four-input AND gate AND4C or as a three-inverting four-input NAND gate NAND4C. When implemented as AND4C, input X, input Y, input J, AND input K are the four inputs of AND4C, output Z is the output of AND4C, AND the output of AND4C When implemented as NAND4C, input X, input Y, input J, and input K are the four inputs of NAND4C, and output ZN is NAND4C, and the output of NAND4C +.>
(2) The configuration programmable logic unit is implemented as a four-input NOR gate NOR4 OR as a four-input OR gate OR4 as shown in fig. 14.
The switches k1, k5, k7, k14, k15, k20, k27, k28, k31 and k35 are controlled to be closed, and the rest of the switches are controlled to be opened, so that the programmable logic unit is implemented as a four-input NOR gate NOR4 OR as a four-input OR gate OR4.
When implemented as NOR4, input X, input Y, input J, and input K are four inputs to NOR4, output Z is an output of NOR4, and the output of NOR4
When OR4 is implemented, input X, input Y, input J, and input K are taken as four inputs of OR4, output ZN is taken as the output of OR4, and the output of OR4
Likewise, on the basis of configuring the programmable logic unit to be implemented as NOR4 OR4, the signal of the input terminal X is inverted by switching the on/off states of the switch K13 and the switch K14, and/OR the signal of the input terminal Y is inverted by switching the on/off states of the switch K7 and the switch K8, and/OR the signal of the input terminal J is inverted by switching the on/off states of the switch K4 and the switch K5, and/OR the signal of the input terminal K is inverted by switching the on/off states of the switch K1 and the switch K2, and the implementation of the NOR4 OR4 including the inverted signal is extended, which mainly includes the following cases not separately illustrated any more:
The control switch k1, the switch k5, the switch k7, the switch k13, the switch k15, the switch k20, the switch k27, the switch k28, the switch k31 and the switch k35 are closed, the rest switches are controlled to be opened, and the programmable logic unit is realized as a single-inversion four-input unitNOR gate NOR4A is alternatively implemented as a single inverting four-input OR gate OR4A. When implemented as NOR4A, input X, input Y, input J, and input K are four inputs to NOR4A, output Z is an output of NOR4A, and the output of NOR4AWhen implemented as OR4A, input X, input Y, input J, and input K are the four inputs of OR4A, output ZN is the output of OR4A, and the output of OR4A ∈>
The control switch k2, the switch k5, the switch k7, the switch k13, the switch k15, the switch k20, the switch k27, the switch k28, the switch k31 and the switch k35 are closed, and the rest switches are controlled to be opened, and the programmable logic unit is realized as a double-inversion four-input NOR gate NOR4B OR as a double-inversion four-input OR gate OR4B. When implemented as NOR4B, input X, input Y, input J, and input K are four inputs to NOR4B, output Z is an output of NOR4B, and the output of NOR4BWhen implemented as OR4B, input X, input Y, input J, and input K are the four inputs of OR4B, output ZN is the output of OR4B, and the output of OR4B ∈ >
The control switch k2, the switch k5, the switch k8, the switch k13, the switch k15, the switch k20, the switch k27, the switch k28, the switch k31 and the switch k35 are closed, and the rest switches are controlled to be opened, and the programmable logic unit is realized as a three-inverting four-input NOR gate 4C OR as a three-inverting four-input OR gate 4C. When implemented as NOR4C, input X, input Y, input J, and input K are four inputs to NOR4C, output Z is an output of NOR4C, and the output of NOR4CWhen implemented as OR4C, input X, input Y, input J, and input K are the four inputs of OR4C, output ZN is the output of OR4C, and the output of OR4C ∈>
In summary, the control of the switch when the configuration of the programmable logic unit of the present application is implemented as various logic functions of the four-input lookup table is as follows:
the above is only a preferred embodiment of the present application, and the present application is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present application are deemed to be included within the scope of the present application.

Claims (10)

1. The programmable logic unit in the FPGA is characterized in that an input end X, an input end Y, an input end J, an input end K, an output end Z and an output end ZN are externally provided, and the input end X is connected with a first signal processing circuit, the input end Y is connected with a second signal processing circuit, the input end J is connected with a third signal processing circuit, and the input end K is connected with a fourth signal processing circuit;
The output end of the first signal processing circuit is connected with the 1 end of the alternative selector MUX1, the 0 end of the MUX1 is connected with the output end ZN, and the output end of the third signal processing circuit is connected with the control end of the MUX 1;
the output end of the MUX1 is connected with the 1 end of the alternative selector MUX2 through a switch k12, and the input end X is also connected with the 1 end of the MUX2 through a first selection circuit; the input end X is also connected with the 0 end of the MUX2 through a second selection circuit, and the grounding end is also connected with the 0 end of the MUX2 through a third selection circuit; the output end of the second signal processing circuit is connected with the control end of the MUX 2;
the output end of the MUX2 is connected with the first input end of the NOR gate NOR, the output end of the third signal processing circuit is also connected with the second input end of the NOR gate NOR through a switch k20, the output end of the fourth signal processing circuit is also connected with the second input end of the NOR gate NOR through a switch k21, the output end of the NOR gate NOR is connected with the 1 end of the alternative selector MUX3 through a switch k30, and the output end of the NOR gate NOR is also connected with the 0 end of the MUX2 through an inverter NOT7 and a switch k19 in sequence;
the output end of the MUX1 is also connected with one end of a switch k25, the input end X is connected with one end of a switch k24, the other end of the switch k24 is connected with the other end of the switch k25 and is connected with the 0 end of the alternative selector MUX3 through a switch k32, the 0 end of the MUX3 is also connected with the grounding end through a switch k31, and the output end ZN is connected with the 0 end of the MUX3 through an inverter NOT9 and a switch k33 in sequence;
The input end X is also connected with a fourth selection circuit, the output end of the fourth selection circuit is connected with the 1 end of the MUX3 through a switch k29, the 1 end of the MUX3 is also connected with the grounding end through a switch k28, the output end of the MUX3 is connected with the 0 end of the alternative selector MUX4, and the output end of the second signal processing circuit is also connected with the control end of the MUX3 through an inverter NOT 10;
the output end of the fourth selection circuit is also connected with the 1 end of the MUX4 through a switch k26, the output end of the NOR gate NOR is also connected with the 1 end of the MUX4 through a switch k27, the output end of the third signal processing circuit is connected with the control end of the MUX4 through a switch k34, and the output end of the fourth signal processing circuit is connected with the control end of the MUX4 through a switch k 35;
the output end of the MUX4 is connected with the output end ZN through an inverter NOT11, and the output end of the inverter NOT11 is also connected with the output end Z through an inverter NOT 12;
each signal processing circuit is used for directly outputting an input signal or outputting an inverted signal of the input signal or continuously outputting a low-level signal, each selection circuit is used for directly outputting the input signal or outputting the inverted signal of the input signal, and each two-in-one selector gates a 1 end when the control end is a high-level signal and gates a 0 end when the control end is a low-level signal.
2. The programmable logic unit of claim 1, wherein the programmable logic unit is configured to implement any one of a three-input look-up table, a four-input look-up table, a D flip-flop with enable and reset functions, a latch with enable, a clock triggered register by controlling the on/off of each switch in the programmable logic unit.
3. The programmable logic unit of claim 1, wherein each Switch in the programmable logic unit is implemented by a sensor-Switch type pFLASH.
4. A programmable logic unit as claimed in claim 2, characterized in that,
in the first signal processing circuit, one end of a switch k11 is connected with an input end of an inverter NOT3 and is connected with an input end X, an output end of the inverter NOT3 is connected with one end of a switch k10, one end of a switch k9 is connected with a grounding end, and the other end of the switch k9, the other end of the switch k10 and the other end of the switch k11 are connected and are connected with an output end of the first signal processing circuit;
in the second signal processing circuit, one end of a switch k8 is connected with the input end of an inverter NOT2 and is connected with an input end Y, the output end of the inverter NOT2 is connected with one end of a switch k7, one end of a switch k6 is connected with a grounding end, and the other end of the switch k6, the other end of the switch k7 and the other end of the switch k8 are connected and are connected with the output end of the second signal processing circuit;
In the third signal processing circuit, one end of a switch k5 is connected with the input end of an inverter NOT1 and is connected with an input end J, the output end of the inverter NOT1 is connected with one end of a switch k4, one end of the switch k3 is connected with a grounding end, and the other end of the switch k3, the other end of the switch k4 and the other end of the switch k5 are connected and are connected with the output end of the third signal processing circuit;
in the fourth signal processing circuit, one end of a switch K2 is connected with the input end of an inverter NOT0 and is connected with an input end K, the output end of the inverter NOT0 is connected with one end of a switch K1, one end of the switch K0 is connected with a grounding end, and the other end of the switch K0, the other end of the switch K1 and the other end of the switch K2 are connected and are connected with the output end of the fourth signal processing circuit;
in the first selection circuit, one end of a switch k14 is connected with an input end of an inverter NOT4 and is connected with an input end X, an output end of the inverter NOT4 is connected with one end of a switch k13, and the other end of the switch k13 is connected with the other end of the switch k14 and is connected with an output end of the first selection circuit;
in the second selection circuit, one end of a switch k18 is connected with the input end of an inverter NOT6 and is connected with an input end X, the output end of the inverter NOT6 is connected with one end of a switch k17, and the other end of the switch k17 is connected with the other end of the switch k18 and is connected with the output end of the second selection circuit;
In the third selection circuit, one end of a switch k16 is connected with the input end of an inverter NOT5 and is connected with a ground end, the output end of the inverter NOT5 is connected with one end of a switch k15, and the other end of the switch k15 is connected with the other end of the switch k16 and is connected with the output end of the third selection circuit;
in the fourth selection circuit, one end of a switch k23 is connected with an input end of an inverter NOT8 and is connected with an input end X, an output end of the inverter NOT8 is connected with one end of a switch k22, and the other end of the switch k22 is connected with the other end of the switch k23 and is connected with an output end of the fourth selection circuit.
5. The programmable logic unit of claim 4, wherein the method for implementing the D flip-flop with the enable and reset functions by configuring the programmable logic unit by controlling the on-off of the individual switches in the programmable logic unit comprises:
control switch k1, switch k5, switch k8, switch k10, switch k12, switch k19, switch k21, switch k27, switch k30, switch k33 and switch k35 to be closed, and control the other switches to be opened;
the input end X is used as an input end D of the D trigger, the input end Y is used as a clock end CK of the D trigger, the input end J is used as an enabling end EN of the D trigger, the input end K is used as a reset end R of the D trigger, the output end Z is used as an output end Q of the D trigger, and the output end ZN is used as a reverse output end QN of the D trigger.
6. The programmable logic unit of claim 4, wherein the method of configuring the programmable logic unit to implement an enabled latch by controlling the on-off of each switch in the programmable logic unit comprises:
control switch k0, switch k5, switch k8, switch k10, switch k12, switch k19, switch k21, switch k27, switch k28, switch k31 and switch k34 to be closed, and control the other switches to be opened;
input X is the input D of the latch, input Y is the clock CK of the latch, input J is the enable EN of the latch, and output Z is the output Q of the latch.
7. The programmable logic unit of claim 4, wherein the method for implementing a clock triggered register by controlling the on-off of each switch in the programmable logic unit to configure the programmable logic unit comprises:
control switch k1, switch k5, switch k8, switch k9, switch k12, switch k19, switch k21, switch k27, switch k30, switch k33 and switch k35 to be closed, and control the other switches to be opened;
the input end Y is used as a clock end CK of the clock trigger register, the input end J is used as an enabling end EN of the clock trigger register, the input end K is used as a reset end R of the clock trigger register, the output end Z is used as an output end Q of the clock trigger register, and the output end ZN is used as a reverse output end QN of the clock trigger register; the input end of the clock trigger register is grounded by default, and the clock trigger register outputs a fixed logic signal under the triggering of a clock signal.
8. The programmable logic unit of claim 4, wherein the method for implementing the logic function of the three-input lookup table by controlling the on-off of each switch in the programmable logic unit comprises:
the control switch k3, the switch k7, the switch k23, the switch k26, the switch k29, the switch k31 AND the switch k34 are closed, AND the rest of the switches are controlled to be opened, AND the programmable logic unit is realized as a two-input AND gate AND2 or a two-input NAND gate NAND2; input terminal X AND input terminal Y are used as two input terminals of AND2, AND output terminal Z is used as output terminal of AND2; the input end X and the input end Y are used as two input ends of the NAND2, and the output end ZN is used as an output end of the NAND2;
the control switch k2, the switch k4, the switch k6, the switch k14, the switch k17, the switch k20, the switch k27, the switch k28, the switch k31 AND the switch k35 are closed, AND the rest of the switches are controlled to be opened, AND the programmable logic unit is realized as a three-input AND gate AND3 or a three-input NAND gate NAND3; input end X, input end Y, input end K as three input ends of AND3, output end Z as output end of AND3; input end X, input end Y, input end K are used as three input ends of NAND3, and output end ZN is used as output end of NAND3;
The switch k3, the switch k8, the switch k22, the switch k29, the switch k31 and the switch k34 are controlled to be closed, and the other switches are controlled to be opened, and the programmable logic unit is realized as a two-input NOR gate NOR2 OR a two-input OR gate OR2; input terminal X and input terminal Y are two input terminals of NOR2, and output terminal Z is an output terminal of NOR 2; the input end X and the input end Y are used as two input ends of OR2, and the output end ZN is used as an output end of OR2;
the control switch k1, the switch k3, the switch k7, the switch k14, the switch k15, the switch k20, the switch k27, the switch k28, the switch k31 and the switch k35 are closed, the rest switches are controlled to be opened, and the programmable logic unit is realized as a three-input NOR gate NOR3 OR a three-input OR gate OR3; input terminal X, input terminal Y and input terminal K are three input terminals of NOR3, and output terminal Z is an output terminal of NOR 3; input end X, input end Y and input end K are used as two input ends of OR3, and output end ZN is used as an output end of OR3;
the control switch k3, the switch k7, the switch k22, the switch k24, the switch k26, the switch k29, the switch k32 and the switch k34 are closed, and the rest of the switches are controlled to be opened, the programmable logic unit is realized as a two-input exclusive-OR gate XOR2, the input end X and the input end Y are used as two input ends of the XOR2, and the output end Z is used as an output end of the XOR 2;
The control switches k0, k5, k8, k13, k18, k21, k24, k27, k30, k32 and k34 are closed, and the rest of the switches are controlled to be opened, the programmable logic unit is realized as a three-input exclusive-OR gate XOR3, the input end X, the input end Y and the input end J are used as three input ends of the XOR3, and the output end Z is used as an output end of the XOR 3;
the control switch k3, the switch k6, the switch k22, the switch k29, the switch k31 and the switch k34 are closed, and the rest switches are controlled to be opened, the programmable logic unit is realized as a NOT gate INV, the input end X is used as the input end of the INV, and the output end Z is used as the output end of the INV.
9. The programmable logic unit of claim 4, wherein the method for configuring the programmable logic unit to generate the carry signal of the full adder by controlling the on-off of each switch in the programmable logic unit comprises:
control switch k2, switch k3, switch k7, switch k13, switch k16, switch k20, switch k23, switch k27, switch k29, switch k31 and switch k35 to be closed, and control the other switches to be opened;
the input end X and the input end Y are used as two addition ends of the full adder, the input end K obtains the carry signal of the upper stage of the full adder, and the output end Z outputs the carry signal of the full adder.
10. The programmable logic unit of claim 4, wherein the method for implementing the logic function of the four-input lookup table by controlling the on-off of each switch in the programmable logic unit comprises:
control switch k2, switch k4, switch k8, switch k13, switch k15, switch k20, switch k27, switch k28, switch k31 and switch k35, closing AND controlling the other switches to be opened, wherein the programmable logic unit is realized as a four-input AND gate AND4 or a four-input NAND gate NAND4; input X, input Y, input J AND input K are taken as four inputs of AND4, output Z is taken as output of AND4, AND z=x&Y&J&K, performing K; input X, input Y, input J and input K are taken as four inputs of NAND4, output ZN is taken as an output of NAND4, and
the control switch k1, the switch k5, the switch k7, the switch k14, the switch k15, the switch k20, the switch k27, the switch k28, the switch k31 and the switch k35 are closed, and the rest switches are controlled to be opened, and the programmable logic unit is realized as a four-input NOR gate NOR4 OR as a four-input OR gate OR4; input X, input Y, input J and input K are four inputs of NOR4, output Z is an output of NOR4, and Input X, input Y, input J and input K are taken as four inputs of OR4, output ZN is taken as an output of OR4, and +.>
On the basis of configuring the programmable logic unit to realize any one logic function of AND4, NAND4, NOR4 AND OR4, inverting the signal of the input end X by switching the on-off states of the switch K13 AND the switch K14, AND/OR inverting the signal of the input end Y by switching the on-off states of the switch K7 AND the switch K8, AND/OR inverting the signal of the input end J by switching the on-off states of the switch K4 AND the switch K5, AND/OR inverting the signal of the input end K by switching the on-off states of the switch K1 AND the switch K2, the expansion realization of the AND4, NAND4, NOR4 AND OR4 comprising inverting the signal is realized.
CN202310807799.4A 2023-07-03 2023-07-03 Programmable logic unit in FPGA Pending CN116705112A (en)

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