CN116683760A - Charge pump circuit, memory and electronic equipment - Google Patents

Abstract

The disclosure provides a charge pump circuit, a memory and electronic equipment, and relates to the technical field of circuits. The charge pump circuit includes: a charge pump, each stage of charge pump comprising a charge pump capacitor; the charge pump capacitance adjusting circuit is used for detecting the power supply voltage of the charge pump circuit, and adjusting the charge pump capacitance of each stage of charge pump to be a first capacitance value when the power supply voltage is greater than or equal to a voltage threshold value; when the power supply voltage is smaller than the voltage threshold value, adjusting the charge pump capacitance of each stage of charge pump to be a second capacitance value; wherein the first capacitance value is smaller than the second capacitance value. The charge pump circuit is capable of reducing the output voltage ripple of the charge pump circuit while maintaining the current capability of the charge pump circuit.

Description

Charge pump circuit, memory and electronic equipment

Technical Field

The disclosure relates to the technical field of circuits, and in particular relates to a charge pump circuit, a memory and electronic equipment.

Background

In a memory, such as a Flash (Flash memory) circuit, a charge pump is required to provide high voltage to operate the memory cells differently. The ripple of the output voltage of the charge pump affects the accuracy of the operation of the memory cell. The ability of the charge pump to output current increases with increasing supply voltage. The area of the charge pump capacitance (referred to as the charge pump capacitance) is designed to the current capability at low voltage, thereby resulting in a severe excess of the current capability of the charge pump at high voltage, resulting in a large output voltage ripple.

As described above, how to reduce the output voltage ripple of the charge pump at high voltage without reducing the current capability of the charge pump at low voltage is a problem to be solved.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide a charge pump circuit, a memory, and an electronic device capable of reducing output voltage ripple of a charge pump at a high voltage without reducing current capability of the charge pump at a low voltage, at least to some extent.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to an aspect of the present disclosure, there is provided a charge pump circuit including: a charge pump, each stage of charge pump comprising a charge pump capacitor; the charge pump capacitance adjusting circuit is used for detecting the power supply voltage of the charge pump circuit, and adjusting the charge pump capacitance of each stage of charge pump to be a first capacitance value when the power supply voltage is greater than or equal to a voltage threshold value; when the power supply voltage is smaller than the voltage threshold value, adjusting the charge pump capacitance of each stage of charge pump to be a second capacitance value; wherein the first capacitance value is smaller than the second capacitance value.

According to some exemplary embodiments of the present disclosure, the charge pump capacitance adjustment circuit includes a supply voltage detection circuit including a first voltage dividing resistor, a second voltage dividing resistor, and a comparator; the first end of the first voltage dividing resistor is connected with the power supply voltage, the second end of the first voltage dividing resistor is connected with the first end of the second voltage dividing resistor and the second input end of the comparator, and the second end of the second voltage dividing resistor is grounded so that the second input end of the comparator is used for receiving the divided voltage of the power supply voltage; the first input end of the comparator is used for receiving a reference voltage; the output end of the comparator is used for outputting a comparison voltage, and when the divided voltage is greater than or equal to the reference voltage, the comparison voltage is a first voltage value so as to judge that the power supply voltage is greater than or equal to the voltage threshold value; when the divided voltage is smaller than the reference voltage, the comparison voltage is a second voltage value to determine that the power supply voltage is smaller than the voltage threshold.

According to some exemplary embodiments of the present disclosure, the charge pump circuit further includes a clock driving circuit for outputting a first clock signal and a second clock signal; the charge pump comprises a first-stage charge pump, a charge pump capacitor of the first-stage charge pump comprises a first capacitor and a second capacitor, and a first end of the first capacitor and a first end of the second capacitor are connected with a boost node of the first-stage charge pump; the second end of the first capacitor is used for receiving the first clock signal, and the second end of the second capacitor is used for receiving the second clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the second clock signal to be a direct current voltage so that the charge pump capacitance of the first stage charge pump is the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the first clock signal and the second clock signal to be in-phase signals so that the charge pump capacitance of the first stage charge pump is the second capacitance value.

According to some exemplary embodiments of the present disclosure, the clock driving circuit includes: the input end of the first inverter is used for receiving an initial clock signal; the input end of the time delay unit is connected with the output end of the first phase inverter; the input end of the second inverter is connected with the output end of the delay unit; the input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter is used for outputting the first clock signal; the first input end of the first NAND gate is connected with the output end of the second inverter, the second input end of the first NAND gate is used for receiving the comparison voltage, and the output end of the first NAND gate is used for outputting the second clock signal.

According to some exemplary embodiments of the present disclosure, the clock driving circuit is further configured to output a third clock signal and a fourth clock signal, the first clock signal and the third clock signal being anti-phase signals; the charge pump further comprises a second-stage charge pump, the charge pump capacitor of the second-stage charge pump comprises a third capacitor and a fourth capacitor, and the first end of the third capacitor and the first end of the fourth capacitor are connected with a boost node of the second-stage charge pump; the second end of the third capacitor is used for receiving the third clock signal, and the second end of the fourth capacitor is used for receiving the fourth clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the fourth clock signal to be the direct current voltage so as to enable the charge pump capacitance of the second-stage charge pump to be the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the third clock signal and the fourth clock signal to be in-phase signals so that the charge pump capacitance of the second stage charge pump is the second capacitance value.

According to some exemplary embodiments of the present disclosure, the first stage charge pump includes a first NMOS transistor, a gate of the first NMOS transistor is connected to a drain of the first NMOS transistor and an input terminal of the first stage charge pump, respectively, and the input terminal of the first stage charge pump is connected to the power supply voltage; and the source electrode of the first NMOS tube is connected with the boost node of the first stage charge pump.

According to some exemplary embodiments of the present disclosure, the clock driving circuit is further configured to output a third clock signal and a fourth clock signal, the first clock signal and the third clock signal being anti-phase signals; the charge pump further comprises a second-stage charge pump, the charge pump capacitor of the second-stage charge pump comprises a third capacitor and a fourth capacitor, and the first end of the third capacitor and the first end of the fourth capacitor are connected with a boost node of the second-stage charge pump; the second end of the third capacitor is used for receiving the third clock signal, and the second end of the fourth capacitor is used for receiving the fourth clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the fourth clock signal to be the direct current voltage so as to enable the charge pump capacitance of the second-stage charge pump to be the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the third clock signal and the fourth clock signal to be in-phase signals so as to enable the charge pump capacitance of the second stage charge pump to be the second capacitance value; the second-stage charge pump further comprises a second NMOS tube, and the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube; and the source electrode of the second NMOS tube is connected with the boost node of the second-stage charge pump.

According to some exemplary embodiments of the present disclosure, the charge pump circuit further includes a clock driving circuit for outputting a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the first clock signal and the third clock signal being anti-phase signals; the charge pump comprises a first-stage charge pump, and the charge pump capacitor of the first-stage charge pump comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; the first end of the first capacitor and the first end of the second capacitor are connected with a first boost node of the first stage charge pump; the second end of the first capacitor is used for receiving the first clock signal, and the second end of the second capacitor is used for receiving the second clock signal; the first end of the third capacitor and the first end of the fourth capacitor are connected with a second boost node of the first-stage charge pump; the second end of the third capacitor is used for receiving the third clock signal, and the second end of the fourth capacitor is used for receiving the fourth clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the second clock signal and the fourth clock signal to be direct-current voltages so that the charge pump capacitance of the first-stage charge pump is the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the first clock signal and the second clock signal to be in-phase signals, and the third clock signal and the fourth clock signal to be in-phase signals, so that the charge pump capacitance of the first stage charge pump is the second capacitance value.

According to some exemplary embodiments of the present disclosure, the first stage charge pump includes a fourth NMOS transistor, a fifth NMOS transistor, a second PMOS transistor, and a third PMOS transistor; the input end of the first stage charge pump is used for receiving the power supply voltage; the fourth NMOS tube is arranged between the input end of the first-stage charge pump and the second boost node, the second PMOS tube is arranged between the second boost node and the output end of the first-stage charge pump, and the grid electrodes of the fourth NMOS tube and the second PMOS tube are connected with the first boost node; the fifth NMOS tube is arranged between the input end of the first stage charge pump and the first boost node, the third PMOS tube is arranged between the first boost node and the output end of the first stage charge pump, and the gates of the fifth NMOS tube and the third PMOS tube are connected with the second boost node.

According to some exemplary embodiments of the present disclosure, the first capacitance is equal to the third capacitance and the second capacitance is equal to the fourth capacitance.

According to some exemplary embodiments of the present disclosure, the dc voltage is equal to the power supply voltage.

According to some exemplary embodiments of the present disclosure, the charge pump circuit further includes a clock driving circuit for outputting a first clock signal; the charge pump comprises a first-stage charge pump, a charge pump capacitor of the first-stage charge pump comprises a first capacitor and a second capacitor, a first end of the first capacitor is connected with a first boost node of the first-stage charge pump, and a second end of the first capacitor is connected with a first end of the second capacitor; the first stage charge pump further comprises a first switch; the second capacitor is connected with the first switch in parallel, when the comparison voltage is the first voltage value, the first switch is controlled to be disconnected through the comparison voltage, the first capacitor is connected with the second capacitor in series, and the second end of the second capacitor is used for receiving the first clock signal so as to enable the charge pump capacitor of the first-stage charge pump to be the first capacitance value; when the comparison voltage is the second voltage value, the first switch is controlled to be conducted through the comparison voltage, and the second end of the first capacitor is used for receiving the first clock signal so that the charge pump capacitor of the first stage charge pump is the second capacitance value.

According to some exemplary embodiments of the present disclosure, the clock driving circuit is further configured to output a third clock signal, the first clock signal and the third clock signal being anti-phase signals; the charge pump capacitor of the first-stage charge pump further comprises a third capacitor and a fourth capacitor, a first end of the third capacitor is connected with the second boost node of the first-stage charge pump, and a second end of the third capacitor is connected with the first end of the fourth capacitor; the first stage charge pump further comprises a second switch; the first end of the third capacitor is connected with the second end of the fourth capacitor; the fourth capacitor is connected with the second switch in parallel, when the comparison voltage is the first voltage value, the second switch is controlled to be disconnected through the comparison voltage, the third capacitor is connected with the fourth capacitor in series, and the second end of the fourth capacitor is used for receiving the third clock signal so that the charge pump capacitor of the first-stage charge pump is the first capacitance value; and when the comparison voltage is the second voltage value, the second switch is controlled to be conducted through the comparison voltage, and the second end of the third capacitor is used for receiving the third clock signal so as to enable the charge pump capacitor of the first stage charge pump to be the second capacitance value.

According to yet another aspect of the present disclosure, there is provided a memory comprising a charge pump circuit as described in any one of the embodiments above.

According to another aspect of the present disclosure, there is provided an electronic device comprising a memory as described in the above embodiments.

According to the charge pump circuit, the memory and the electronic equipment provided by some embodiments of the present disclosure, a charge pump capacitance adjusting circuit is arranged in the charge pump circuit, the charge pump capacitance adjusting circuit is used to detect a power supply voltage of the charge pump circuit, and when the power supply voltage is detected to be greater than or equal to a voltage threshold, that is, when the power supply voltage is high voltage, the charge pump capacitance in each stage of charge pump in the charge pump circuit is adjusted to be a first capacitance value; when the power supply voltage is detected to be larger than or equal to a voltage threshold, namely the power supply voltage is low voltage, the charge pump capacitor in each stage of charge pump in the charge pump circuit is regulated to be a second capacitance value, and the first capacitance value is smaller than the second capacitance value, namely the size of the charge pump capacitor can be dynamically regulated according to the power supply voltage of the charge pump circuit through the charge pump capacitor regulating circuit, the output voltage ripple of the charge pump circuit is reduced through reducing the charge pump capacitor when the power supply voltage is high, and meanwhile, the current capacity of the charge pump circuit is ensured under the low power supply voltage through increasing the charge pump capacitor when the power supply voltage is low, so that the output voltage ripple of the charge pump under the high voltage is reduced while the current capacity of the charge pump under the low voltage is not reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 shows a schematic diagram of a charge pump circuit in an embodiment of the present disclosure.

Fig. 2 shows a schematic diagram of a supply voltage detection circuit in a charge pump capacitance adjustment circuit in an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a clock driving circuit in an embodiment of the disclosure.

Fig. 4 shows a schematic diagram of a first stage charge pump in an embodiment of the present disclosure.

Fig. 5 shows a pump operation schematic of the first stage charge pump of fig. 4 at a low supply voltage.

Fig. 6 shows a pump operation schematic of the first stage charge pump of fig. 4 at a high supply voltage.

Fig. 7 shows a schematic diagram of another first stage charge pump in an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of another charge pump circuit in an embodiment of the disclosure.

Fig. 9 shows a schematic diagram of yet another charge pump circuit in an embodiment of the disclosure.

Fig. 10 shows a schematic diagram of a memory in an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, apparatus, steps, etc. In other instances, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise. The symbol "/" generally indicates that the context-dependent object is an "or" relationship.

In the present disclosure, unless explicitly specified and limited otherwise, terms such as "connected" and the like are to be construed broadly and, for example, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In the related art, the charge pump capacitor in the charge pump is kept consistent under different power supply voltages, so that when the power supply voltage is relatively high, the output voltage ripple of the charge pump circuit is relatively large. One way to solve this technical problem provided in the related art is: the output voltage ripple of the charge pump is reduced by increasing the output load capacitance of the charge pump, but this increases not only the area, but also the settling time of the output voltage at low voltage. The charge pump circuit provided by the embodiment of the disclosure keeps the charge pump capacitance unchanged or increased when the power supply voltage is low by reducing the charge pump capacitance under the high power supply voltage, so that the current capability of the charge pump circuit under the low power supply voltage can be ensured, and the output voltage ripple of the charge pump circuit is reduced under the high power supply voltage.

Fig. 1 shows a schematic diagram of a charge pump circuit in an embodiment of the present disclosure.

As shown in fig. 1, a charge pump circuit 100 provided by embodiments of the present disclosure may include a charge pump 110 and a charge pump capacitance adjustment circuit 120.

The charge pump 110 may include n stages of charge pumps sequentially cascaded (which may be serial or parallel, and the embodiment of fig. 1 is illustrated in serial, but the disclosure is not limited thereto), for example, charge pump 1 (first stage charge pump), charge pump 2 (second stage charge pump), … up to charge pump n (nth stage charge pump), where n is a positive integer greater than or equal to 1, which are sequentially cascaded. The input terminal of the charge pump 1 is used for receiving the input voltage VIN of the charge pump circuit 100, and the output terminal of the charge pump n is used for outputting the output voltage VOUT of the charge pump circuit 100.

A respective charge pump capacitor may be included in each stage of charge pump, for example, charge pump 1 including charge pump capacitor 11, charge pump 2 including charge pump capacitor 12, and charge pump n including charge pump capacitor 1n. The charge pump capacitor in the embodiment of the disclosure may also be referred to as boost capacitor or boost capacitor, and has a boost function.

The charge pump capacitance adjustment circuit 120 may be configured to detect a supply voltage VCC of the charge pump circuit 100, and adjust a charge pump capacitance in each stage of charge pumps in the charge pump 110 to a first capacitance value when the supply voltage VCC of the charge pump circuit 100 is detected to be greater than or equal to a voltage threshold; when it is detected that the power supply voltage VCC of the charge pump circuit 100 is less than the voltage threshold, the charge pump capacitance in each stage of charge pumps in the charge pump 110 is adjusted to a second capacitance value.

The first capacitance value may be smaller than the second capacitance value.

In the embodiment of the present disclosure, the voltage threshold VDDX may be designed according to actual needs, that is, the power supply voltage is relatively high and low, which is determined according to an actual application scenario, and the present disclosure is not limited thereto.

According to the charge pump circuit provided by the embodiment of the disclosure, the charge pump capacitance adjusting circuit is arranged in the charge pump circuit, the power supply voltage of the charge pump circuit is detected by the charge pump capacitance adjusting circuit, and when the power supply voltage is detected to be greater than or equal to a voltage threshold, namely, the power supply voltage is high voltage, the charge pump capacitance in each stage of charge pump in the charge pump circuit is adjusted to be a first capacitance value; when the power supply voltage is detected to be larger than or equal to a voltage threshold, namely the power supply voltage is low voltage, the charge pump capacitor in each stage of charge pump in the charge pump circuit is regulated to be a second capacitance value, and the first capacitance value is smaller than the second capacitance value, namely the size of the charge pump capacitor can be dynamically regulated according to the power supply voltage of the charge pump circuit through the charge pump capacitor regulating circuit, the output voltage ripple of the charge pump circuit is reduced through reducing the charge pump capacitor when the power supply voltage is high, and meanwhile, the current capacity of the charge pump circuit is ensured under the low power supply voltage through increasing the charge pump capacitor when the power supply voltage is low, so that the output voltage ripple of the charge pump under the high voltage is reduced while the current capacity of the charge pump under the low voltage is not reduced.

Fig. 2 shows a schematic diagram of a supply voltage detection circuit in a charge pump capacitance adjustment circuit in an embodiment of the present disclosure.

As shown in fig. 2, the charge pump capacitance adjustment circuit 120 provided in the embodiment of the present disclosure may further include a power supply voltage detection circuit 121, and the power supply voltage detection circuit 121 may include a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a comparator COMP.

A first end of the first voltage dividing resistor R1 may be connected to the power supply voltage VCC, a second end of the first voltage dividing resistor R1 may be connected to a first end of the second voltage dividing resistor R2 and a second input end (indicated by "-" in fig. 2) of the comparator COMP, and a second end of the second voltage dividing resistor R2 may be grounded, so that the second input end of the comparator COMP may be used to receive the divided voltage of the power supply voltage VCC

A first input terminal (indicated by "+" in fig. 2) of the comparator COMP may be used to receive the reference voltage VREF, and an output terminal of the comparator COMP may be used to output the comparison voltage cmp_out when the voltage is dividedWhen the voltage is greater than or equal to the reference voltage VREF, the output comparison voltage CMP_OUT is a first voltage value, and the power supply voltage VCC is judged to be greater than or equal to the voltage threshold value, namely the power supply voltage VCC is high; when dividing voltage- >When the comparison voltage cmp_out is smaller than the reference voltage VREF, the output comparison voltage cmp_out is a second voltage value, and it is determined that the power supply voltage VCC is smaller than the voltage threshold, that is, the power supply voltage VCC is lower.

In the following embodiment, the first voltage value is taken as a low level, and is denoted by "0"; the second voltage value is high, and is illustrated by a "1" representation, but the disclosure is not limited thereto.

It should be understood that the power supply voltage detection circuit provided in the embodiment of fig. 3 is only used for illustration, and the circuit structure of the power supply voltage detection circuit is not limited in the embodiment of the disclosure, as long as it can detect whether the power supply voltage of the charge pump circuit is greater than the voltage threshold, for example, the first voltage dividing resistor R1 is not limited to one resistor, and may be a plurality of (two or more) resistors connected in series, parallel, or a combination of series and parallel. For another example, the second voltage dividing resistor R2 is not limited to one resistor, and may be a series connection, a parallel connection, or a combination of series and parallel connection of a plurality of (two or more) resistors.

In an exemplary embodiment, the charge pump circuit may further include a clock driving circuit, which may be used to output the first clock signal and the second clock signal.

In an exemplary embodiment, the clock driving circuit may further be configured to output a third clock signal and a fourth clock signal, and the first clock signal and the third clock signal may be opposite phase signals. For example, at the same time, if the first clock signal is high level "1", the third clock signal is low level "0"; if the first clock signal is low level "0", the third clock signal is high level "1".

In an exemplary embodiment, the clock driving circuit may include: a first inverter, an input of which may be used to receive an initial clock signal; the input end of the time delay unit can be connected with the output end of the first phase inverter; the input end of the second inverter can be connected with the output end of the time delay unit; the input end of the third inverter can be connected with the output end of the second inverter, and the output end of the third inverter is used for outputting the first clock signal; and a first input end of the first NAND gate can be connected with the output end of the second inverter, a second input end of the first NAND gate can be used for receiving the comparison voltage, and an output end of the first NAND gate can be used for outputting the second clock signal.

The clock driving circuit provided in the embodiment of the present disclosure is exemplified by the embodiment of fig. 3, but the present disclosure is not limited to the specific circuit configuration of the clock driving circuit, and any clock driving circuit capable of providing a signal satisfying the requirement may be used in the charge pump circuit of the embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a clock driving circuit in an embodiment of the disclosure.

As shown in fig. 3, the charge pump circuit provided in the embodiment of the present disclosure may further include a clock driving circuit 300, and the clock driving circuit 300 may include a first inverter 301, a delay unit 310, a second inverter 302, a third inverter 303, a first nand gate 304, a fourth inverter 305, a fifth inverter 306, a sixth inverter 307, and a second nand gate 308.

An input of the first inverter 301 may be configured to receive the initial clock signal CLK, and an output of the first inverter 301 may be connected to an input of the delay unit 310 and an input of the fourth inverter 305, respectively.

An output of the delay unit 310 may be used to connect to an input of the second inverter 302.

The output of the second inverter 302 may be used to connect the input of the third inverter 303 and the first input of the first nand gate 304, respectively.

An output terminal of the third inverter 303 may be used to output the first clock signal CLK1.

The second input terminal of the first nand gate 304 may be used for receiving the comparison voltage cmp_out, the output terminal of the first nand gate 304 may be used for outputting the second clock signal CLK2, when the divided voltage is greater than or equal to the reference voltage VREF, the output comparison voltage cmp_out is a first voltage value "0", that is, when the power supply voltage VCC is greater than or equal to the voltage threshold, the output CLK2 is a direct current voltage; when the divided voltage is smaller than the reference voltage VREF, the output comparison voltage cmp_out is a second voltage value "1", that is, when the power supply voltage VCC is smaller than the voltage threshold, the output CLK2 is a second clock signal whose high and low levels are periodically changed.

With continued reference to fig. 3, the delay unit 310 may include a third NMOS transistor N1 and a first PMOS transistor P1.

The gate of the third NMOS transistor N1 may be configured to receive the power supply voltage VCC, the drain of the third NMOS transistor N1 may be respectively connected to the output end of the first inverter 301 and the drain of the first PMOS transistor P1, and the source of the third NMOS transistor N1 may be respectively connected to the input end of the second inverter 302 and the source of the first PMOS transistor.

The gate of the first PMOS transistor P1 may be configured to receive the negative supply voltage VSS, the drain of the first PMOS transistor P1 may be connected to the output terminal of the first inverter 301 and the drain of the third NMOS transistor N1, and the source of the first PMOS transistor P1 may be connected to the input terminal of the second inverter 302 and the source of the third NMOS transistor N1, respectively.

The delay unit in the embodiment of fig. 3 is illustrated as a transmission gate including the third NMOS transistor N1 and the first PMOS transistor P1, but the disclosure is not limited thereto, and any delay circuit capable of realizing the matching of the delays of the different clock signals of the output may be applied to the embodiment of the disclosure.

An input terminal of the fourth inverter 305 may be connected to an output terminal of the first inverter 301, and an output terminal of the fourth inverter 305 may be connected to an input terminal of the fifth inverter 306.

An input terminal of the fifth inverter 306 may be connected to an output terminal of the fourth inverter 305, and an output terminal of the fifth inverter 306 may be connected to an input terminal of the sixth inverter 307 and a first input terminal of the second nand gate 308, respectively.

An output terminal of the sixth inverter 307 may be used to output the third clock signal CLK3.

A second input terminal of the second nand gate 308 may be used for receiving the comparison voltage cmp_out, and an output terminal of the second nand gate 308 may be used for outputting the fourth clock signal CLK4, and when the divided voltage is greater than the reference voltage VREF, the output comparison voltage cmp_out is a first voltage value "0", that is, when the power voltage VCC is greater than or equal to the voltage threshold value, the output CLK4 is a direct current voltage, and in the following embodiments, the direct current voltage is taken as the power voltage VCC for illustration, but the disclosure is not limited thereto; when the divided voltage is less than or equal to the reference voltage VREF, the output comparison voltage cmp_out is a second voltage value "1" (may be the voltage value VCC of the power supply voltage), that is, when the power supply voltage VCC is less than the voltage threshold, the output CLK4 is a fourth clock signal whose high and low levels are periodically changed.

The above-described clock driving circuit of the embodiment of the present disclosure is a non-overlapping (non-overlapping) clock circuit capable of generating a pair of non-overlapping clocks CLK1 and CLK3 by receiving an initial clock signal CLK generated by an oscillator, that is, the first clock signal CLK1 and the third clock signal CLK3 are a pair of complementary clocks, which may also be referred to as anti-phase signals, for example, when the first clock signal CLK1 is at a high level such as a voltage value VCC, and the third clock signal CLK3 is at a low level such as 0.

In an exemplary embodiment, the charge pump may include a first stage charge pump, and the charge pump capacitance of the first stage charge pump may include a first capacitance, a second capacitance, a third capacitance, and a fourth capacitance; the first end of the first capacitor and the first end of the second capacitor can be connected with a first boost node of the first stage charge pump; a second end of the first capacitor may be configured to receive the first clock signal and a second end of the second capacitor may be configured to receive the second clock signal; the first end of the third capacitor and the first end of the fourth capacitor can be connected with a second boost node of the first stage charge pump; a second end of the third capacitor may be configured to receive the third clock signal and a second end of the fourth capacitor may be configured to receive the fourth clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit can adjust the second clock signal and the fourth clock signal to be direct-current voltages so that the charge pump capacitance of the first stage charge pump is the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit can adjust the first clock signal and the second clock signal to be in-phase signals, and the third clock signal and the fourth clock signal to be in-phase signals, so that the charge pump capacitance of the first stage charge pump is the second capacitance value.

In an exemplary embodiment, the first stage charge pump may include a fourth NMOS transistor, a fifth NMOS transistor, a second PMOS transistor, and a third PMOS transistor; the input end of the first stage charge pump can be used for receiving the power supply voltage; the fourth NMOS tube can be arranged between the input end of the first stage charge pump and the second boost node, the second PMOS tube can be arranged between the second boost node and the output end of the first stage charge pump, and the grid electrodes of the fourth NMOS tube and the second PMOS tube can be connected with the first boost node; the fifth NMOS tube can be arranged between the input end of the first stage charge pump and the first boost node, the third PMOS tube can be arranged between the first boost node and the output end of the first stage charge pump, and the gates of the fifth NMOS tube and the third PMOS tube are connected with the second boost node.

The first stage charge pump in the charge pump circuit provided in the embodiment of the present disclosure is illustrated in the following with reference to fig. 4 to 6, but the present disclosure is not limited thereto.

Fig. 4 shows a schematic diagram of a first stage charge pump in an embodiment of the present disclosure.

As shown in fig. 4, the charge pump in the embodiment of the disclosure may include a first stage charge pump (charge pump 1), the input terminal of the charge pump 1 may be used to receive the input voltage VIN of the charge pump circuit, the input voltage VIN may be a power supply voltage VCC, the output terminal of the first stage charge pump may be used to output a first output voltage VOUT1, the first output voltage VOUT1 may be used as the input voltage of a second stage charge pump, the second output voltage VOUT2 (not shown in the drawing) output by the output terminal of the second stage charge pump may be used as the input voltage of a third stage charge pump, …, and so on, the output voltage output by the output terminal of the nth stage charge pump may be used as the output voltage VOUT of the charge pump circuit.

The charge pump capacitor 11 of the first stage charge pump may include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

The first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 may be connected to the first boost node V2 of the first stage charge pump.

A second terminal of the first capacitor C1 may be used to receive the first clock signal CLK1 and a second terminal of the second capacitor C2 may be used to receive the second clock signal CLK2.

The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 may be connected to the second boost node V1 of the first stage charge pump.

A second terminal of the third capacitor C3 may be used to receive the third clock signal CLK3 and a second terminal of the fourth capacitor C4 may be used to receive the fourth clock signal CLK4.

When the comparison voltage cmp_out is the first voltage value "0", the charge pump capacitance adjusting circuit can adjust the second clock signal CLK2 and the fourth clock signal CLK4 to be dc voltages, for example, refer to the embodiment of fig. 3. At this time, for the first boost node V2 side, the charge pump capacitance of the first stage charge pump is a first capacitance value C1; for the second boost node V1 side, the charge pump capacitance of the first stage charge pump is the first capacitance value C3.

When the comparison voltage cmp_out is "1", the charge pump capacitance adjusting circuit can adjust the first clock signal CLK1 and the second clock signal CLK2 to be in-phase signals, and the third clock signal CLK3 and the fourth clock signal CLK4 to be in-phase signals, for example, refer to the embodiment of fig. 3. At this time, for the first boost node V2 side, the charge pump capacitance of the first stage charge pump is a first capacitance value c1+c2; for the second boost node V1 side, the charge pump capacitance of the first stage charge pump is a second capacitance value c3+c4, so that the charge pump capacitance of the first stage charge pump satisfies that the first capacitance value is smaller than the second capacitance value.

Optionally, the first stage charge pump in the embodiment of fig. 4 may further include a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second PMOS transistor P2, and a third PMOS transistor P3.

The fourth NMOS transistor N4 may be disposed between the input terminal of the first stage charge pump and the second boost node V1, the second PMOS transistor P2 may be disposed between the second boost node V1 and the output terminal of the first stage charge pump, for example, a drain of the fourth NMOS transistor N4 may be connected to the input terminal of the first stage charge pump, a source of the fourth NMOS transistor N4 may be connected to the second boost node V1 of the first stage charge pump, a drain of the second PMOS transistor P2 may be connected to the second boost node V1, and a source of the second PMOS transistor P2 may be connected to the output terminal of the first stage charge pump.

The gate of the fourth NMOS transistor N4 and the gate of the second PMOS transistor P2 may both be connected to the first boost node V2.

The fifth NMOS transistor N5 may be disposed between the input terminal of the first stage charge pump and the first boost node V2, the third PMOS transistor P3 may be disposed between the first boost node V2 and the output terminal of the first stage charge pump, for example, a drain of the fifth NMOS transistor N5 may be connected to the input terminal of the first stage charge pump, a source of the fifth NMOS transistor N5 may be connected to the first boost node V2 of the first stage charge pump, a drain of the third PMOS transistor P3 may be connected to the first boost node V2, and a source of the third PMOS transistor P3 may be connected to the output terminal of the first stage charge pump.

The gate of the fifth NMOS transistor N5 and the gate of the third PMOS transistor P3 may both be connected to the second boost node V1.

For the embodiment of fig. 4, the charge pump circuit may further include a second stage charge pump, where the first output voltage VOUT1 of the first stage charge pump may be used as an input voltage of the second stage charge pump, the second output voltage VOUT2 (not shown) output by the output terminal of the second stage charge pump may be used as an input voltage of the third stage charge pump, …, and so on, and the output voltage output by the output terminal of the nth stage charge pump may be used as an output voltage VOUT of the charge pump circuit.

The circuit structure of the second stage charge pump may refer to the first stage charge pump provided in the embodiment of fig. 4, that is, the charge pump capacitor of the second stage charge pump may also include a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, and the second stage charge pump may also include a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second PMOS transistor P2 and a third PMOS transistor P3.

The second stage charge pump differs from the first stage charge pump in that: a second terminal of the first capacitor C1 may be used to receive the third clock signal CLK3 and a second terminal of the second capacitor C2 may be used to receive the fourth clock signal CLK4; a second terminal of the third capacitor C3 may be used to receive the first clock signal CLK1 and a second terminal of the fourth capacitor C4 may be used to receive the second clock signal CLK2. The upper clock signal and the lower clock signal of two adjacent stages of charge pumps in the charge pump circuit are opposite phase signals.

By the charge pump circuit provided by the embodiment, output voltage ripple when the power supply voltage is relatively high can be reduced.

In the embodiment of the disclosure, the input voltage VIN of the charge pump circuit has a voltage value of VCC, and the power supply of the comparator COMP and the power supply voltage of the clock driving circuit (CLK chain) are VCC.

Fig. 5 shows a pump operation schematic of the first stage charge pump of fig. 4 at a low supply voltage.

As shown in fig. 5, the comparator COMP is used to detect the input voltage VIN, where the input voltage vin=the power supply voltage VCC, and a voltage point is set as the voltage threshold VDDX, when the power supply voltage VCC is smaller than the voltage threshold VDDX, that is, when vin=vcc is smaller, a larger boost capacitor is required, where the comparison voltage cmp_out signal is a second voltage value "1", a second end of the second capacitor C2 is used to receive the second clock signal CLK2 periodically changing at a high level and a low level, and a second end of the fourth capacitor C4 is used to receive the fourth clock signal CLK4 periodically changing at a high level and a low level, while satisfying clk1=clk2, clk3=clk4, c1=c3, and c2=c4. That is, when the power supply voltage VCC is lower than the voltage threshold VDDX, the comparison voltages cmp_out=vcc, C1 and C2 are connected in parallel, that is, the first capacitance value is (c1+c2), C3 and C4 are connected in parallel, that is, the first capacitance value is (c3+c4), that is, the second capacitance C2, the fourth capacitance C4, the first capacitance C1 and the third capacitance C3 participate in operation together, contributing to the current capability, so as to ensure the current capability under low voltage.

As shown in fig. 5, when CLK3 is VCC and CLK1 is grounded GND, N5 is turned on, P3 is turned off, C1 and C2 are charged by VIN to VCC (neglecting the threshold loss of N5), C1 and C2 are connected in parallel, so the second capacitance value is (c1+c2), and the output charge amount is VCC (c1+c2). When CLK3 is GND and CLK1 is VCC, N5 is turned off and P3 is turned on, at this time, the voltages at the first ends of C1 and C2 are VCC, the voltages at the second ends of C1 and C2 are boost to 2VCC, the charge is shared to the output end of the first stage charge pump, the voltages at the output end of the first stage charge pump are boost to VOUT1, the voltages at the second ends of C1 and C2 are changed from 2VCC to VOUT1 after stabilization, the voltage difference between the ends of C1 and C2 is VOUT1-VCC, and the change in the charge amount VCC (c1+c2) - (VOUT-VCC) ×1+c2).

When CLK1 is VCC and CLK3 is grounded GND, N4 is on, P2 is off, C3 and C4 are charged by VIN to VCC (ignoring the threshold loss of N4), C3 and C4 are connected in parallel, so the second capacitance value is (c3+c4), and the output charge amount is VCC (c3+c4). When CLK1 is GN D and CLK3 is VCC, N4 is turned off and P2 is turned on, at this time, voltages at the first ends of C3 and C4 are VCC, voltages at the second ends of C3 and C4 are boost to 2VCC, charge is shared to the output end of the first stage charge pump, so that voltages at the output end of the first stage charge pump are boost to VOUT1, voltages at the second ends of C3 and C4 are changed from 2VCC to VOUT1 after stabilization, voltage differences at the two ends of C3 and C4 are VOUT1-VCC, and change VCC (c3+c4) - (VOUT-VCC) × (c3+c4) of charge amount.

Fig. 6 shows a pump operation schematic of the first stage charge pump of fig. 4 at a high supply voltage.

In the embodiment of fig. 6, the dc voltage is taken as the power voltage VCC for illustration, but the disclosure is not limited thereto, as long as the voltage values received by the second terminal of the second capacitor and the second terminal of the fourth capacitor are dc voltages when the power voltage VCC is greater than or equal to the voltage threshold VDDX.

When the comparator detects that the supply voltage VCC is greater than or equal to the voltage threshold VDDX, the comparison voltage cmp_out signal is "0", and a high supply voltage VCC brings about a large charge pump current capability, at which time the charge pump capacitance needs to be reduced, so that the current capability of the charge pump is reduced.

In the embodiment of fig. 6, the second clock signal CLK2 and the fourth clock signal CLK4 stop at the voltage value VCC when the comparison voltage cmp_out=0, and the second capacitor C2 and the fourth capacitor C4 do not participate in contributing to the current capability, so as to reduce the current capability of the charge pump, and at the same time reduce the ripple of the output voltage.

The second capacitor C2 and the fourth capacitor C4 correspond to a parasitic capacitor when the second clock signal CLK2 and the fourth clock signal CLK4 are maintained at the voltage value VCC, and the first capacitor value is C1 and the output charge amount is q1=vcc×c1- (VOUT-VCC) ×c1+c2 for the V2 side. In the embodiment of fig. 5, the second clock signal CLK2 and the fourth clock signal CLK4 are not fixed to have the voltage value VCC, when CLK1 is VCC, CLK3 is grounded GND, N4 is turned on, P2 is turned off, C3 and C4 are charged to VCC by VIN (neglecting the threshold loss of N4), and the output charge amount is q2=vcc (c1+c2) - (VOUT-VCC) × (c1+c2). That is, Q1< Q2 is equal to the voltage VCC, but the relative value of Q1 is increased when the power supply voltage VCC is relatively high. The amount of output charge determines the current capability of the charge pump and decreases, i.e., reduces the output voltage ripple of the charge pump circuit.

As shown in fig. 6, when vin=vcc is large, a small boost capacitance is required, and CLK2 and CLK4 are fixed to VCC. When CLK3 is VCC and CLK1 is GND, N5 is turned on, P3 is turned off, the first terminal of C1 is charged to VCC by VIN, the second terminal of C1 is GND, i.e., one terminal of C1 is VCC, both terminals of C2 are VCC, and the charge on C1 is vcc×c1. When CLK3 is GND and CLK1 is VCC, N5 is turned off and P3 is turned on, at this time, the voltages at the second ends of C1 and C2 are VCC, the voltages at the first ends of C1 and C2 are boost to 2VCC, the charge is shared to the output end of the first stage charge pump, the voltages at the output end of the first stage charge pump are boost to VOUT1, the voltages at the first ends of C1 and C2 are changed from 2VCC to VOUT1 after stabilization, the voltage difference between the ends of C1 and C2 is VOUT1-VCC, and the change of the charge amount is vcc×c1- (VOUT-VCC) (c1+c2).

When vin=vcc is large, small boost capacitances are required, CLK2 and CLK4 being fixed to VCC. When CLK1 is VCC and CLK3 is GND, N4 is turned on, P2 is turned off, the first terminal of C3 is charged to VCC by VIN, the second terminal of C3 is GND, i.e., one terminal of C3 is VCC, both terminals of C4 are VCC, and the charge on C3 is vcc×c3. When CLK1 is GND and CLK3 is VCC, N4 is turned off and P2 is turned on, at this time, the voltages at the second ends of C3 and C4 are VCC, the voltages at the first ends of C3 and C4 are boost to 2VCC, the charge is shared to the output end of the first stage charge pump, the voltage at the output end of the first stage charge pump is boost to VOUT1, the voltage at the first ends of C3 and C4 is changed from 2VCC to VOUT1 after stabilization, the voltage difference across C3 and C4 is VOUT1-VCC, and the change of the charge amount is vcc×c3- (VOUT-VCC) (c3+c4).

In an exemplary embodiment, the charge pump circuit may further include a clock driving circuit, which may be used to output the first clock signal; the charge pump may include a first stage charge pump, a charge pump capacitor of the first stage charge pump may include a first capacitor and a second capacitor, a first end of the first capacitor may be connected to a first boost node of the first stage charge pump, and a second end of the first capacitor may be connected to a first end of the second capacitor; the first stage charge pump may further include a first switch; the second capacitor can be connected with the first switch in parallel, when the comparison voltage is the first voltage value, the first switch can be controlled to be disconnected through the comparison voltage, the first capacitor is connected with the second capacitor in series, and the second end of the second capacitor is used for receiving the first clock signal so that the charge pump capacitor of the first stage charge pump is the first capacitance value; when the comparison voltage is the second voltage value, the first switch can be controlled to be turned on through the comparison voltage, and the second end of the first capacitor can be used for receiving the first clock signal so as to enable the charge pump capacitor of the first stage charge pump to be the second capacitance value.

In an exemplary embodiment, the clock driving circuit may be further configured to output a third clock signal, where the first clock signal and the third clock signal are anti-phase signals; the charge pump capacitor of the first stage charge pump may further include a third capacitor and a fourth capacitor, a first end of the third capacitor may be connected to the second boost node of the first stage charge pump, and a second end of the third capacitor may be connected to the first end of the fourth capacitor; the first stage charge pump may further include a second switch; the first end of the third capacitor can be connected with the second end of the fourth capacitor; the fourth capacitor may be connected in parallel with the second switch, and when the comparison voltage is the first voltage value, the second switch may be controlled to be turned off by the comparison voltage, the third capacitor is connected in series with the fourth capacitor, and the second end of the fourth capacitor may be used to receive the third clock signal, so that the charge pump capacitor of the first stage charge pump is the first capacitance value; when the comparison voltage is the second voltage value, the second switch can be controlled to be turned on through the comparison voltage, and the second end of the third capacitor can be used for receiving the third clock signal so as to enable the charge pump capacitor of the first stage charge pump to be the second capacitance value.

The charge pump circuit provided in the embodiment of the present disclosure is illustrated in the following with reference to fig. 7, but the present disclosure is not limited thereto. For the embodiment of fig. 7, the clock driving circuit may only need the circuit portions for the first clock signal CLK1 and the third clock signal CLK 3.

Fig. 7 shows a schematic diagram of another first stage charge pump in an embodiment of the present disclosure.

As shown in fig. 7, the charge pump in the embodiment of the disclosure may include a first stage charge pump, an input terminal of which may be used to receive an input voltage VIN of the charge pump circuit, the input voltage VIN may be a power supply voltage VCC, and an output terminal of which may be used to output a first output voltage VOUT1.

The charge pump capacitors of the first stage charge pump may include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

A first terminal of the first capacitor C1 may be connected to the first boost node V2 of the first stage charge pump, and a second terminal of the first capacitor C1 may be connected to a first terminal of the second capacitor C2.

The first stage charge pump may further include a first switch K1, where the first switch K1 is connected in parallel with the second capacitor C2, i.e. a first end of the first switch K1 may be used to connect a first end of the second capacitor C2 and a second end of the first capacitor C1, and a second end of the first switch K1 may be used to connect a second end of the second capacitor C2.

When the comparison voltage cmp_out is "0", the first switch K1 is controlled to be turned off by the comparison voltage cmp_out, the first capacitor C1 is connected in series with the second capacitor C2, and the second end of the second capacitor C2 is used for receiving the first clock signal CLK1, so that the charge pump capacitor of the first stage charge pump is at the first capacitance value on the side of the first boost node V2When the comparison voltage cmp_out is at the second voltage value "1", the first switch K1 is controlled to be turned on by the comparison voltage cmp_out, and the second terminal of the first capacitor C1 is used for receiving the first clock signal CLK1, so that the charge pump of the first stage charge pump is located on the side of the first boost node V2The capacitor is a second capacitance C1, i.e. the first capacitance of the first stage charge pump is satisfied>Less than the second capacitance C1.

A first terminal of the third capacitor C3 may be connected to the second boost node V1 of the first stage charge pump, and a second terminal of the third capacitor C3 may be connected to a first terminal of the fourth capacitor C4.

The first stage charge pump may further include a second switch K2, where the second switch K2 is connected in parallel with the fourth capacitor C4, i.e. a first end of the second switch K2 is connected to a first end of the fourth capacitor C4 and a second end of the third capacitor C3, and a second end of the second switch K2 may be connected to a second end of the fourth capacitor C4.

When the comparison voltage cmp_out is the first voltage value "0", the comparison voltage cmp_out controls the second switch K2 to be turned off, and the third capacitor C3 is connected in series with the fourth capacitor C4, and the second end of the fourth capacitor C4 is used for receiving the third clock signal CLK3, so that the charge pump capacitor of the first stage charge pump is the first capacitance value at the side of the second boost node V1When the comparison voltage cmp_out is the second voltage value "1", the second switch K2 is controlled to be turned on by the comparison voltage cmp_out, and the second end of the third capacitor C3 is used for receiving the third clock signal CLK3, so that the charge pump capacitor of the first stage charge pump is the second capacitance C3 on the side of the second boost node V1, i.e. the first capacitance +.f. of the first stage charge pump is satisfied>Less than the second capacitance C3.

The first stage charge pump in the embodiment of fig. 7 may further include a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second PMOS transistor P2, and a third PMOS transistor P3, and the specific connection relationship may refer to the embodiment of fig. 4.

For the embodiment of fig. 7, the charge pump circuit may further include a second stage charge pump, where the first output voltage VOUT1 of the first stage charge pump may be used as an input voltage of the second stage charge pump, the second output voltage VOUT2 (not shown) output by the output terminal of the second stage charge pump may be used as an input voltage of the third stage charge pump, …, and so on, and the output voltage output by the output terminal of the nth stage charge pump may be used as an output voltage VOUT of the charge pump circuit.

The circuit structure of the second stage charge pump may refer to the first stage charge pump provided in the embodiment of fig. 7, that is, the charge pump capacitor of the second stage charge pump may also include a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, and the second stage charge pump may also include a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second PMOS transistor P2 and a third PMOS transistor P3.

The second stage charge pump differs from the first stage charge pump in that: when the comparison voltage cmp_out is "0", the first switch K1 and the second switch K2 are controlled to be turned off by the comparison voltage cmp_out, the first capacitor C1 is connected in series with the second capacitor C2, the third capacitor C3 is connected in series with the fourth capacitor C4, the second end of the second capacitor C2 is used for receiving the third clock signal CLK3, the second end of the fourth capacitor C4 is used for receiving the first clock signal CLK1, so that the charge pump capacitor of the second stage charge pump is at the first capacitor value on the side of the first boost node V2On the side of the second boost node V1, the charge pump capacitance of the second stage charge pump is a first capacitance value +.>When the comparison voltage cmp_out is the second voltage value "1", the first switch K1 and the second switch K2 are controlled to be turned on by the comparison voltage cmp_out, and at this time, the second end of the first capacitor C1 is used for receiving the third clock signal CLK3, and the second end of the third capacitor C3 is used for receiving the first clock signal CLK1, so that the charge pump capacitor of the second stage charge pump is the second capacitance value C1 at the side of the first boost node V2, and the charge pump capacitor of the second stage charge pump is the second capacitance value C1 at the side of the second boost node V1 The charge pump capacitor is a second capacitance value C3, namely the first capacitance value of the second stage charge pump is smaller than the second capacitance value. The upper clock signal and the lower clock signal of two adjacent stages of charge pumps in the charge pump circuit are opposite phase signals.

In an exemplary embodiment, the charge pump circuit may further include a clock driving circuit, which may be used to output the first clock signal and the second clock signal; the charge pump may include a first stage charge pump, a charge pump capacitor of the first stage charge pump may include a first capacitor and a second capacitor, and a first end of the first capacitor and a first end of the second capacitor may be connected to a boost node of the first stage charge pump; a second end of the first capacitor may be configured to receive the first clock signal and a second end of the second capacitor may be configured to receive the second clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit can adjust the second clock signal to be a direct current voltage so as to enable the charge pump capacitance of the first stage charge pump to be the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit can adjust the first clock signal and the second clock signal to be in-phase signals so as to enable the charge pump capacitance of the first stage charge pump to be the second capacitance value.

In an exemplary embodiment, the clock driving circuit may further be configured to output a third clock signal and a fourth clock signal, and the first clock signal and the third clock signal may be anti-phase signals; the charge pump may further include a second stage charge pump, the charge pump capacitor of the second stage charge pump may include a third capacitor and a fourth capacitor, and the first end of the third capacitor and the first end of the fourth capacitor may be connected to a boost node of the second stage charge pump; a second end of the third capacitor may be configured to receive the third clock signal and a second end of the fourth capacitor may be configured to receive the fourth clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit can adjust the fourth clock signal to be the direct current voltage so as to enable the charge pump capacitance of the second-stage charge pump to be the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit can adjust the third clock signal and the fourth clock signal to be in-phase signals so that the charge pump capacitance of the second stage charge pump is the second capacitance value.

In an exemplary embodiment, the first stage charge pump may include a first NMOS transistor, a gate of the first NMOS transistor being connected to a drain of the first NMOS transistor and an input terminal of the first stage charge pump, respectively, the input terminal of the first stage charge pump being connected to the power supply voltage; and the source electrode of the first NMOS tube can be connected with the boost node of the first stage charge pump.

In an exemplary embodiment, the clock driving circuit may be further configured to output a third clock signal and a fourth clock signal, where the first clock signal and the third clock signal are anti-phase signals; the charge pump may further include a second stage charge pump, the charge pump capacitor of the second stage charge pump may include a third capacitor and a fourth capacitor, and the first end of the third capacitor and the first end of the fourth capacitor may be connected to a boost node of the second stage charge pump; a second end of the third capacitor may be configured to receive the third clock signal and a second end of the fourth capacitor may be configured to receive the fourth clock signal; when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit can adjust the fourth clock signal to be the direct current voltage so that the charge pump capacitance of the second stage charge pump can be the first capacitance value; when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit can adjust the third clock signal and the fourth clock signal to be in-phase signals so as to enable the charge pump capacitance of the second stage charge pump to be the second capacitance value; the second-stage charge pump can further comprise a second NMOS tube, and the grid electrode of the second NMOS tube can be connected with the drain electrode of the second NMOS tube; and the source electrode of the second NMOS tube can be connected with the boost node of the second-stage charge pump.

The charge pump circuit provided in the embodiment of the present disclosure is illustrated in the following with reference to fig. 8, but the present disclosure is not limited thereto.

Fig. 8 shows a schematic diagram of another charge pump circuit in an embodiment of the disclosure.

As shown in fig. 8, it is assumed that the charge pump circuit includes N stages of charge pumps, where N is a positive integer greater than or equal to 1. Optionally, the boost node V of the nth stage charge pump is connected to the drain and the gate of the output NMOS MO, and the source of the output NMOS MO is used for outputting the output voltage VOUT of the charge pump circuit.

Each stage of charge pump includes a respective charge pump capacitance, and the charge pump capacitance of the first stage of charge pump may include a first capacitance C1 and a second capacitance C2.

The first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 may each be connected to the boost node V of the first stage charge pump.

A second terminal of the first capacitor C1 may be used to receive the first clock signal CLK1 and a second terminal of the second capacitor C2 may be used to receive the second clock signal CLK2.

When the comparison voltage cmp_out is the first voltage value "0", the charge pump capacitance adjusting circuit can adjust the second clock signal CLK2 to be a dc voltage, such as the power voltage VCC, so that the charge pump capacitance of the first stage charge pump is the first capacitance value C1.

When the comparison voltage cmp_out is a second voltage value "1", the charge pump capacitance adjusting circuit can adjust the first clock signal CLK1 and the second clock signal CLK2 to be in-phase signals, so that the charge pump capacitance of the first stage charge pump is a second capacitance value c1+c2, and the first capacitance value of the first stage charge pump is smaller than the second capacitance value.

With continued reference to fig. 8, the first stage charge pump may include a first NMOS transistor M1, both the drain and gate of the first NMOS transistor M1 may be connected to the power supply voltage VCC, and the source of the first NMOS transistor M1 may be connected to the boost node V of the first stage charge pump.

Optionally, the charge pump shown in fig. 8 may further include a second stage charge pump, an input terminal of the second stage charge pump is connected to the boost node V of the first stage charge pump, and a charge pump capacitor of the second stage charge pump may include a third capacitor C3 and a fourth capacitor C4.

The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 may each be connected to the boost node V of the second stage charge pump.

A second terminal of the third capacitor C3 may be used to receive the third clock signal CLK3 and a second terminal of the fourth capacitor C4 may be used to receive the fourth clock signal CLK4. Since the first clock signal CLK1 and the third clock signal CLK3 are opposite phase signals, the charge pump circuit of the embodiment of fig. 8 also satisfies that the clock signals of the adjacent two stages of charge pumps are opposite phase signals.

When the comparison voltage cmp_out is the first voltage value "0", the charge pump capacitance adjusting circuit can adjust the fourth clock signal CLK4 to be a dc voltage, such as the power voltage VCC, so that the charge pump capacitance of the second stage charge pump is the first capacitance value C3.

When the comparison voltage cmp_out is the second voltage value "1", the charge pump capacitance adjusting circuit can adjust the third clock signal CLK3 and the fourth clock signal CLK4 to be in-phase signals, so that the charge pump capacitance of the second stage charge pump is the second capacitance value c3+c4, and the first capacitance value of the second stage charge pump is smaller than the second capacitance value.

With continued reference to fig. 8, the first stage charge pump may include a first NMOS transistor M1, both the drain and gate of the first NMOS transistor M1 may be connected to the power supply voltage VCC, and the source of the first NMOS transistor M1 may be connected to the boost node V of the first stage charge pump.

Optionally, the charge pump shown in fig. 8 may further include a third stage charge pump, and a charge pump capacitor of the third stage charge pump may include a first capacitor C5 and a second capacitor C6. The input terminal of the third stage charge pump may be connected to the boost node V of the second stage charge pump, the third stage charge pump may include an NMOS transistor M3, and the third stage charge pump may refer to the first stage charge pump, that is, the charge pump circuit provided in the embodiment of fig. 8, and the circuit structure of the odd stage charge pump is similar.

Optionally, the charge pump shown in fig. 8 may further include a fourth stage charge pump, and the charge pump capacitor of the fourth stage charge pump may include a third capacitor C7 and a fourth capacitor C8. The input terminal of the fourth stage charge pump may be connected to the boost node V of the third stage charge pump, the fourth stage charge pump may include an NMOS transistor M4, and the fourth stage charge pump may refer to the second stage charge pump described above, that is, the charge pump circuit provided in the embodiment of fig. 8, and the circuit structure of the even stage charge pump is similar.

Similarly, the charge pump shown in fig. 8 may further include an nth stage charge pump, and the charge pump capacitor of the nth stage charge pump may include a third capacitor C2N-1 and a fourth capacitor C2N, which may be referred to as the second stage charge pump.

The charge pump circuit provided in the embodiment of the present disclosure is illustrated in the following with reference to fig. 9, but the present disclosure is not limited thereto. For the embodiment of fig. 9, the clock driving circuit may only need the circuit portions for the first clock signal CLK1 and the third clock signal CLK 3.

Fig. 9 shows a schematic diagram of yet another charge pump circuit in an embodiment of the disclosure.

As shown in fig. 9, the charge pump in the embodiments of the present disclosure may include a first stage charge pump, an input terminal of which may be used to receive an input voltage VIN of the charge pump circuit, which may be a supply voltage VCC.

The charge pump capacitance of the first stage charge pump may include a first capacitance C1 and a second capacitance C2.

A first terminal of the first capacitor C1 may be connected to the boost node V of the first stage charge pump, and a second terminal of the first capacitor C1 may be connected to a first terminal of the second capacitor C2.

The first stage charge pump may further include a third switch K3, where the third switch K3 is connected in parallel with the second capacitor C2, i.e. a first end of the third switch K3 may be used to connect a first end of the second capacitor C2 and a second end of the first capacitor C1, and a second end of the third switch K3 may be used to connect a second end of the second capacitor C2.

When the comparison voltage cmp_out is "0", the comparison voltage cmp_out controls the third switch K3 to be turned off, and the first capacitor C1 is connected in series with the second capacitor C2, and the second end of the second capacitor C2 is used for receiving the first clock signal CLK1, so that the charge pump capacitor of the first stage charge pump is the first capacitanceWhen the comparison voltage cmp_out is the second voltage value "1", the third switch K3 is controlled to be turned on by the comparison voltage cmp_out, and the second end of the first capacitor C1 is used for receiving the first clock signal CLK1, so that the charge pump capacitor of the first stage charge pump is the second capacitance value C1, i.e. the first capacitance value ∈of the first stage charge pump is satisfied >Less than the second capacitance C1.

The charge pump circuit may further include a second stage charge pump, an input terminal of which may be connected to the boost node V of the first stage charge pump, and a charge pump capacitor of the second stage charge pump may include a third capacitor C3 and a fourth capacitor C4.

A first terminal of the third capacitor C3 may be connected to the boost node V of the second stage charge pump, and a second terminal of the third capacitor C3 may be connected to a first terminal of the fourth capacitor C4.

The second stage charge pump may further include a fourth switch K4, where the fourth switch K4 is connected in parallel with the fourth capacitor C4, i.e. a first end of the fourth switch K4 is used to connect the first end of the fourth capacitor C4 and a second end of the third capacitor C3, and a second end of the fourth switch K4 may be used to connect the second end of the fourth capacitor C4.

When the comparison voltage cmp_out is "0", the comparison voltage cmp_out controls the fourth switch K4 to be turned off, and the third capacitor C3 is connected in series with the fourth capacitor C4, and the second end of the fourth capacitor C4 is used for receiving the third clock signal CLK3, so that the charge pump capacitor of the second stage charge pump is the first capacitanceWhen the comparison voltage cmp_out is the second voltage value "1", the comparison voltage cmp_out controls the fourth switch K4 to be turned on, and the second end of the third capacitor C3 is used for receiving the third clock signal CLK3, so that the charge pump capacitor of the second stage charge pump is the second capacitance value C3, i.e. the second stage charge pump is satisfied First capacitance value->Less than the second capacitance C3.

The first stage charge pump in the embodiment of fig. 9 may further include a first NMOS transistor M1, the second stage charge pump may further include a second NMOS transistor M2, the third stage charge pump may further include an NMOS transistor M3, the fourth stage charge pump may further include an NMOS transistor M4, and the nth stage charge pump may further include an NMOS transistor, which may be specifically referred to the embodiment of fig. 8 described above.

The first capacitance in the above embodiment may be equal to the third capacitance, and the second capacitance may be equal to the fourth capacitance.

In the above embodiment, the generation of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 may refer to the embodiment of fig. 3, but the disclosure is not limited thereto, and the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 generated by the clock driving circuit in the embodiment of the disclosure may satisfy the following conditions: the first clock signal CLK1 and the third clock signal CLK3 are anti-phase signals; when the second clock signal CLK2 and the fourth clock signal CLK4 are not dc voltages, the second clock signal CLK2 and the first clock signal CLK1 are in-phase signals, the third clock signal CLK3 and the fourth clock signal CLK4 are in-phase signals, i.e., the first clock signal CLK1 and the fourth clock signal CLK4 are in-phase signals, and the second clock signal CLK2 and the third clock signal CLK3 are in-phase signals. The embodiment of the present disclosure is not limited to a specific circuit configuration of the clock driving circuit.

It will be appreciated that the embodiments of the present disclosure are not limited to a specific circuit configuration within a charge pump, and that the circuit configurations of the charge pump in fig. 4-9 described above are merely for illustration, e.g., N4 and P2 may be interchanged and N5 and P3 may be interchanged in the embodiments of fig. 4-7. For another example, M1 to MN in fig. 8 to 9 may be replaced with diodes as long as it is possible to realize that the control charges can be transferred only in one direction. The charge pump circuitry of embodiments of the present disclosure may employ any suitable charge pump.

Various structures of charge pump capacitors (boost capacitors) may be included in each stage of charge pump in the charge pump circuit provided by embodiments of the present disclosure.

The charge pump circuit provided in the embodiments of the present disclosure is not limited to the circuit structure exemplified in the above embodiment, two capacitors are connected in parallel to each boost node for illustration, for example, a first boost node is connected in parallel to a first capacitor and a second capacitor, and a second boost node is connected in parallel to a third capacitor and a fourth capacitor; alternatively, the boost nodes are connected in parallel to the first capacitor and the second capacitor, or the third capacitor and the fourth capacitor, but the disclosure is not limited thereto, in other embodiments, each boost node of each stage of charge pump may be connected in parallel to three or more capacitors, and when the power supply voltage is high, the clock signal received by the second end of some of the three or more capacitors is controlled to be a fixed dc voltage, the second end of the other part of the capacitors is controlled to receive the clock signal periodically changing in high and low levels, and when the power supply voltage is low, the second end of the three or more capacitors is controlled to receive the clock signal periodically changing in high and low levels, so as to realize more flexible adjustment of the charge pump capacitor under the high and low power supply voltages.

In other embodiments, the power supply voltage detection circuit may further detect whether the power supply voltage is greater than a multi-stage voltage threshold, and when three or more capacitors are connected in parallel to each boost node, it may be determined, according to which stage voltage threshold the detected power supply voltage is within, which part of the three or more capacitors receives a clock signal that is a fixed dc voltage, which part of the capacitors receives a clock signal that periodically varies in high-low level, so that multi-stage regulation of the charge pump capacitors under multi-stage (three or more) power supply voltages may be achieved.

In the above embodiment, two capacitors are connected in series to each boost node for illustration, but the disclosure is not limited thereto, and in other embodiments, three or more capacitors may be connected in series to each boost node of each stage of charge pump, and each capacitor except the first capacitor connected to the boost node is connected in parallel to one switch, and when the power supply voltage is high, the switch connected in parallel to the capacitor is controlled to be turned off, and when the power supply voltage is low, the switch connected in parallel to the capacitor is controlled to be turned on, and the switch connected in parallel to the other capacitor is turned off, so that the charge pump capacitor can be adjusted more flexibly under the power supply voltage.

In still other embodiments, the power supply voltage detection circuit may further detect whether the power supply voltage is greater than a multi-stage voltage threshold, and when three or more capacitors are connected in series to each boost node, it may be determined, according to which stage voltage threshold the detected power supply voltage is within, which part of the parallel-connected switches are controlled to be turned on and which part of the parallel-connected switches are turned off, so that multi-stage regulation of the charge pump capacitors under the multi-stage power supply voltage may be achieved.

Fig. 10 shows a schematic diagram of a memory in an embodiment of the disclosure.

As illustrated in fig. 10, the disclosed embodiments also provide a memory, such as memory 100, that is a non-volatile memory, such as a flash memory. The memory 100 may include a controller 1001, a charge pump circuit 1000, a memory cell array 1002, a row selector 1003, and a column selector 1004. The memory cell array 1002 includes a plurality of memory cells that are addressed by word lines and bit lines. The row selector 1003 is used to select a target word line according to an address. The column selector 1004 is used to select a target bit line according to an address. The controller is used to control operations for the memory cell array 1002, such as a read operation, a write operation, and an erase operation. The charge pump circuit 1000 is configured to provide an operating voltage for the above operation, and the charge pump circuit 1000 may be any of the charge pump circuits described in the above embodiments. For example, the memory 100 is a NAND flash memory, and the charge pump circuit 1000 may supply a program voltage to a target word line in a write operation or a turn-on voltage to a non-target word line in a verify operation. The program voltage and the on voltage are both positive voltages, and the program voltage is greater than the on voltage. For another example, the memory 100 is a NOR flash memory, and the charge pump circuit 1000 may provide a negative high voltage to a target word line in an erase operation, or a negative low voltage to a non-target word line in a verify operation. The memory 100 may also be a Resistive Random Access Memory (RRAM), a Magnetic Random Access Memory (MRAM), or the like.

Further, the embodiment of the disclosure also provides an electronic device, which includes the memory and/or the charge pump circuit according to any one of the embodiments. The electronic device may be any terminal device and/or server, and the terminal device may be any one or more of a mobile phone, a tablet computer, a desktop computer, a notebook computer, a game console, a television, a vehicle-mounted terminal, a wearable intelligent device, and the like.

Exemplary embodiments of the present disclosure are specifically illustrated and described above. It is to be understood that this disclosure is not limited to the particular arrangements, instrumentalities and methods of implementation described herein; on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (15)

1. A charge pump circuit, comprising:

a charge pump, each stage of charge pump comprising a charge pump capacitor;

the charge pump capacitance adjusting circuit is used for detecting the power supply voltage of the charge pump circuit, and adjusting the charge pump capacitance of each stage of charge pump to be a first capacitance value when the power supply voltage is greater than or equal to a voltage threshold value; when the power supply voltage is smaller than the voltage threshold value, adjusting the charge pump capacitance of each stage of charge pump to be a second capacitance value;

Wherein the first capacitance value is smaller than the second capacitance value.

2. The charge pump circuit of claim 1, wherein the charge pump capacitance adjustment circuit comprises a supply voltage detection circuit comprising a first voltage divider resistor, a second voltage divider resistor, and a comparator;

the first end of the first voltage dividing resistor is connected with the power supply voltage, the second end of the first voltage dividing resistor is connected with the first end of the second voltage dividing resistor and the second input end of the comparator, and the second end of the second voltage dividing resistor is grounded so that the second input end of the comparator is used for receiving the divided voltage of the power supply voltage;

the first input end of the comparator is used for receiving a reference voltage;

the output end of the comparator is used for outputting a comparison voltage, and when the divided voltage is greater than or equal to the reference voltage, the comparison voltage is a first voltage value so as to judge that the power supply voltage is greater than or equal to the voltage threshold value; when the divided voltage is smaller than the reference voltage, the comparison voltage is a second voltage value to determine that the power supply voltage is smaller than the voltage threshold.

3. The charge pump circuit of claim 2, further comprising a clock drive circuit for outputting the first clock signal and the second clock signal;

the charge pump comprises a first-stage charge pump, a charge pump capacitor of the first-stage charge pump comprises a first capacitor and a second capacitor, and a first end of the first capacitor and a first end of the second capacitor are connected with a boost node of the first-stage charge pump;

the second end of the first capacitor is used for receiving the first clock signal, and the second end of the second capacitor is used for receiving the second clock signal;

when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the second clock signal to be a direct current voltage so that the charge pump capacitance of the first stage charge pump is the first capacitance value;

when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the first clock signal and the second clock signal to be in-phase signals so that the charge pump capacitance of the first stage charge pump is the second capacitance value.

4. A charge pump circuit according to claim 3, wherein the clock drive circuit comprises:

The input end of the first inverter is used for receiving an initial clock signal;

the input end of the time delay unit is connected with the output end of the first phase inverter;

the input end of the second inverter is connected with the output end of the delay unit;

the input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter is used for outputting the first clock signal;

the first input end of the first NAND gate is connected with the output end of the second inverter, the second input end of the first NAND gate is used for receiving the comparison voltage, and the output end of the first NAND gate is used for outputting the second clock signal.

5. The charge pump circuit of claim 3, wherein the clock drive circuit is further configured to output a third clock signal and a fourth clock signal, the first clock signal and the third clock signal being anti-phase signals;

the charge pump further comprises a second-stage charge pump, the charge pump capacitor of the second-stage charge pump comprises a third capacitor and a fourth capacitor, and the first end of the third capacitor and the first end of the fourth capacitor are connected with a boost node of the second-stage charge pump;

The second end of the third capacitor is used for receiving the third clock signal, and the second end of the fourth capacitor is used for receiving the fourth clock signal;

when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the fourth clock signal to be the direct current voltage so as to enable the charge pump capacitance of the second-stage charge pump to be the first capacitance value;

when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the third clock signal and the fourth clock signal to be in-phase signals so that the charge pump capacitance of the second stage charge pump is the second capacitance value.

6. The charge pump circuit of claim 3, wherein the first stage charge pump comprises a first NMOS transistor having a gate connected to a drain of the first NMOS transistor and an input of the first stage charge pump, respectively, the input of the first stage charge pump being connected to the supply voltage;

and the source electrode of the first NMOS tube is connected with the boost node of the first stage charge pump.

7. The charge pump circuit of claim 6, wherein the clock drive circuit is further configured to output a third clock signal and a fourth clock signal, the first clock signal and the third clock signal being anti-phase signals;

The charge pump further comprises a second-stage charge pump, the charge pump capacitor of the second-stage charge pump comprises a third capacitor and a fourth capacitor, and the first end of the third capacitor and the first end of the fourth capacitor are connected with a boost node of the second-stage charge pump;

the second end of the third capacitor is used for receiving the third clock signal, and the second end of the fourth capacitor is used for receiving the fourth clock signal;

when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the fourth clock signal to be the direct current voltage so as to enable the charge pump capacitance of the second-stage charge pump to be the first capacitance value;

when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the third clock signal and the fourth clock signal to be in-phase signals so as to enable the charge pump capacitance of the second stage charge pump to be the second capacitance value;

the second-stage charge pump further comprises a second NMOS tube, and the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube;

and the source electrode of the second NMOS tube is connected with the boost node of the second-stage charge pump.

8. The charge pump circuit of claim 2, further comprising a clock drive circuit for outputting a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the first clock signal and the third clock signal being anti-phase signals;

The charge pump comprises a first-stage charge pump, and the charge pump capacitor of the first-stage charge pump comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;

the first end of the first capacitor and the first end of the second capacitor are connected with a first boost node of the first stage charge pump;

the second end of the first capacitor is used for receiving the first clock signal, and the second end of the second capacitor is used for receiving the second clock signal;

the first end of the third capacitor and the first end of the fourth capacitor are connected with a second boost node of the first-stage charge pump;

the second end of the third capacitor is used for receiving the third clock signal, and the second end of the fourth capacitor is used for receiving the fourth clock signal;

when the comparison voltage is the first voltage value, the charge pump capacitance adjusting circuit adjusts the second clock signal and the fourth clock signal to be direct-current voltages so that the charge pump capacitance of the first-stage charge pump is the first capacitance value;

when the comparison voltage is the second voltage value, the charge pump capacitance adjusting circuit adjusts the first clock signal and the second clock signal to be in-phase signals, and the third clock signal and the fourth clock signal to be in-phase signals, so that the charge pump capacitance of the first stage charge pump is the second capacitance value.

9. The charge pump circuit of claim 8, wherein the first stage charge pump comprises a fourth NMOS transistor, a fifth NMOS transistor, a second PMOS transistor, and a third PMOS transistor;

the input end of the first stage charge pump is used for receiving the power supply voltage;

the fourth NMOS tube is arranged between the input end of the first-stage charge pump and the second boost node, the second PMOS tube is arranged between the second boost node and the output end of the first-stage charge pump, and the grid electrodes of the fourth NMOS tube and the second PMOS tube are connected with the first boost node;

the fifth NMOS tube is arranged between the input end of the first stage charge pump and the first boost node, the third PMOS tube is arranged between the first boost node and the output end of the first stage charge pump, and the gates of the fifth NMOS tube and the third PMOS tube are connected with the second boost node.

10. The charge pump circuit of any one of claims 5, 7, 8, or 9, wherein the first capacitance is equal to the third capacitance and the second capacitance is equal to the fourth capacitance.

11. The charge pump circuit according to any one of claims 3 to 9, wherein the direct current voltage is equal to the power supply voltage.

12. The charge pump circuit of claim 2, further comprising a clock drive circuit for outputting a first clock signal;

the charge pump comprises a first-stage charge pump, a charge pump capacitor of the first-stage charge pump comprises a first capacitor and a second capacitor, a first end of the first capacitor is connected with a first boost node of the first-stage charge pump, and a second end of the first capacitor is connected with a first end of the second capacitor;

the first stage charge pump further comprises a first switch;

the second capacitor is connected with the first switch in parallel, when the comparison voltage is the first voltage value, the first switch is controlled to be disconnected through the comparison voltage, the first capacitor is connected with the second capacitor in series, and the second end of the second capacitor is used for receiving the first clock signal so as to enable the charge pump capacitor of the first-stage charge pump to be the first capacitance value; when the comparison voltage is the second voltage value, the first switch is controlled to be conducted through the comparison voltage, and the second end of the first capacitor is used for receiving the first clock signal so that the charge pump capacitor of the first stage charge pump is the second capacitance value.

13. The charge pump circuit of claim 12, wherein the clock drive circuit is further configured to output a third clock signal, the first clock signal and the third clock signal being anti-phase signals;

the charge pump capacitor of the first-stage charge pump further comprises a third capacitor and a fourth capacitor, a first end of the third capacitor is connected with the second boost node of the first-stage charge pump, and a second end of the third capacitor is connected with the first end of the fourth capacitor;

the first stage charge pump further comprises a second switch;

the first end of the third capacitor is connected with the second end of the fourth capacitor;

the fourth capacitor is connected with the second switch in parallel, when the comparison voltage is the first voltage value, the second switch is controlled to be disconnected through the comparison voltage, the third capacitor is connected with the fourth capacitor in series, and the second end of the fourth capacitor is used for receiving the third clock signal so that the charge pump capacitor of the first-stage charge pump is the first capacitance value; and when the comparison voltage is the second voltage value, the second switch is controlled to be conducted through the comparison voltage, and the second end of the third capacitor is used for receiving the third clock signal so as to enable the charge pump capacitor of the first stage charge pump to be the second capacitance value.

14. A memory comprising a charge pump circuit as claimed in any one of claims 1 to 13.

15. An electronic device comprising the memory of claim 14.