CN116666223B - Technological method for improving SGT threshold voltage stability and SGT device - Google Patents
Technological method for improving SGT threshold voltage stability and SGT device Download PDFInfo
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Abstract
The invention provides a process method for improving SGT threshold voltage stability and an SGT device, the method comprises the steps of measuring the width of a groove after etching the groove, differentiating the measured groove width value with a corresponding target value, inputting a first difference value into a mapping model, outputting a first target gear, forming a grid in the groove, controlling source electrode ion implantation, calling a photoetching program according to the first target gear to control etching of a through hole, measuring the width of the through hole, differentiating a measuring result with the corresponding target value to obtain a second difference value, determining a second target gear according to the second difference value, finally judging whether the first target gear and the second target gear are the same gear, if yes, ending the control process flow, and if no, re-debugging the photoetching program to ensure that the first difference value and the second difference value which are finally etched belong to the same gear, and guaranteeing the fluctuation condition of the size of the groove and the size of the through hole, thereby improving the stability of the threshold voltage.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a process method for improving SGT threshold voltage stability and an SGT device.
Background
MOSFETs can be broadly divided into the following categories: a planar MOSFET; trench MOSFET is mainly used in low voltage field; SGT (Shielded Gate Transistor, shielded gate trench) MOSFETs, mainly for medium and low voltage applications; SJ- (superjunction) MOSFETs are mainly used in high voltage applications.
The SGT MOSFET structure has a charge coupling effect, horizontal depletion is introduced on the basis of vertical depletion of PN junctions of the traditional trench MOSFET device, and the device can obtain higher breakdown voltage under the condition of adopting epitaxial materials with the same doping concentration. Deeper trench depths may take advantage of more silicon volume to absorb EAS (Energy Avalanche Stress, avalanche energy test) energy so the SGT may perform better in avalanche and be more tolerant of avalanche breakdown and surge currents. In the application fields of switching power supplies, motor control, power battery systems and the like, the SGT MOSFET is matched with advanced packaging, so that the efficiency and the power density of the system are improved.
The threshold voltage of the MOS device refers to the gate voltage when the drain and the source of the device are just conducted, and the requirement of the threshold voltage is mainly determined by the applied driving voltage. The stability of the threshold voltage is very important, especially in multi-MOS parallel applications (e.g. motor control, BMS, etc.), if the threshold voltage difference is large, the device that is turned on the highest can cause thermal failure due to large current.
During SGT process fabrication, the fabrication process is subject to instability, which typically occurs over a range of fluctuations, such as trench size, trench depth, implant dose and energy stability, thermal process stability, and dielectric and via dimensions. The main factors affecting the SGT threshold voltage are gate oxide thickness and quality, impurity ion implantation concentration, trench size, via size, uniformity and consistency of heat treatment, etc. As the line width and the like gradually decrease, the correlation between the trench size, the via size and the like and the threshold voltage becomes stronger, and therefore, the control and matching of the trench size and the via size are particularly important.
Disclosure of Invention
Based on this, the invention aims to provide a process method for improving SGT threshold voltage stability and an SGT device, and aims to solve the problem of large fluctuation of threshold voltage caused by fluctuation and mismatch of trench size and via size in the prior art.
According to one embodiment of the invention, a process for improving SGT threshold voltage stability includes:
providing an epitaxial substrate, and depositing a mask layer with a composite structure on the epitaxial substrate;
etching on the epitaxial substrate deposited with the mask layer to form a trench;
obtaining a first target value, measuring the width of the groove to obtain a groove width value, and performing difference between the groove width value and the first target value to obtain a first difference value;
inputting the first difference value into a mapping model, and outputting a corresponding first target gear;
forming a grid in the groove, controlling source electrode ion implantation, and calling a corresponding photoetching program according to the first target gear so as to control etching of the through hole;
obtaining a second target value, measuring the width of the through hole to obtain a through hole width value, and performing difference between the through hole width value and the second target value to obtain a second difference value;
inputting the second difference value into the mapping model, and outputting a corresponding second target gear;
judging whether the first target gear and the second target gear are the same gear or not;
if yes, the control process flow is ended;
if not, debugging the photoetching program again so that the first difference value and the second difference value which are finally etched belong to the same gear.
Further, before the step of inputting the first difference value into the mapping model and outputting the corresponding first target gear, the step of inputting the first difference value into the mapping model includes:
and establishing a mapping relation between the preset range value and each first target gear to obtain a mapping model, wherein the mapping model is used for inputting a specific value and outputting the first target gear corresponding to the preset range value.
Further, the first target gear includes three sub-gears, the first sub-gear corresponds to a preset range value of [ -0.1 μm, -0.05 μm ], the second sub-gear corresponds to a preset range value (-0.05 μm,0.05 μm), and the third sub-gear corresponds to a preset range value of [0.05 μm,0.1 μm ].
Further, the first target gear includes three sub-gears, the first sub-gear corresponds to a preset range value of [ -0.15 μm, -0.05 μm ], the second sub-gear corresponds to a preset range value (-0.05 μm,0.05 μm), and the third sub-gear corresponds to a preset range value of [0.05 μm,0.15 μm ].
Further, the first target gear includes four sub-gears, the first sub-gear corresponds to a preset range value of [ -0.1 μm, -0.05 μm), the second sub-gear corresponds to a preset range value of [ -0.05 μm,0 μm), the third sub-gear corresponds to a preset range value of [0 μm,0.05 μm), and the fourth sub-gear corresponds to a preset range value of [0.05 μm,0.1 μm ].
Further, the step of forming a gate in the trench includes:
growing a first oxide layer on the inner wall of the groove in a thermal oxidation mode, wherein the first oxide layer is used as a dielectric layer on the side wall of the shielding gate;
filling shielding gate polysilicon in the groove, and grinding and leveling by adopting a CMP technology and then etching back to form a shielding gate in the groove;
etching the dielectric layer on the side wall to a preset depth by adopting a wet etching technology, filling an isolation oxide layer between the grid electrode and the shielding grid, and then growing a second oxide layer through thermal oxidation to form a grid oxide layer;
and depositing polysilicon on the second oxide layer to enable the polysilicon to fill the groove, and adopting a CMP technology to polish down to finish the manufacture of the grid electrode.
Further, in the step of growing a first oxide layer on the inner wall of the trench in a thermal oxidation manner, wherein the first oxide layer is used as a dielectric layer on the side wall of the shielding gate, the growth temperature of the first oxide layer is 800-1100 ℃, and the growth thickness of the first oxide layer is 4000-6000 a.
Further, in the step of etching the dielectric layer of the side wall to a preset depth by adopting a wet etching technology, the preset depth is 1.5-2.5 μm.
Further, in the step of growing the second oxide layer by thermal oxidation to form the gate oxide layer, the thickness of the second oxide layer is 400 a to 600 a.
According to the SGT device, the SGT device is manufactured through the technical method for improving the stability of the SGT threshold voltage.
Compared with the prior art: the invention provides a process method for improving SGT threshold voltage stability and an SGT device, which are characterized in that an epitaxial substrate is provided, a mask layer is deposited on the epitaxial substrate, then etching is carried out on the epitaxial substrate deposited with the mask layer to form a groove, a first target value is obtained, the width of the groove is measured to obtain a groove width value, the groove width value is differed from the first target value to obtain a first difference value, the first difference value is input into a mapping model, a corresponding first target gear is output, a grid is formed in the groove, then source electrode ion implantation is controlled, a corresponding photoetching program is called according to the first target gear, so as to control etching of a through hole, a second target value is obtained, the width of the through hole is measured to obtain a width value of the through hole, the width value of the through hole is differed from the second target value, the second difference value is obtained, the second difference value is input into the mapping model, whether the first target gear and the second target gear are identical or not is finally judged, if yes, the control process flow is finished, if no, the corresponding first target gear and the size of the through hole are not matched with the first target gear, and the size of the through hole are not adjusted, and the stability is improved.
Drawings
FIG. 1 is a flowchart of a process for improving SGT threshold voltage stability according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure of trenches and vias in an SGT device.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the SGT MOS production process, in order to reduce contact resistance, the resistance of a base region is reduced, so that the current impact resistance of a chip can be improved, and in the process of a through hole, heavy doping ion implantation and heat treatment are required, and ions are diffused to the vicinity of a channel to influence threshold voltage due to the fact that the size of a repeating unit on the chip is smaller and smaller. The size of the trench can affect the size of the active region, and further affect the distance from the via to the channel, thereby affecting the stability of the threshold voltage. The technical method for improving the stability of the SGT threshold voltage provided by the embodiment of the invention greatly improves the stability of the distance from the through hole to the channel, so that the stability of the threshold voltage is improved.
Referring to fig. 1, fig. 1 is a flowchart illustrating a process for improving SGT threshold voltage stability according to an embodiment of the present invention, where the process specifically includes the following steps:
s01: providing an epitaxial substrate, and depositing a mask layer with a composite structure on the epitaxial substrate;
specifically, an epitaxial substrate is provided, which may be a silicon substrate, the epitaxial substrate does not limit an N substrate or a P substrate, and a mask layer having a composite structure is deposited on the epitaxial substrate, wherein the mask layer is sequentially composed of a first oxide layer, a nitride layer and a second oxide layer, that is, an ONO (oxide layer/nitride layer/oxide layer) structure, the nitride layer is a silicon nitride, and the oxide layer/nitride layer/oxide layer is a three-layer structure, wherein the combination of the oxide layer and the base crystal is better than the nitride layer, and the nitride layer is centered, so that the extension of defects can be blocked, and the three-layer structure is complementary.
S02: etching on the epitaxial substrate deposited with the mask layer to form a trench;
after the preparation of the mask layer is completed, etching is performed on the epitaxial substrate deposited with the mask layer to form a groove, and the deeper the groove is, the thicker the photoresist required in etching is, but the photoresist is easy to fall off after being exposed too thick, so that the mask layer is required to replace the effect of the photoresist, and the photoresist is thinned, besides the groove is etched, the mask layer can also be used as a barrier layer of CMP and HDP so as to protect the surface of the substrate from being damaged.
S03: obtaining a first target value, measuring the width of the groove to obtain a groove width value, and performing difference between the groove width value and the first target value to obtain a first difference value;
specifically, the first target value is a theoretical width value of the groove in design, after the groove is formed, the groove can be shot through an image recognition mode, then a shot groove picture is recognized to obtain the groove width value, or a metallographic microscope is used for measuring the groove width through a manual mode to obtain the groove width value, and then the groove width value and the theoretical width value are subjected to difference to obtain a first difference value.
S04: inputting the first difference value into a mapping model, and outputting a corresponding first target gear;
specifically, before the first difference is input into the mapping model, a mapping model is first established, wherein a mapping relation between a preset range value and each first target gear is established to obtain the mapping model, and the mapping model is used for inputting a specific value and outputting the first target gear corresponding to the preset range value.
It should be noted that, in order to ensure that the distance between the via and the trench (conductive channel) remains unchanged, the width of the via is changed correspondingly by adjusting the process procedure when the via is exposed according to different trench widths, so that the influence caused by the trench width can be compensated.
In this embodiment, the first target gear includes three sub-gears, the first sub-gear corresponds to a preset range value of [ -0.1 μm, -0.05 μm ], the second sub-gear corresponds to a preset range value (-0.05 μm,0.05 μm), the third sub-gear corresponds to a preset range value [0.05 μm,0.1 μm ], for convenience of understanding, the first sub-gear is designated as A1 gear, the second sub-gear is designated as B1 gear, and the third sub-gear is designated as C1 gear, it being understood that, for example, when the first difference is-0.06 μm, it belongs to A1 gear; when the first difference value is 0 μm, the B1 grade is included; when the first difference is 0.06 μm, it belongs to C1. And establishing a mapping relation between the preset range value and each sub-gear through the rule.
In other embodiments of the present invention, the first target gear includes three sub-gears, the first sub-gear corresponds to a preset range value of [ -0.15 μm, -0.05 μm ], the second sub-gear corresponds to a preset range value (-0.05 μm,0.05 μm), the third sub-gear corresponds to a preset range value [0.05 μm,0.15 μm ], for ease of understanding, the first sub-gear is designated as A2 gear, the second sub-gear is designated as B2 gear, and the third sub-gear is designated as C2 gear, it being understood that, for example, when the first difference is-0.12 μm, it is in A2 gear; when the second difference value is 0 μm, the second difference value belongs to B2; when the third difference is 0.12 μm, it belongs to C2. And establishing a mapping relation between the preset range value and each sub-gear through the rule.
In other embodiments of the present invention, the first target gear includes four sub-gears, the first sub-gear corresponding to a preset range value of [ -0.1 μm, -0.05 μm), the second sub-gear corresponding to a preset range value of [ -0.05 μm,0 μm), the third sub-gear corresponding to a preset range value of [0.05 μm,0.05 μm), the fourth sub-gear corresponding to a preset range value of [0.05 μm,0.1 μm ], for ease of understanding, the first sub-gear is designated as A3 gear, the second sub-gear is designated as B3 gear, the third sub-gear is designated as C3 gear, and the fourth sub-gear is designated as D3 gear, it being understood that, for example, when the first difference is-0.06 μm, it is designated as A3 gear; when the second difference is-0.01 mu m, the second difference belongs to B3; when the third difference is 0.01 μm, the third difference belongs to C3; when the fourth difference is 0.06 μm, it belongs to D3. And establishing a mapping relation between the preset range value and each sub-gear through the rule.
S05: forming a grid in the groove, controlling source electrode ion implantation, and calling a corresponding photoetching program according to the first target gear so as to control etching of the through hole;
specifically, the step of forming a gate in the trench includes:
growing a first oxide layer on the inner wall of the groove in a thermal oxidation mode, wherein the first oxide layer is used as a dielectric layer on the side wall of the shielding gate, the growth temperature of the first oxide layer is 800-1100 ℃, and the growth thickness of the first oxide layer is 4000-6000A;
filling shielding gate polysilicon in the trench, and grinding and leveling by adopting a CMP technology and then back etching to form a shielding gate in the trench;
etching the dielectric layer on the side wall to a preset depth by adopting a wet etching technology, filling an isolation oxide layer between the grid electrode and the shielding grid, and growing a second oxide layer through thermal oxidation to form a grid oxide layer, wherein the preset depth is 1.5-2.5 mu m, and the thickness of the second oxide layer is 400-600A;
and depositing polysilicon on the second oxide layer to enable the polysilicon to fill the groove, and adopting a CMP technology to polish down to finish the manufacture of the grid electrode.
S06: obtaining a second target value, measuring the width of the through hole to obtain a through hole width value, and performing difference between the through hole width value and the second target value to obtain a second difference value;
specifically, the second target value is a theoretical width value of the through hole in design, after the through hole is formed, the through hole can be shot through an image recognition mode, then a shot through hole picture is recognized to obtain the through hole width value, or a metallographic microscope is used for measuring the through hole width through a manual mode to obtain the through hole width value, and then the through hole width value and the theoretical width value are subjected to difference to obtain a second difference value.
S07: inputting the second difference value into the mapping model, and outputting a corresponding second target gear;
s08: judging whether the first target gear and the second target gear are the same gear, if so, executing a step S09, and if not, executing a step S10;
it will be appreciated that if there are three sub-gears, such as A1 gear, B1 gear and C1 gear, when the first difference value falls into A1 gear, it needs to be determined whether the second difference value also falls into A1 gear, and similarly, when the first difference value falls into B1 gear, it needs to be determined whether the second difference value also falls into B1 gear, and when the first difference value falls into C1 gear, it needs to be determined whether the second difference value also falls into C1 gear. If there are four sub-gears, for example, A3 gear, a B3 gear, a C3 gear and a D3 gear, when the first difference value falls into the A3 gear, it needs to be determined whether the second difference value also falls into the A3 gear, and similarly, when the first difference value falls into the B3 gear, it needs to be determined whether the second difference value also falls into the B3 gear, when the first difference value falls into the C3 gear, it needs to be determined whether the second difference value also falls into the C3 gear, and when the first difference value falls into the D3 gear, it needs to be determined whether the second difference value also falls into the D3 gear.
S09: the control process flow ends;
s10: the photolithography process is debugged again so that the first difference value and the second difference value of the final etching belong to the same gear.
Referring to fig. 2, a schematic structural diagram of a trench and a via hole in an SGT device is shown, and it is to be noted that, according to different widths of the trench 1, a process procedure when the via hole 2 is exposed is adjusted, and the width of the via hole 2 is changed accordingly to ensure that the distance between the via hole 2 and the trench 1 (conductive channel) remains unchanged, so that the influence caused by the trench width can be compensated, that is, d1 is always kept equal to d2, d1 is represented as a distance between the trench 1 and the via hole 2 etched under a certain photolithography procedure, and d2 is represented as a distance between the trench 1 and the via hole 2 etched under another photolithography procedure, where a dotted line is represented as a condition that the width of the trench 1 is reduced and the width of the via hole 2 is increased.
The invention is further illustrated by the following examples:
example 1
The embodiment provides a process method for improving SGT threshold voltage stability, which comprises the following steps:
(1) Providing an epitaxial substrate, and depositing a mask layer with a composite structure on the epitaxial substrate;
(2) Etching on the epitaxial substrate deposited with the mask layer to form a trench;
(3) Obtaining a first target value, measuring the width of the groove to obtain a groove width value, and performing difference between the groove width value and the first target value to obtain a first difference value, wherein the first difference value is 0 mu m;
(4) Inputting the first difference value into a mapping model, and outputting a corresponding first target gear, wherein the first target gear comprises three sub gears, the preset range value corresponding to the first sub gear (A1) is [ -0.1 mu m, -0.05 mu m ], the preset range value corresponding to the second sub gear (B1) is (-0.05 mu m,0.05 mu m), the preset range value corresponding to the third sub gear (C1) is [0.05 mu m,0.1 mu m ], and the first difference value 0 mu m belongs to the second sub gear (B1);
(5) Forming a grid in the groove, controlling source electrode ion implantation, and calling a corresponding photoetching program according to a target gear so as to control etching of the through hole;
(6) Obtaining a second target value, measuring the width of the through hole to obtain a through hole width value, and performing difference between the through hole width value and the second target value to obtain a second difference value, wherein the second difference value is 0 mu m;
(7) Inputting the second difference value into a mapping model, outputting a corresponding second target gear, wherein the second target gear also comprises three sub-gears, the preset range value corresponding to the first sub-gear (A1) is [ -0.1 mu m, -0.05 mu m ], the preset range value corresponding to the second sub-gear (B1) is (-0.05 mu m,0.05 mu m), and the preset range value corresponding to the third sub-gear (C1) is [0.05 mu m,0.1 mu m ];
(8) Judging whether the first target gear and the second target gear are the same gear, if so, executing the step (9), otherwise, executing the step (10);
specifically, the second difference value 0 μm also belongs to the second sub-gear (B1).
(9) The control process flow ends;
the prepared SGT device is subjected to threshold voltage, and the threshold voltage obtained by testing is 3.1mV.
(10) The photolithography process is debugged again so that the first difference value and the second difference value of the final etching belong to the same gear.
Example 2
The present embodiment provides a process for improving stability of SGT threshold voltage, which is different from embodiment 1 in that the first difference is 0.06 μm, the second difference is 0.05 μm, and the first difference is the third sub-gear (C1), and the threshold voltage obtained by the test is 3.13mV.
Example 3
The present embodiment provides a process for improving stability of SGT threshold voltage, which is different from embodiment 1 in that the first difference is 0.02 μm, the second difference is 0.02 μm, and the first difference is the second sub-gear (B1), and the threshold voltage obtained by the test is 3.12mV.
Example 4
The present embodiment provides a process for improving stability of SGT threshold voltage, which is different from embodiment 1 in that the first difference is-0.02 μm, the second difference is-0.02 μm, and the first difference is the second sub-gear (B1), and the threshold voltage obtained by the test is 3.08mV.
Example 5
The present embodiment provides a process for improving stability of SGT threshold voltage, which is different from embodiment 1 in that the first difference is-0.06 μm, the second difference is-0.05 μm, and the first difference is the first sub-gear (A1), and the threshold voltage obtained by the test is 3.12mV.
Example 6
The present embodiment provides a process for improving stability of SGT threshold voltage, which is different from embodiment 1 in that the first difference is 0.06 μm, belonging to the third sub-gear (C1 gear), the second difference is 0 μm, belonging to the second sub-gear (B1), and the threshold voltage obtained by the test is 3.22mV.
Example 7
The difference between the technical method for improving the stability of the SGT threshold voltage and the technical method for improving the stability of the SGT threshold voltage is that the first target gear and the second target gear both comprise three sub-gears, specifically, the preset range value corresponding to the first sub-gear (A2 gear) is [ -0.15 μm, -0.05 μm, the preset range value corresponding to the second sub-gear (B2 gear) is (-0.05 μm,0.05 μm), the preset range value corresponding to the third sub-gear (C2 gear) is [0.05 μm,0.15 μm ], in addition, the first difference value is-0.05 μm, the second difference value is-0.12 μm, the first sub-gear (A2 gear) is the threshold voltage obtained through testing at the moment is 2.96mV.
Example 8
The difference between the technical method for improving the stability of the SGT threshold voltage and the technical method for improving the stability of the SGT threshold voltage according to the embodiment 1 is that the first target gear and the second target gear each include three sub-gears, specifically, the first sub-gear (A2 gear) corresponds to a preset range value of [ -0.15 μm, -0.05 μm, the second sub-gear (B2 gear) corresponds to a preset range value (-0.05 μm,0.05 μm), the third sub-gear (C2 gear) corresponds to a preset range value [0.05 μm,0.15 μm ], in addition, the first difference is 0.05 μm, the second difference is 0.15 μm, and the first sub-gear (A2 gear) corresponds to the third sub-gear (C2 gear), and the threshold voltage obtained by the test at this time is 3.25mV.
Example 9
The difference between the technical method for improving the stability of the SGT threshold voltage and the technical method for improving the stability of the SGT threshold voltage according to the embodiment 1 is that the first target gear and the second target gear each include four sub-gears, the preset range value corresponding to the first sub-gear (A3 gear) is [ -0.1 μm, -0.05 μm), the preset range value corresponding to the second sub-gear (B3 gear) is [ -0.05 μm,0 μm), the preset range value corresponding to the third sub-gear (C3 gear) is [0 μm,0.05 μm ], the preset range value corresponding to the fourth sub-gear (D3 gear) is [0.05 μm,0.1 μm ], in addition, the first difference value is-0.02 μm, the second difference value is-0.03 μm, all belong to the second sub-gear (B3 gear), and the threshold voltage obtained by the test at this time is 3.07mV.
Example 10
The difference between the technical method for improving the stability of the SGT threshold voltage and the technical method for improving the stability of the SGT threshold voltage according to the embodiment 1 is that the first target gear and the second target gear each include four sub-gears, the first sub-gear (A3 gear) has a preset range value of [ -0.1 μm, -0.05 μm), the second sub-gear (B3 gear) has a preset range value of [ -0.05 μm,0 μm), the third sub-gear (C3 gear) has a preset range value of [0 μm,0.05 μm), the fourth sub-gear (D3 gear) has a preset range value of [0.05 μm,0.1 μm ], the first difference value is 0 μm, the second difference value is 0.02 μm, and the first sub-gear (B3 gear) has a preset range value of [ -0.05 μm, the third sub-gear (C3 gear), and the threshold voltage obtained by the test is 3.12mV.
By comparing the threshold voltage variations (with the threshold voltage as the target value in example 1) of the SGT devices prepared in examples 1 to 10, specific results are as follows:
as can be seen from the table, the SGT device prepared by the method in the embodiment of the invention has stable threshold voltage variation, the fluctuation is controlled within 5%, and most of the fluctuation of the threshold voltage is kept within 1%, when the first target gear and the second target gear both comprise three sub-gears, the preset range value corresponding to the first sub-gear is [ -0.1 μm, -0.05 μm ], the preset range value corresponding to the second sub-gear is (-0.05 μm,0.05 μm), and the preset range value corresponding to the third sub-gear is [0.05 μm,0.1 μm ], if the sub-gears are not matched, the variation of the threshold voltage is increased as shown in embodiment 6; when the first target gear and the second target gear each include three sub-gears, the preset range value corresponding to the first sub-gear is [ -0.15 μm, -0.05 μm ], the preset range value corresponding to the second sub-gear is (-0.05 μm,0.05 μm), and the preset range value corresponding to the third sub-gear is [0.05 μm,0.15 μm ], there is a risk that the threshold voltage is changed more due to a larger range within the sub-gears, as shown in embodiment 7 and embodiment 8; when the first target gear and the second target gear each include four sub-gears, the preset range value corresponding to the first sub-gear is [ -0.1 μm, -0.05 μm), the preset range value corresponding to the second sub-gear is [ -0.05 μm,0 μm), the preset range value corresponding to the third sub-gear is [0 μm,0.05 μm), and the preset range value corresponding to the fourth sub-gear is [0.05 μm,0.1 μm ], the change of the threshold voltage can be controlled more reasonably without affecting the production efficiency, as shown in embodiment 9 and embodiment 10.
The embodiment of the invention also provides an SGT device, which is prepared by the technical method for improving the stability of the SGT threshold voltage.
In summary, a process method for improving stability of SGT threshold voltage and SGT device in the embodiments of the present invention, the method includes providing an epitaxial substrate, depositing a mask layer on the epitaxial substrate, etching on the epitaxial substrate deposited with the mask layer to form a trench, obtaining a first target value, measuring a width of the trench to obtain a trench width value, differentiating the trench width value with the first target value to obtain a first difference value, inputting the first difference value into a mapping model, outputting a corresponding first target gear, forming a gate in the trench, controlling source ion implantation, calling a corresponding photolithography program according to the first target gear, controlling etching of a through hole to obtain a second target value, measuring a width of the through hole to obtain a width value of the through hole, differentiating the width value of the through hole with the second target value to obtain a second difference value, inputting the second difference value into the mapping model, outputting a corresponding second target gear, finally judging whether the first target gear is the same as the second target gear, if the first target gear is the same gear, controlling the first difference value, inputting the first difference value into the mapping model, outputting the corresponding first target gear, forming a gate in the trench, controlling source ion implantation, calling the corresponding photolithography program, controlling etching of the through hole to obtain a second target value, and obtaining a difference value, and comparing the dimension of the first difference value with a specific dimension and improving the threshold voltage.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (6)
1. A process for improving SGT threshold voltage stability, the process comprising:
providing an epitaxial substrate, and depositing a mask layer with a composite structure on the epitaxial substrate;
etching on the epitaxial substrate deposited with the mask layer to form a trench;
forming a gate in the trench, and then controlling source ion implantation;
measuring the width of the groove, adjusting the process program of the through hole in exposure according to the measured width of the groove, controlling the etching of the through hole according to the process program of the through hole in exposure, and correspondingly changing the width of the through hole to ensure that the distance between the through hole and the groove is kept unchanged;
in the process of the through hole, heavy doping ion implantation and heat treatment are carried out to reduce the contact resistance of the base region.
2. The process for improving SGT threshold voltage stability as claimed in claim 1, wherein said step of forming a gate in a trench comprises:
growing a first oxide layer on the inner wall of the groove in a thermal oxidation mode, wherein the first oxide layer is used as a dielectric layer on the side wall of the shielding gate;
filling shielding gate polysilicon in the groove, and grinding and leveling by adopting a CMP technology and then etching back to form a shielding gate in the groove;
etching the dielectric layer on the side wall to a preset depth by adopting a wet etching technology, filling an isolation oxide layer between the grid electrode and the shielding grid, and then growing a second oxide layer through thermal oxidation to form a grid oxide layer;
and depositing polysilicon on the second oxide layer to enable the polysilicon to fill the groove, and adopting a CMP technology to polish down to finish the manufacture of the grid electrode.
3. The process for improving stability of SGT threshold voltage according to claim 2, wherein in the step of growing a first oxide layer on the inner wall of the trench by thermal oxidation, the first oxide layer is used as a dielectric layer on the sidewall of the shield gate, the growth temperature of the first oxide layer is 800 ℃ to 1100 ℃, and the growth thickness of the first oxide layer is 4000 a to 6000 a.
4. The process for improving stability of SGT threshold voltage according to claim 2, wherein in the step of etching the dielectric layer of the sidewall to a predetermined depth by wet etching technology, the predetermined depth is 1.5 μm to 2.5 μm.
5. The process for improving SGT threshold voltage stability according to claim 2, wherein in the step of growing a second oxide layer by thermal oxidation to form a gate oxide layer, the thickness of the second oxide layer is 400 a to 600 a.
6. An SGT device manufactured by the process of any one of claims 1 to 5 for improving SGT threshold voltage stability.
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| JP2006140239A (en) * | 2004-11-11 | 2006-06-01 | Fuji Electric Device Technology Co Ltd | Semiconductor device and its manufacturing method |
| CN103474335A (en) * | 2012-06-07 | 2013-12-25 | 上海华虹Nec电子有限公司 | Method for preparing small-line-width trenched power MOS transistor |
| CN105826205A (en) * | 2016-05-31 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid power device and structure |
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| JP6776205B2 (en) * | 2017-09-20 | 2020-10-28 | 株式会社東芝 | Manufacturing method of semiconductor devices |
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| JP2006140239A (en) * | 2004-11-11 | 2006-06-01 | Fuji Electric Device Technology Co Ltd | Semiconductor device and its manufacturing method |
| CN103474335A (en) * | 2012-06-07 | 2013-12-25 | 上海华虹Nec电子有限公司 | Method for preparing small-line-width trenched power MOS transistor |
| CN105826205A (en) * | 2016-05-31 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid power device and structure |
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