CN116581225B - Flip light-emitting diode chip and preparation method thereof - Google Patents
Flip light-emitting diode chip and preparation method thereof Download PDFInfo
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- CN116581225B CN116581225B CN202310855066.8A CN202310855066A CN116581225B CN 116581225 B CN116581225 B CN 116581225B CN 202310855066 A CN202310855066 A CN 202310855066A CN 116581225 B CN116581225 B CN 116581225B
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Abstract
The application provides a flip-chip light-emitting diode chip and a preparation method thereof, wherein the chip comprises a substrate, and a first semiconductor layer, a current expansion layer, an electrode layer, a Bragg reflection layer and a second semiconductor layer which are sequentially arranged on the substrate; the Bragg reflection through hole is provided with a first bottom surface and a second bottom surface, and the electrode layer is provided with a first surface and a second surface; the projection circle diameter of the first surface is larger than that of the second surface, the projection circle diameter of the first bottom surface is larger than that of the second surface and smaller than that of the first surface, and the projection circle diameter of the second bottom surface is larger than that of the first surface.
Description
Technical Field
The application belongs to the technical field of LED epitaxial wafers, and particularly relates to a flip LED chip and a preparation method thereof.
Background
The LED chip is widely applied to the fields of illumination and display due to environmental protection, energy saving, high response speed, long service life, and the flip LED chip has the remarkable characteristics of insulation, fast heat dissipation, high light efficiency and the like.
After forming the through hole of the Bragg reflection layer, the Bragg reflection layer of the existing flip-chip light-emitting diode can form a bump on the electrode layer, and the bump easily causes the formation of a cavity on the bump by the metal of the connection layer, and finally causes metal migration, reduces the reliability of the light-emitting diode and reduces the service life.
Disclosure of Invention
In order to solve the technical problems, the application provides the flip LED chip and the preparation method thereof, which can thoroughly solve the problem of the convex blocks of the Bragg reflection layer on the electrode layer and improve the reliability of the flip LED chip.
In a first aspect, an embodiment of the present application provides a flip-chip light emitting diode chip, including a substrate, and a first semiconductor layer, a current spreading layer, an electrode layer, a bragg reflection layer, and a second semiconductor layer sequentially disposed on the substrate;
the electrode layer is partially arranged on the current expansion layer, the Bragg reflection layer is arranged on the current expansion layer and the electrode layer, a plurality of Bragg reflection through holes are formed in the Bragg reflection layer, the Bragg reflection through holes are in a round table shape, a first bottom surface is arranged on one side, close to the electrode layer, of the Bragg reflection through holes, a second bottom surface is arranged on one side, far away from the electrode layer, of the Bragg reflection through holes, a first surface is arranged on one side, close to the current expansion layer, of the electrode layer, and a second surface is arranged on one side, far away from the current expansion layer, of the electrode layer;
the electrode layer comprises a P-type electrode and an N-type electrode, the Bragg reflection through holes comprise a P-type Bragg reflection through hole and an N-type Bragg reflection through hole, the P-type electrode and the P-type Bragg reflection through hole are correspondingly arranged, and the N-type electrode and the N-type Bragg reflection through hole are correspondingly arranged;
the projection of the first surface, the second surface, the first bottom surface and the second bottom surface on the substrate is concentric circles, the first surface and the second surface are all circular, the projection circle diameter of the first surface is larger than that of the second surface, the projection circle diameter of the first bottom surface is larger than that of the second surface and smaller than that of the first surface, and the projection circle diameter of the second bottom surface is larger than that of the first surface.
Compared with the prior art, the application has the beneficial effects that: according to the Bragg reflection through hole, the projection circle diameter of the first surface is larger than that of the second surface, the projection circle diameter of the first bottom surface is larger than that of the second surface and smaller than that of the first surface, the projection circle diameter of the second bottom surface is larger than that of the first surface, the protruding blocks of the Bragg reflection layer arranged at the corners of the electrode layer can be removed, holes are prevented from being formed on the protruding blocks by metal of the electric connection layer, metal migration is avoided, the reliability of the light-emitting diode chip is improved, and meanwhile the service life of the light-emitting diode chip is prolonged.
Preferably, an acute angle between the side surface of the electrode layer and the current expansion layer is not more than 25 degrees, the thickness of the electrode layer is not more than 0.5 μm, and the thickness of the Bragg reflection layer ranges from 3 μm to 6 μm.
Preferably, the first semiconductor layer comprises an N-type semiconductor layer, an active light emitting layer, a P-type semiconductor layer and a current blocking layer which are sequentially arranged on the substrate, the area of the P-type semiconductor layer is equal to that of the active light emitting layer, the area of the P-type semiconductor layer is 70% -95% of that of the N-type semiconductor layer, the area of the N-type semiconductor layer is 90% -95% of that of the substrate, the projection of the current blocking layer and the P-type electrode on the substrate is concentric circles, and the area of the current blocking layer is 2% -5 times that of the first surface.
Preferably, a recess is disposed above the N-type semiconductor layer, the recess penetrates through the active light emitting layer and the P-type semiconductor layer, and the N-type electrode is disposed in the recess, so that the N-type electrode is communicated with the N-type semiconductor layer.
Preferably, the current expansion layer is provided with a current expansion through hole, the projection of the current expansion through hole and the concave part on the substrate is concentric circles, and the diameter of the projection circle of the current expansion through hole is not smaller than that of the projection circle of the concave part.
Preferably, the second semiconductor layer includes an electrical connection layer, a first insulation layer, a preset bonding pad layer, a second insulation layer and a bonding pad layer which are sequentially arranged on the bragg reflection layer, the electrical connection layer is partially arranged on the bragg reflection layer, the first insulation layer is arranged on the electrical connection layer and the bragg reflection layer, the preset bonding pad layer is partially arranged on the first insulation layer, and the second insulation layer is arranged on the preset bonding pad layer and the first insulation layer.
Preferably, the electric connection layer comprises a P-type electric connection layer and an N-type electric connection layer, the P-type electric connection layer is connected with the P-type electrode through a P-type Bragg reflection through hole, the N-type electric connection layer is connected with the N-type electrode through an N-type Bragg reflection through hole, a first P-type insulation through hole and a first N-type insulation through hole are arranged on the first insulation layer, the first P-type insulation through hole is arranged above the P-type electric connection layer, and the first N-type insulation through hole is arranged above the N-type electric connection layer.
Preferably, the preset bonding pad layer comprises a P-type preset bonding pad and an N-type preset bonding pad, the P-type preset bonding pad is communicated with the P-type electric connection layer through a first P-type insulation through hole, the N-type preset bonding pad is communicated with the N-type electric connection layer through a first N-type insulation through hole, and the distance between two adjacent P-type preset bonding pads and the N-type preset bonding pad ranges from 20 micrometers to 50 micrometers.
Preferably, the second insulating layer includes a second P-type insulating through hole and a second N-type insulating through hole, the second P-type insulating through hole is disposed above the P-type preset bonding pad, the second N-type insulating through hole is disposed above the N-type preset bonding pad, the bonding pad layer includes a P-type bonding pad and an N-type bonding pad, the P-type bonding pad is communicated with the P-type preset bonding pad through the second P-type insulating through hole, and the N-type bonding pad is communicated with the N-type preset bonding pad through the second N-type insulating through hole.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a flip light emitting diode chip, where the method includes the following steps:
providing a substrate, and depositing a first semiconductor layer on the substrate;
depositing a current spreading layer on the first semiconductor layer;
depositing a P-type electrode and an N-type electrode on the current expansion layer to form an electrode layer;
forming a Bragg reflection layer on the current expansion layer and the electrode layer by utilizing an electron beam evaporation process;
a P-type Bragg reflection through hole and an N-type Bragg reflection through hole are obtained on the Bragg reflection layer by utilizing a plasma etching process so as to form the Bragg reflection through hole;
depositing a second semiconductor layer on the Bragg reflection layer and the Bragg reflection through hole;
the step of forming the Bragg reflection through hole by using a plasma etching process to obtain the P-type Bragg reflection through hole and the N-type Bragg reflection through hole on the Bragg reflection layer comprises the following steps:
dropping photoresist on the surface of the Bragg reflection layer by using a photoresist homogenizing machine, then rotating the photoresist at a high speed for the first time by using a spin coating method, then rotating the photoresist at a high speed for the second time, so that the thickness of the photoresist is 8-12 mu m, then performing first exposure by using a first photoetching plate, wherein the diameter of a light-transmitting area on the first photoetching plate is equal to the projected circle diameter of a first bottom surface, then performing second exposure by using a second photoetching plate, the diameter of the light-transmitting area on the second photoetching plate is equal to the projected circle diameter of a second bottom surface, then performing development by using an alcohol or benzene or phenol or a combined developer of the alcohols or phenols, developing for three times, developing for 10-15S each time by using a developer, then heating and baking the photoresist from the bottom surface of the substrate by using a hot plate, then baking the photoresist again by using an oven, so as to form a photoresist pattern on the Bragg reflection layer, exposing part of the Bragg reflection layer, and then etching the exposed Bragg reflection layer by using coupling inductance plasma to obtain a P-type Bragg reflection through hole and an N-type Bragg reflection through hole to form the Bragg reflection through hole;
the first high-speed rotation speed is 1500-2000r/min, the first high-speed rotation time is 10-15S, the second high-speed rotation speed is 4000-4500r/min, the second high-speed rotation time is 10-15S, the first exposure energy is not less than 1500mj/cm, the light intensity wavelength of the first exposure is 300-340 nm, the second exposure energy is 500 mj/cm-800 mj/cm, the light intensity wavelength of the second exposure is 350-380 nm, the hot plate temperature is 150-160 ℃, the hot plate baking time is 100-150S, the oven temperature is 120-140 ℃, and the oven baking time is 45-55 min.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a diagram illustrating a structure of a flip-chip led chip according to a first embodiment of the present application;
FIG. 2 is an enlarged view of the structure at B in FIG. 1;
FIG. 3 is an enlarged view of the structure at C in FIG. 1;
FIG. 4 is an enlarged view of the structure at D in FIG. 1;
FIG. 5 is a cross-sectional view A-A of FIG. 1;
fig. 6 is a flowchart of a method for manufacturing a flip-chip light emitting diode chip according to a second embodiment of the present application.
Reference numerals illustrate:
embodiments of the present application will be further described with reference to the accompanying drawings.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the application and should not be construed as limiting the application.
In the description of the embodiments of the present application, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the embodiments of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to specific circumstances.
Example 1
As shown in fig. 1 to 5, a first embodiment of the present application provides a flip-chip light emitting diode chip, which includes a substrate 1, and a first semiconductor layer, a current spreading layer 6, an electrode layer, a bragg reflection layer 8, and a second semiconductor layer sequentially disposed on the substrate 1;
the electrode layer is partially arranged on the current expansion layer 6, the Bragg reflection layer 8 is arranged on the current expansion layer 6 and the electrode layer, a plurality of Bragg reflection through holes are formed in the Bragg reflection layer 8, the Bragg reflection through holes are in a round table shape, a first bottom surface 83 is arranged on one side, close to the electrode layer, of the Bragg reflection through holes, a second bottom surface 84 is arranged on one side, far away from the electrode layer, of the Bragg reflection through holes, a first surface 73 is arranged on one side, close to the current expansion layer 6, of the electrode layer, and a second surface 74 is arranged on one side, far away from the current expansion layer 6, of the electrode layer;
wherein an acute angle between the side surface of the electrode layer and the current expansion layer 6 is not more than 25 degrees, the thickness of the electrode layer is not more than 0.5 mu m, the electrode layer is formed by combining Al, ti, pt, ni metal materials, the thickness range of the Bragg reflection layer 8 is 3 mu m-6 mu m, the electrode layer does not comprise Au metal, and meanwhile, the Bragg reflection layer 8 is formed by alternately laminating a plurality of periodically-laminated SiO 2 And TiO 2 The composition is that the lamination period is 20-40.
The electrode layer comprises a P-type electrode 71 and an N-type electrode 72, the bragg reflection through holes comprise a P-type bragg reflection through hole 81 and an N-type bragg reflection through hole 82, the P-type electrode 71 is arranged corresponding to the P-type bragg reflection through hole 81, and the N-type electrode 72 is arranged corresponding to the N-type bragg reflection through hole 82;
specifically, the number ratio between the P-type electrode 71 and the N-type electrode 72 is 1:1-1:5, the bragg reflection layer 8 also has an N-type bragg reflection layer and a P-type bragg reflection layer, the P-type bragg reflection layer corresponds to the P-type electrode 71 and the P-type bragg reflection through hole 81, the N-type bragg reflection layer corresponds to the N-type electrode 72 and the N-type bragg reflection through hole 82, for the polarities of the electrode and the bragg reflection through hole, the upper surface and the lower surface of the P-type electrode 71 are respectively provided with the first surface 73 and the second surface 74, and the upper surface and the lower surface of the P-type bragg reflection through hole 81 are respectively provided with the first bottom surface 83 and the second bottom surface 84, and similarly, the N-type electrode 72 and the N-type bragg reflection through hole 82 also respectively have the first surface 73, the second surface 74 and the first bottom surface 83 and the second bottom surface 84.
Wherein, the projections of the first surface 73, the second surface 74, the first bottom surface 83 and the second bottom surface 84 on the substrate 1 are concentric circles, the first surface 73 and the second surface 74 are both circular, the projected circle diameter of the first surface 73 is larger than the projected circle diameter of the second surface 74, the projected circle diameter of the first bottom surface 83 is larger than the projected circle diameter of the second surface 74 and smaller than the projected circle diameter of the first surface 73, and the projected circle diameter of the second bottom surface 84 is larger than the projected circle diameter of the first surface 73;
specifically, the first surface 73, the second surface 74, the first bottom surface 83, and the second bottom surface 84 are all of the same polarity, that is, for the P-type bragg reflection through hole 81 and the P-type electrode 71, the projections of the first surface 73, the second surface 74, the first bottom surface 83, and the second bottom surface 84 are concentric circles, the first surface 73 and the second surface 74 are all circular, the projected circle diameter of the first surface 73 is larger than the projected circle diameter of the second surface 74, the projected circle diameter of the first bottom surface 83 is larger than the projected circle diameter of the second surface 74, and is smaller than the projected circle diameter of the first surface 73, and the projected circle diameter of the second bottom surface 84 is larger than the projected circle diameter of the first surface 73, and for the N-type electrode 72 and the N-type bragg reflection through hole 82, the first surface 73, the second surface 74, the first bottom surface 83, and the second bottom surface 84 have the relationship of the projected circle diameters;
in this embodiment, the bragg reflection through hole is obtained by the preparation, the projection circle diameter of the first surface 73 is larger than the projection circle diameter of the second surface 74, the projection circle diameter of the first bottom surface 83 is larger than the projection circle diameter of the second surface 74 and smaller than the projection circle diameter of the first surface 73, and the projection circle diameter of the second bottom surface 84 is larger than the projection circle diameter of the first surface 73, so that the bump of the bragg reflection layer 8 at the corner of the electrode layer can be removed, the formation of a void on the bump by the metal of the electric connection layer is avoided, the metal migration is avoided, the reliability of the light emitting diode chip is improved, and the service life of the light emitting diode chip is also prolonged.
In this embodiment, the first semiconductor layer includes an N-type semiconductor layer 2, an active light emitting layer 3, a P-type semiconductor layer 4 and a current blocking layer 5 sequentially disposed on the substrate 1, the area of the P-type semiconductor layer 4 is equal to the area of the active light emitting layer 3, the area of the P-type semiconductor layer 4 is 70% -95% of the area of the N-type semiconductor layer 2, the area of the N-type semiconductor layer 2 is 90% -95% of the area of the substrate 1, the projections of the current blocking layer 5 and the P-type electrode 71 on the substrate 1 are concentric circles, and the area of the current blocking layer 5 is 2% -5 times the area of the first surface 73;
specifically, by providing the current blocking layer 5, and the area of the current blocking layer 5 is 2-5 times that of the first surface 73, the anti-static breakdown capability of the flip-chip light emitting diode chip can be improved.
In this embodiment, a recess 14 is disposed above the N-type semiconductor layer 2, the recess 14 penetrates through the active light emitting layer 3 and the P-type semiconductor layer 4, and the N-type electrode 72 is disposed in the recess 14 so that the N-type electrode 72 communicates with the N-type semiconductor layer 2;
specifically, the recess 14 is specifically disposed above the N-type semiconductor layer 2 and is used for placing the N-type electrode 72, and by disposing the recess 14, a portion of the active light emitting layer 3 and the P-type semiconductor layer 4 can be removed, so that the N-type semiconductor layer 2 can be partially exposed, and meanwhile, the recess 14 can be disposed in a central area or a peripheral area of the flip-chip light emitting diode chip.
In this embodiment, the current spreading layer 6 is provided with a current spreading through hole 61, the projection of the current spreading through hole 61 and the recess 14 on the substrate 1 is concentric circles, and the diameter of the projection circle of the current spreading through hole 61 is not smaller than the diameter of the projection circle of the recess 14.
In this embodiment, the second semiconductor layer includes an electrical connection layer, a first insulating layer 10, a preset pad layer, a second insulating layer 12, and a bonding pad layer sequentially disposed on the bragg reflection layer, the electrical connection layer is partially disposed on the bragg reflection layer 8, the first insulating layer 10 is disposed on the electrical connection layer and the bragg reflection layer 8, the preset pad layer is partially disposed on the first insulating layer 10, and the second insulating layer 12 is disposed on the preset pad layer and the first insulating layer 10.
In this embodiment, the electrical connection layer includes a P-type electrical connection layer 91 and an N-type electrical connection layer 92, the P-type electrical connection layer 91 is connected to the P-type electrode 71 through a P-type bragg reflection through hole 81, the N-type electrical connection layer 92 is connected to the N-type electrode 72 through an N-type bragg reflection through hole 82, a first P-type insulation through hole 101 and a first N-type insulation through hole 102 are provided on the first insulation layer 10, the first P-type insulation through hole 101 is provided above the P-type electrical connection layer 91, and the first N-type insulation through hole 102 is provided above the N-type electrical connection layer 92;
specifically, before preparing the bragg reflection layer 8, part of the first semiconductor layer or the N-type semiconductor layer 2 needs to be removed around the chip to form an isolation groove around the chip, the bragg reflection layer 8 is prepared in the isolation groove, the width of the isolation groove is 4-20 μm, the distance between the electric connection layer and the isolation groove is 15-30 μm, and the distance can prevent the flip-chip light-emitting diode chip from being scattered by metal reflection of the electric connection layer in the dicing process when dicing laser is injected from the substrate surface, so that the risk of low dicing yield is caused, and meanwhile, the electric connection layer can be matched with the bragg reflection layer 8 to form a total reflection structure, so that the external quantum efficiency of the flip-chip light-emitting diode chip is improved;
meanwhile, the first P-type insulating via 101 and the first N-type insulating via 102 are circular or rectangular, and when circular, the diameters of the first P-type insulating via 101 and the first N-type insulating via 102 are not smaller than 20 μm, and when rectangular, the side length of any side is not smaller than 20 μm, and the first insulating layer 10 may be SiO 2 、Al 2 O 3 SiN, etc.
In this embodiment, the preset pad layer includes a P-type preset pad 111 and an N-type preset pad 112, the P-type preset pad 111 is communicated with the P-type electrical connection layer 91 through a first P-type insulation through hole 101, the N-type preset pad 112 is communicated with the N-type electrical connection layer 92 through a first N-type insulation through hole 102, and a distance between two adjacent P-type preset pads 111 and N-type preset pads 112 ranges from 20 μm to 50 μm;
specifically, the distance between the preset pad layer and the isolation groove is 40-50 μm, and the preset pad layer can be one or a combination of a plurality of Al, ag, ti, pt, ni, au, cu metals.
In this embodiment, the second insulating layer 12 includes a second P-type insulating via 121 and a second N-type insulating via 122, the second P-type insulating via 121 is disposed above the P-type preset pad 111, the second N-type insulating via 122 is disposed above the N-type preset pad 112, the bonding pad layer includes a P-type bonding pad 131 and an N-type bonding pad 132, the P-type bonding pad 131 is communicated with the P-type preset pad 111 through the second P-type insulating via 121, and the N-type bonding pad 132 is communicated with the N-type preset pad 112 through the second N-type insulating via 122;
specifically, the second P-type insulating via 121 and the second N-type insulating via 122 are circular or rectangular, and the diameters of the second P-type insulating via 121 and the second N-type insulating via 122 are not smaller than 40 μm when circular, and the side length of any side is not smaller than 40 μm when rectangular, and the first insulating layer 10 may be SiO 2 、Al 2 O 3 SiN, etc.;
meanwhile, in this embodiment, the bonding pad layer includes four P-type bonding pads 131 and four N-type bonding pads 132, the eight bonding pads are rectangular and have equal areas, the size of any side of the eight bonding pads is greater than 200 μm, the distance between two adjacent bonding pads with the same polarity is not less than 100 μm in the P-type bonding pads 131 or the N-type bonding pads 132, the distance between the two adjacent P-type bonding pads 131 and the N-type bonding pads 132 is not less than 150 μm, the flip-chip light emitting diode chip can be bonded with the package body through the P-type bonding pads 131 and the N-type bonding pads 132, and the current from the package body is transmitted to the preset bonding pad layer through the bonding pad layer, the bonding pad layer includes multiple layers of metals, the first layer of metal is Al, ag highly reflective metal, the second layer of metal can be inert metal such as Ti, pt, ni, and the last layer of metal can be Au, sn, auSn alloy, and the like.
Example two
As shown in fig. 6, a second embodiment of the present application provides a method for manufacturing a flip-chip light emitting diode chip, the method comprising the steps of:
s1, providing a substrate 1, and depositing a first semiconductor layer on the substrate 1;
specifically, in step S1, a substrate 1 is provided first, where the substrate 1 may be transparent Al 2 O 3 Or GaN, then sequentially growing an N-type semiconductor layer 2, an active light-emitting layer 3 and a P-type semiconductor layer 4 on the substrate 1 by using an MOCVD process;
then, depositing SiO on the surface of the P-type semiconductor layer 4 by utilizing PECVD process 2 Then at SiO 2 Coating photoresist on the surface by using a spin coating method, exposing and developing to remove part of the photoresist, and exposing part of SiO 2 The exposed SiO is removed by using BOE corrosive liquid 2 Then, the remaining photoresist is removed, and SiO remaining on the P-type semiconductor layer 4 2 Namely, the current blocking layer 5 having a diameter of 36 μm, thereby obtaining a first semiconductor layer.
S2, depositing a current expansion layer 6 on the first semiconductor layer;
specifically, photoresist is coated on the surfaces of the P-type semiconductor layer 4 and the current blocking layer 5, then part of the photoresist is removed by exposure and development, part of the P-type semiconductor layer 4 is exposed, then the exposed P-type semiconductor layer 4 and the active light emitting layer 3 below the part of the P-type semiconductor layer 4 are removed by utilizing an inductively coupled plasma etching process, 24 concave parts 14 are formed, and then the rest of the photoresist is removed by utilizing photoresist removal solution, wherein the diameter of the concave parts 14 is 40 μm;
then, depositing ITO (indium tin oxide) on the surfaces of the P-type semiconductor layer 4, the current blocking layer 5 and the concave part 14 by utilizing a magnetron sputtering process, coating photoresist on the ITO surface, exposing and developing to remove part of the photoresist to expose part of the ITO, and removing the exposed ITO by utilizing an ITO corrosive liquid to form a current expansion layer 6 and a current expansion through hole 61; the current spreading through hole 61 has a diameter of 42 μm.
S3, depositing a P-type electrode 71 and an N-type electrode 72 on the current expansion layer 6 to form an electrode layer;
specifically, a negative photoresist is coated on the current expansion layer 6 and the concave portion 14, then a part of the photoresist is removed by exposure and development, then Cr/Al/Ti/Pt/Ti/Pt/Au/Pt/Ti metal is sequentially evaporated by an electron beam evaporation technology, then metal on the photoresist is removed by a blue film stripping technology, then the photoresist is removed to obtain a plurality of P-type electrodes 71 and a plurality of N-type electrodes 72, so as to form an electrode layer, the structures of the P-type electrodes 71 and the N-type electrodes 72 are completely consistent, a first surface 73 is arranged on one side of the electrode layer close to the current expansion layer 6, a second surface 74 is arranged on one side of the electrode layer far away from the current expansion layer 6, the diameter of the first surface 73 is 24 microns, and the diameter of the second surface 74 is 16 microns.
S4, vapor plating is carried out on the current expansion layer 6 and the electrode layer by utilizing an electron beam vapor plating process to form a Bragg reflection layer 8;
specifically, photoresist is coated on the surfaces of the current expansion layer 6, the electrode layer and the first semiconductor layer which is not covered by the current expansion layer 6, then part of the photoresist is removed by exposure and development, part of the first semiconductor layer is exposed, then the exposed first semiconductor layer is removed by utilizing a coupled inductance plasma etching process, isolation grooves are formed around the chip, and the distance between the isolation grooves and the edge of the substrate is 8 mu m;
then, 26 groups of SiO are sequentially evaporated on the surfaces of the isolation groove, the current expansion layer 6 and the electrode layer by utilizing an electron beam evaporation process 2 And TiO 2 A bragg reflection layer 8 is formed.
S5, a P-type Bragg reflection through hole and an N-type Bragg reflection through hole are obtained on the Bragg reflection layer by utilizing a plasma etching process so as to form the Bragg reflection through hole;
specifically, the step S5 includes:
2 ml-3 ml of photoresist is dripped on the surface of the Bragg reflection layer 8 by using a photoresist homogenizing machine, then the photoresist is rotated at a high speed for the first time by using a spin coating method, the rotating speed of the first time is 1500-2000r/min, the rotating speed of the first time is 10S-15S, then the photoresist is rotated at a high speed for the second time, the rotating speed of the second time is 4000-4500r/min, the rotating speed of the second time is 10S-15S, the thickness of the photoresist is 8 mu m-12 mu m, then the first exposure is performed by using a first photoetching plate, the light intensity wavelength of the first exposure is not less than 1500mj/cm, the diameter of a light transmission area on the first photoetching plate is 300-340 nm, then the second exposure is performed by using a second photoetching plate, the light intensity of the second exposure is 500 mj/cm-800 mj/cm, the light intensity of the second exposure is 350nm, the diameter of the light-transmitting area on the second photoetching plate is equal to the projection circle diameter of the second bottom surface, then development is carried out by using an alcohol, benzene, phenol or a developing solution of the combination of the alcohol, the benzene and the phenol for three times, the development is divided into three times, 2ml to 3ml of developing solution is used for developing 10S to 15S each time, then a hot plate is used for heating and baking photoresist from the bottom surface of the substrate, the temperature of the hot plate is between 150 ℃ and 160 ℃, the baking time of the hot plate is between 100S and 150S, then the photoresist is baked again by using an oven, the temperature of the oven is between 120 ℃ and 140 ℃, the baking time of the oven is between 45min and 55min, so as to form a photoresist pattern on the Bragg reflecting layer, the photoresist image is in the shape of a preset Bragg reflecting through hole, part of the Bragg reflecting layer is exposed, and then the exposed Bragg reflecting layer is etched by using a coupling inductance plasma etching process, and obtaining a P-type Bragg reflection through hole and an N-type Bragg reflection through hole to form the Bragg reflection through hole, wherein a first bottom surface 83 is arranged on one side, close to the electrode layer, of the Bragg reflection through hole, a second bottom surface 84 is arranged on one side, far away from the electrode layer, of the Bragg reflection through hole, the diameter of the first bottom surface 83 is 20 mu m, and the diameter of the second bottom surface is 32 mu m.
By applying different photolithography and different parameter exposure twice in the process of the bragg reflection layer through hole photolithography, the projections of the first surface 73, the second surface 74, the first bottom surface 83 and the second bottom surface 84 are concentric circles, the first surface 73 and the second surface 74 are all circular, the projection circle diameter of the first surface 73 is larger than that of the second surface 74, the projection circle diameter of the first bottom surface 83 is larger than that of the second surface 74 and smaller than that of the first surface 73, and the projection circle diameter of the second bottom surface 84 is larger than that of the first surface 73.
S6, depositing a second semiconductor layer on the Bragg reflection layer 8 and the Bragg reflection through hole;
specifically, firstly, coating negative photoresist on the Bragg reflection layer 8 and the Bragg reflection through hole, exposing and developing to remove part of the photoresist, sequentially evaporating Al/Ti/Ni/Pt/Ni/Pt/Ni/Pt/Au/Ti/Pt/Ti metal by using an electron beam evaporation process, stripping the metal on the rest photoresist by using a blue film stripping technology, and removing the photoresist to obtain a P-type electric connection layer 91 and an N-type electric connection layer 92 to form an electric connection layer;
thereafter, a PECVD process is used to deposit SiO on the electrical connection layer and the Bragg reflection layer 8 not covered by the electrical connection layer 2 Forming a first insulating layer 10, coating photoresist on the surface of the first insulating layer 10, exposing, developing to remove part of the photoresist, exposing part of SiO 2 Then the exposed SiO is removed by wet etching or coupled inductive plasma etching process 2 Forming a first P-type insulating through hole 101 and a first N-type insulating through hole 102, wherein the first P-type insulating through hole 101 and the first N-type insulating through hole 102 are rectangular with the diameter of 35 μm being 25 μm;
then, coating negative photoresist on the first insulating layer 10, the first P-type insulating through hole 101 and the first N-type insulating through hole 102, exposing and developing to remove part of the photoresist, sequentially evaporating Al/Ti/Pt/Ti/Pt/Au/Ni/Pt/Ni metal by using an electron beam evaporation process, removing metal on the rest of the photoresist by using a blue film stripping process, and removing the photoresist to obtain a P-type preset bonding pad 111 and an N-type preset bonding pad 112 so as to form a preset bonding pad layer, wherein the distance between the preset bonding pad layer and an isolation groove is 45 mu m, and the distance between the P-type preset bonding pad 111 and the N-type preset bonding pad 112 is 30 mu m;
then, sequentially evaporating SiO on the surface of the first insulating layer 10 uncovered by the preset bonding pad layer by PECVD process 2 /SiN/SiO 2 /SiN/SiO 2 /SiN forms a second insulating layer 12 of a laminated structure, the laminated structure can effectively prevent the risk of failure of the flip LED chip caused by the invasion of external water vapor, then photoresist is coated on the surface of the second insulating layer 12, then part of the photoresist is removed by exposure and development, part of the second insulating layer 12 is exposed, then the exposed second insulating layer 12 is removed by utilizing a coupled inductance plasma etching process, a second P-type insulating through hole 121 and a second N-type insulating through hole 122 are formed, and the second P-type insulating through hole 121 and the second N-type insulating through hole 122 are rectangular with 35 mu m and 50 mu m;
finally, negative photoresist is coated on the surfaces of the second insulating layer 12, the second P-type insulating through hole 121 and the second N-type insulating through hole 122, then part of the photoresist is removed by exposure and development, then Al/Ti/Ni/Au metal is sequentially evaporated by an electron beam evaporation process, then metal on the residual photoresist is stripped by a blue film stripping process, then the residual photoresist is removed, and a plurality of P-type bonding pads 131 and N-type bonding pads 132 are obtained, so as to form a bonding pad layer, the P-type bonding pads 131 and the N-type bonding pads 132 are rectangular and have the same area, the rectangular size is 300 mu m, the distance between two adjacent bonding pads with the same polarity is 110 mu m, and the distance between the two adjacent P-type bonding pads 131 and the N-type bonding pad 132 is 200 mu m.
In summary, by applying different photolithography plates and exposing with different parameters twice in the process of the through hole lithography of the Bragg reflection layer, the application makes the projection circle diameter of the first surface 73 larger than the projection circle diameter of the second surface 74, the projection circle diameter of the first bottom surface 83 larger than the projection circle diameter of the second surface 74 and smaller than the projection circle diameter of the first surface 73, and the projection circle diameter of the second bottom surface 84 larger than the projection circle diameter of the first surface 73, so that the bump of the Bragg reflection layer 8 at the corner of the electrode layer can be removed, the formation of a cavity on the bump by the metal of the electric connection layer is avoided, the metal migration is avoided, the reliability of the light emitting diode chip is improved, and the service life of the light emitting diode chip is also improved.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.
Claims (9)
1. The flip-chip light-emitting diode chip is characterized by comprising a substrate, a first semiconductor layer, a current expansion layer, an electrode layer, a Bragg reflection layer and a second semiconductor layer which are sequentially arranged on the substrate;
the electrode layer is partially arranged on the current expansion layer, the Bragg reflection layer is arranged on the current expansion layer and the electrode layer, a plurality of Bragg reflection through holes are formed in the Bragg reflection layer, the Bragg reflection through holes are in a round table shape, a first bottom surface is arranged on one side, close to the electrode layer, of the Bragg reflection through holes, a second bottom surface is arranged on one side, far away from the electrode layer, of the Bragg reflection through holes, a first surface is arranged on one side, close to the current expansion layer, of the electrode layer, and a second surface is arranged on one side, far away from the current expansion layer, of the electrode layer;
the electrode layer comprises a P-type electrode and an N-type electrode, the Bragg reflection through holes comprise a P-type Bragg reflection through hole and an N-type Bragg reflection through hole, the P-type electrode and the P-type Bragg reflection through hole are correspondingly arranged, and the N-type electrode and the N-type Bragg reflection through hole are correspondingly arranged;
the projection of the first surface, the second surface, the first bottom surface and the second bottom surface on the substrate are concentric circles, the first surface and the second surface are circular, the projection circle diameter of the first surface is larger than that of the second surface, the projection circle diameter of the first bottom surface is larger than that of the second surface and smaller than that of the first surface, and the projection circle diameter of the second bottom surface is larger than that of the first surface;
the acute angle between the side surface of the electrode layer and the current expansion layer is not more than 25 degrees, the thickness of the electrode layer is not more than 0.5 mu m, the thickness range of the Bragg reflection layer is 3 mu m-6 mu m, the electrode layer is formed by combining Al, ti, pt, ni metal materials, and the Bragg reflection layer is formed bySeveral periodically alternately laminated SiO 2 And TiO 2 The composition is that the lamination period is 20-40.
2. The flip-chip light emitting diode chip of claim 1, wherein the first semiconductor layer comprises an N-type semiconductor layer, an active light emitting layer, a P-type semiconductor layer and a current blocking layer which are sequentially arranged on the substrate, the area of the P-type semiconductor layer is equal to the area of the active light emitting layer, the area of the P-type semiconductor layer is 70% -95% of the area of the N-type semiconductor layer, the area of the N-type semiconductor layer is 90% -95% of the area of the substrate, the projections of the current blocking layer and the P-type electrode on the substrate are concentric circles, and the area of the current blocking layer is 2% -5 times the area of the first surface.
3. The flip-chip light emitting diode chip of claim 2, wherein a recess is provided above the N-type semiconductor layer, the recess penetrates through the active light emitting layer and the P-type semiconductor layer, and the N-type electrode is disposed in the recess so that the N-type electrode communicates with the N-type semiconductor layer.
4. The flip-chip light emitting diode chip as set forth in claim 3, wherein a current spreading through hole is provided on the current spreading layer, a projection of the current spreading through hole and the recess on the substrate is concentric circles, and a projected circle diameter of the current spreading through hole is not smaller than a projected circle diameter of the recess.
5. The flip-chip light emitting diode chip of claim 1, wherein the second semiconductor layer comprises an electrical connection layer, a first insulating layer, a preset bonding pad layer, a second insulating layer, and a bonding pad layer sequentially disposed on the bragg reflection layer, the electrical connection layer is partially disposed on the bragg reflection layer, the first insulating layer is disposed on the electrical connection layer and the bragg reflection layer, the preset bonding pad layer is partially disposed on the first insulating layer, and the second insulating layer is disposed on the preset bonding pad layer and the first insulating layer.
6. The flip-chip light emitting diode chip of claim 5, wherein the electrical connection layer comprises a P-type electrical connection layer and an N-type electrical connection layer, the P-type electrical connection layer is connected to the P-type electrode through a P-type bragg reflection via, the N-type electrical connection layer is connected to the N-type electrode through an N-type bragg reflection via, a first P-type insulation via and a first N-type insulation via are provided on the first insulation layer, the first P-type insulation via is provided above the P-type electrical connection layer, and the first N-type insulation via is provided above the N-type electrical connection layer.
7. The flip-chip light emitting diode chip of claim 6, wherein the preset bonding pad layer comprises a P-type preset bonding pad and an N-type preset bonding pad, the P-type preset bonding pad is communicated with the P-type electric connection layer through a first P-type insulation through hole, the N-type preset bonding pad is communicated with the N-type electric connection layer through a first N-type insulation through hole, and a distance between two adjacent P-type preset bonding pads and the N-type preset bonding pad ranges from 20 μm to 50 μm.
8. The flip-chip light emitting diode chip of claim 7, wherein the second insulating layer comprises a second P-type insulating via and a second N-type insulating via, the second P-type insulating via is disposed above the P-type preset pad, the second N-type insulating via is disposed above the N-type preset pad, the bonding pad layer comprises a P-type bonding pad and an N-type bonding pad, the P-type bonding pad communicates with the P-type preset pad through the second P-type insulating via, and the N-type bonding pad communicates with the N-type preset pad through the second N-type insulating via.
9. A method of manufacturing a flip-chip light emitting diode chip as claimed in any one of claims 1 to 8, comprising the steps of:
providing a substrate, and depositing a first semiconductor layer on the substrate;
depositing a current spreading layer on the first semiconductor layer;
depositing a P-type electrode and an N-type electrode on the current expansion layer to form an electrode layer;
forming a Bragg reflection layer on the current expansion layer and the electrode layer by utilizing an electron beam evaporation process;
a P-type Bragg reflection through hole and an N-type Bragg reflection through hole are obtained on the Bragg reflection layer by utilizing a plasma etching process so as to form the Bragg reflection through hole;
depositing a second semiconductor layer on the Bragg reflection layer and the Bragg reflection through hole;
the step of forming the Bragg reflection through hole by using a plasma etching process to obtain the P-type Bragg reflection through hole and the N-type Bragg reflection through hole on the Bragg reflection layer comprises the following steps:
dropping photoresist on the surface of the Bragg reflection layer by using a photoresist homogenizing machine, then rotating the photoresist at a high speed for the first time by using a spin coating method, then rotating the photoresist at a high speed for the second time, so that the thickness of the photoresist is 8-12 mu m, then performing first exposure by using a first photoetching plate, wherein the diameter of a light-transmitting area on the first photoetching plate is equal to the projected circle diameter of a first bottom surface, then performing second exposure by using a second photoetching plate, the diameter of the light-transmitting area on the second photoetching plate is equal to the projected circle diameter of a second bottom surface, then performing development by using an alcohol or benzene or phenol or a combined developer of the alcohols or phenols, developing for three times, developing for 10-15S each time by using a developer, then heating and baking the photoresist from the bottom surface of the substrate by using a hot plate, then baking the photoresist again by using an oven, so as to form a photoresist pattern on the Bragg reflection layer, exposing part of the Bragg reflection layer, and then etching the exposed Bragg reflection layer by using coupling inductance plasma to obtain a P-type Bragg reflection through hole and an N-type Bragg reflection through hole to form the Bragg reflection through hole;
the first high-speed rotation speed is 1500-2000r/min, the first high-speed rotation time is 10-15S, the second high-speed rotation speed is 4000-4500r/min, the second high-speed rotation time is 10-15S, the first exposure energy is not less than 1500mj/cm, the light intensity wavelength of the first exposure is 300-340 nm, the second exposure energy is 500 mj/cm-800 mj/cm, the light intensity wavelength of the second exposure is 350-380 nm, the hot plate temperature is 150-160 ℃, the hot plate baking time is 100-150S, the oven temperature is 120-140 ℃, and the oven baking time is 45-55 min;
the acute angle between the side surface of the electrode layer and the current expansion layer is not more than 25 degrees, the thickness of the electrode layer is not more than 0.5 mu m, the thickness range of the Bragg reflection layer is 3 mu m-6 mu m, the electrode layer is formed by combining Al, ti, pt, ni metal materials, and the Bragg reflection layer is formed by a plurality of periodically and alternately laminated SiO 2 And TiO 2 The composition is that the lamination period is 20-40.
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| CN118588824B (en) * | 2024-07-31 | 2024-10-25 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
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