CN116466785A - LDO circuit with low noise and high PSR - Google Patents
LDO circuit with low noise and high PSR Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to an LDO circuit with low noise and high PSR, which comprises a reference module and an LDO main loop module. Wherein the reference module generates accurate reference current and bias voltage, the reference current generates V required by the LDO main loop after passing through the off-chip RC filter network REF And the reference voltage is generated by the reference module, and the bias voltage provides voltage bias for the LDO main loop module. The error amplifier of the LDO main loop module adopts a BJT type rail-to-rail error amplifier, and the output of the error amplifier is V EA_OUT A buffer stage is connected in the rear; the output of the buffer stage is V buf_OUT An adaptive PSR enhancement module is connected in series. The whole structure adopts a unit gain negative feedback mode, so that noise of a resistor voltage division network of a traditional LDO structure is eliminated, and noise of a reference module and high-frequency power supply ripples are filtered by an off-chip RC filter network. The input pair tube of the on-track to-track error amplifier adopts the depletion stack tube technology, realizes low voltage difference and simultaneously remarkably improves the power supply ripple suppression performance of the low frequency band in the system.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an LDO circuit with low noise and high PSR.
Background
The LDO is one of the kinds of power management chips, and can convert a dc voltage into another fixed dc voltage for output in a certain load range. Compared with a switching converter, the LDO has the advantages of being outstanding in noise isolation and ripple suppression, low in cost, easy to integrate, simple to control, few in peripheral elements and stable in output voltage, is often used for supplying power to an analog or radio frequency module sensitive to on-chip noise, so that larger voltage ripple needs to be eliminated, and in addition, the device noise of the LDO circuit is as low as possible to output a clean voltage.
The traditional LDO noise sources are mainly a reference, an error amplifier and a resistor divider network for setting the output voltage, and the reference and the error amplifier also affect the PSR performance. In particular, for LDOs with a wide load range, an adaptive bias needs to be added to compensate for the frequency, but this results in an excessive range of gate impedance of the power tube, so that the PSR effect of raising the middle and high frequencies is not good by using the conventional feedforward ripple cancellation method.
Disclosure of Invention
Aiming at the problems, the invention provides an LDO circuit with low noise and high PSR. The aim is to solve the PSR deterioration problem of LDO under wide load condition and realize low noise of the whole circuit.
The technical scheme of the invention is as follows:
an LDO circuit with low noise and high PSR comprises a reference module and an LDO main body circuit module;
the reference module is used for generating accurate reference current, and the accurate reference current is output to the LDO main loop module as reference voltage V after flowing through the off-chip RC filter network REF . Input is power supply VIN and output is flow through R SET Reference voltage V generated by resistor REF First bias V B1 Second bias V B2 PMOS common grid tube bias V BP NMOS common grid tube bias V BN Switching tube bias V SW The method comprises the steps of carrying out a first treatment on the surface of the The reference block also generates a bias voltage,providing voltage bias for the LDO main loop module.
The reference module includes a reference current bias voltage generation module and an RC filter network. Wherein the reference current bias voltage generation module is used for generating a reference current and a bias voltage V B1 ，V B2 ，V BP ，V BN V (V) SW . The RC filter network is formed by R SET Resistance sum C SET Capacitor structure, R SET Resistance determination output voltage V REF ，C SET The capacitor can filter out high-frequency noise and improve the high-frequency power supply rejection ratio.
The LDO main loop module is used for outputting a direct-current voltage VO with low noise and high PSR. Input is power supply VIN, V REF 、V B1 、V B2 、V BP 、V BN V (V) SW Output is V O . Wherein V is REF An inverting terminal connected to the rail-to-rail error amplifier module; v (V) B1 Providing bias for the rail-to-rail error amplifier and adaptive PSR enhancement; v (V) B2 Providing a bias for the buffer stage; v (V) BP 、V BN Providing a bias for the rail-to-rail error amplifier; v (V) SW Control switch tube M 3 。
The LDO main loop module comprises a rail-to-rail error amplifier, a buffer stage, a self-adaptive PSR enhancement circuit and a power stage; the rail-to-rail error amplifier comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a first depletion type NMOS laminated tube M dep1 Second depletion type NMOS laminated pipe M dep2 Third depletion type NMOS laminated pipe M dep3 A first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, and an eighteenth transistor Q18; the source electrode of the first MOS tube M1 is connected with a power supply, and the grid electrode thereof is connected with a first bias voltage V B1 Its drain electrode is connected with the first depletion type NMOS laminated pipe M dep1 Gate and drain of (a); the source electrode of the second MOS tube M2 is connected with the power supply, and the grid electrode thereof is connected with the first bias voltage V B1 The drain electrode of the third MOS transistor M3 is connected with the emitter electrode of the third triode Q3, the emitter electrode of the fourth triode Q4 and the source electrode of the third MOS transistor M3; first depletion type NMOS laminated pipe M dep1 Is connected with the second depletion type NMOS laminated pipe M dep2 Gate and third depletion type NMOS laminate tube M dep3 Gate of first depletion type NMOS laminated pipe M dep1 The source electrode of the first triode Q1 is connected with the base electrode of the third triode Q3; second depletion type NMOS laminated pipe M dep2 The drain electrode of the second depletion type NMOS laminated tube M is connected with the collector electrode of the ninth triode Q9 and the source electrode of the sixth MOS tube M6 dep2 The source electrode of the first triode Q1 is connected with the collector electrode of the first triode Q1; third depletion type NMOS laminated pipe M dep3 The drain electrode of the thirteenth electrode tube Q10 and the source electrode of the seventh MOS tube M7, the third depletion type NMOS laminated tube M dep3 The source electrode of the second triode Q2 is connected with the collector electrode of the second triode Q2; the emitter of the first triode Q1 is connected with the collector of the fifth triode Q5 and the emitter of the second triode Q2; the collector electrode of the third triode Q3 is connected with the source electrode of the fourth MOS tube M4 and the collector electrode of the seventh triode Q7; the base of the fourth triode Q4 is connected with the base of the second triode Q2 and the reference voltage V REF The method comprises the steps of carrying out a first treatment on the surface of the The collector electrode of the fourth triode Q4 is connected with the source electrode of the fifth MOS tube M5 and the collector electrode of the eighth triode Q8; the grid electrode of the third MOS tube M3 is connected with the bias voltage V of the switch tube SW The drain electrode of the third MOS transistor M3 is connected with the base electrode of the fifth triode, the collector electrode and the base electrode of the sixth triode Q6, and the emitter electrode of the fifth triode Q5 and the emitter electrode of the sixth triode Q6 are grounded; the emitter of the ninth triode Q9 is connected with a power supply, and the base of the ninth triode Q9 is connected with the base of the tenth triode Q10 and the emitter of the eleventh triode Q11; the base electrode of the eleventh triode Q11 is connected with the drain electrode of the sixth MOS tube M6, the emitter electrode of the twelfth triode Q12 and the collector electrode of the thirteenth triode Q13, and the collector electrode of the eleventh triode Q11 is grounded; the grid electrode of the sixth MOS tube M6 is connected with the grid electrode of the seventh MOS tube M7 in parallel with the PMOS common grid tube bias voltage V BP The method comprises the steps of carrying out a first treatment on the surface of the The base of the twelfth transistor Q12 is connected with the base and collector of the eighteenth transistor Q18 and the drain of the ninth MOS transistor M9The collector of the twelfth triode Q12 is connected with the emitter of the thirteenth triode Q13, the drain of the fourth MOS tube M4, the base of the seventh triode Q7 and the base of the eighth triode Q8; the base electrode of the thirteenth triode Q13 is connected with the drain electrode of the eighth MOS tube M8, the base electrode and the collector electrode of the fifteenth triode Q15; the grid electrode of the fourth MOS tube M4 is connected with the grid electrode of the fifth MOS tube in parallel with the bias voltage V of the NMOS common grid tube BN The method comprises the steps of carrying out a first treatment on the surface of the The emitter of the seventh triode Q7 and the emitter of the eighth triode Q8 are grounded; the source electrode of the eighth MOS tube M8 is connected with the power supply, the grid electrode thereof is connected with the first bias voltage V B1 The method comprises the steps of carrying out a first treatment on the surface of the The emitter junction of the fifteenth triode Q15 is connected with the collector and the base of the fourteenth triode Q14, and the emitter of the fourteenth triode Q14 is grounded; the emitter of the sixteenth triode Q16 is connected with a power supply, and the collector and the base of the sixteenth triode Q16 are connected with the emitter of the seventeenth triode Q17; the collector and the base of the seventeenth triode Q17 are connected with the emitter of the eighteenth triode Q18; the grid electrode of the ninth MOS tube M9 is connected with the second bias voltage V B2 The source electrode is grounded; the drain electrode of the seventh MOS tube M7 is connected with the drain electrode of the fifth MOS tube M5 and is used as the output end of the rail-to-rail error amplifier;
the input end of the buffer stage is connected with the output end of the rail-to-rail error amplifier, the output end of the buffer stage is connected with the input end of the self-adaptive PSR enhancement circuit, and the bias voltage of the buffer stage is the second bias voltage V B2 ；
The self-adaptive PSR enhancement circuit comprises a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a nineteenth triode Q19 and a twentieth triode Q20; the source electrode of the tenth MOS transistor M10 is connected with the power supply, and the grid electrode thereof is connected with the first bias voltage V B1 The drain electrode of the drain electrode is connected with the drain electrode and the grid electrode of the eleventh MOS tube M11, the grid electrode of the twelfth MOS tube M12 and the drain electrode of the fourteenth MOS tube M14; the source electrode of the eleventh MOS tube M11 is grounded; the source electrode of the fourteenth MOS tube M14 is connected with a power supply, and the grid electrode of the fourteenth MOS tube M14 is connected with the drain electrode of the thirteenth MOS tube M13, the emitter electrode of the nineteenth triode Q19, the grid electrode and the drain electrode of the fifteenth MOS tube M15 and the collector electrode of the twenty-eighth triode Q20; the thirteenth MOS transistor M13 has its source connected to the power supply and its gate connected to the first bias voltage V B1 The method comprises the steps of carrying out a first treatment on the surface of the The base of nineteenth triode Q19 is connected with the output end of buffer stage and its collectorThe electrode is connected with the base electrode of the twenty-third triode Q20 and the drain electrode of the twelfth MOS tube M12; the source electrode of the twelfth MOS transistor M12 and the emitter electrode of the twenty-third transistor Q20 are grounded; the drain electrode of the fifteenth MOS tube M15 is the output end of the self-adaptive PSR enhancement circuit;
the power stage consists of a PMOS power tube, an off-chip capacitor COUT, an equivalent series resistor RESR, a load resistor RL and a load capacitor CL, wherein the source electrode of the PMOS power tube is connected with a power supply, and the grid electrode of the PMOS power tube is connected with the output of the self-adaptive PSR enhancement circuit; the drain of the PMOS power tube is the output end of the LDO circuit and is connected with one end of the equivalent series resistance RESR, one end of the load capacitor CL and the first depletion type NMOS laminated tube M dep1 A source of a first transistor Q1 and a base of a first transistor Q1; the other end of the equivalent series resistance RESR is grounded after passing through the off-chip capacitor COUT, and the other end of the load capacitor CL is grounded.
The rail-to-rail error amplifier adopts a folded cascode structure, obtains better PSR performance of a circuit at low frequency with higher low-frequency gain, stacks a depletion type NMOS tube on the collector of an NPN input pair tube, and can reduce the influence of the NPN input pair tube collector on base noise while guaranteeing low pressure difference; the buffer stage is composed of a source follower and is used for raising the direct-current working point output by the rail-to-rail error amplifier so that the direct-current working point can provide higher gain in the full load range; the self-adaptive PSR enhancement circuit is used for ensuring loop stability in a wide load range and enhancing PSR performance of a medium-high frequency band; the power stage is composed of PMOS power tube and off-chip capacitor C OUT Equivalent series resistance R ESR Load resistor R L And a load capacitance C L Constitution, wherein R is ESR Resistor and off-chip capacitor C OUT The generated zero is used for compensating the EA output pole, so that only one pole exists in the GBW, and good frequency response characteristic is obtained.
The beneficial effects of the invention are as follows: the invention provides an LDO circuit with low noise and high PSR. The circuit eliminates the contribution of the resistor divider network to noise in the traditional LDO through a unit gain negative feedback structure, and the structure can ensure that the loop gain, the frequency response and the bandwidth do not change along with the output voltage, so that the noise, the PSR and the transient performance do not change along with the output voltage. In addition, the PSR deterioration problem commonly generated by the BJT as an input pair tube is solved, and the PSR is greatly improved in the low-medium frequency band. The invention also utilizes the self-adaptive PSR enhancement technology, so that the PSR performance of the LDO circuit is improved to a certain extent in a wide load range.
Drawings
FIG. 1 is a system block diagram of an LDO circuit with low noise and high PSR according to the present invention.
FIG. 2 is a block diagram of an LDO rail-to-rail error amplifier of an LDO circuit with low noise and high PSR.
FIG. 3 is a schematic diagram showing the LDO adaptive PSR enhancement structure of the LDO circuit with low noise and high PSR.
FIG. 4 is a graph showing a PSR characteristic comparison of an LDO circuit with low noise and high PSR with or without an input multilayer pipe under a 500mA load.
FIG. 5 is a PSR characteristic comparison of the LDO circuit with low noise and high PSR provided by the invention, with or without an adaptive ripple feedforward circuit under a 500mA load.
FIG. 6 is a graph showing the output noise spectrum of the LDO circuit with low noise and high PSR under 500mA load.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. The described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is noted that in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The system block diagram of the LDO circuit with low noise and high PSR provided by the invention is shown in fig. 1, and comprises a reference module and an LDO main loop module. Integral bodyThe structure adopts a unit gain negative feedback structure, does not need a resistor voltage dividing network to determine output voltage, and eliminates noise of the resistor voltage dividing network with the traditional LDO structure. Wherein the reference module will generate accurate reference current and bias voltage, the reference current will generate V needed by LDO main loop after passing through the off-chip RC filter network REF Reference voltage for determining output voltage V of LDO O The bias voltage generated by the reference module provides voltage bias for the LDO main loop module; noise and high frequency power supply ripple contained in the reference are filtered by the RC filter network. The error amplifier of the LDO main loop module adopts a BJT type rail-to-rail cascode error amplifier so as to meet the requirements of high gain and low noise in a wide load range. When V is O ＜V REF1 When the PNP input geminate transistors work, the NPN input geminate transistors are cut off; when V is O ＞V REF2 When the NPN input geminate transistors work, the PNP input geminate transistors are cut off; when V is REF1 <V O <V REF2 When two pairs of input pair tubes work, thereby meeting the requirement of smooth switching of the working states of the two pairs of input pair tubes when the output voltage changes in a wide range, wherein V REF1 ，V REF2 Is R SET The reference voltage value is generated and V REF1 <V REF2 . The depletion type NMOS tube is adopted as a laminated tube, ripple waves are shielded, cleaner voltage is obtained at the collector electrodes of the NPN input pair, and PSR of the middle-low frequency band is remarkably improved. The use of depletion tubes is mainly to meet the low pressure differential requirements. The self-adaptive PSR enhancement circuit can perform frequency compensation on one hand so as to solve the stability problem caused by overlarge output pole change in a wide load range; on the other hand, PSR performance of medium and high frequency is improved. The circuit structure and connection relation of each module are described below, respectively.
One implementation of a rail-to-rail error amplifier is given in fig. 2. Input pair tube Q 1 ，Q 3 The base electrode of the power tube and the drain electrode of the power tube are output V O Are connected together. Input pair tube Q 2 And Q 4 Is connected with the base electrode of the reference module to output voltage V REF 。Q 3 ，Q 4 Emitter and M of (2) 2 Drain electrode of (d) and switching tube M 3 Is connected to the source ofTogether, M 2 Fixed bias V of grid electrode connected with output of reference module B1 ，M 2 A tail current source is provided for the rail-to-rail error amplifier. M is M 3 Drain and Q of (2) 6 Collector, base, Q 5 Is connected together with the base electrode of Q 5 And Q 6 Forming a current mirror for NPN input pair Q 1 And Q 2 Providing a tail current. Wherein Q is 6 Is diode connected. Q (Q) 1 ，Q 2 The collector electrodes of (a) are respectively connected with the depletion tube M dep2 ，M dep3 Source of M dep2 ，M dep3 Is a depletion type NMOS laminated pipe. M is M dep2 ，M dep3 Is connected with the grid of the current source M 1 M short-circuited with gate drain dep1 Biasing is performed. Wherein M is 1 Is connected with a fixed bias V B1 ，M dep1 Is connected with the output voltage V O 。M dep2 ，M dep3 Is not equal to the drain terminal V of C1 And V C2 Respectively connected to PMOS common grid tube M 6 And M 7 Source of (c) and Q 9 And Q 10 Collector, Q of 1 ，Q 2 ，Q 9 ，Q 10 ，M 6 And M 7 Forms a folding cascode structure when the NPN input pair tube works, wherein Q 9 ，Q 10 Is a current mirror. Q (Q) 3 ，Q 4 Collector V of (2) C3 And V C4 Respectively connected to NMOS common grid tube M 4 And M 5 Source of (c) and Q 7 And Q 8 Collector, Q of 3 ，Q 4 ，Q 7 ，Q 9 ，M 4 And M 5 Forms a folding common-source common-gate structure when PNP input pair tubes work, Q 7 ，Q 8 Is a current mirror. Q (Q) 10 ，Q 11 ，Q 12 ，Q 16 ，Q 17 ，Q 18 Form a transconductance linear loop of Q 9 And Q 10 Providing a bias current. Q (Q) 10 Is connected with Q by the base electrode of (2) 11 Emitter, Q of 11 Is connected with Q by the base electrode of (2) 12 Is provided. Q (Q) 16 ，Q 17 ，Q 18 PNP with three diodes connected, three BJTs connected in series, Q 18 Collector of (d), current source M 9 Drain electrode of (c) and Q 12 Is connected with the base electrode of M 9 Is of fixed bias V B2 。Q 8 ，Q 13 ，Q 14 ，Q 15 Form a transconductance linear loop of Q 7 And Q 8 Providing a bias current. Q (Q) 13 Emitter junction Q of (2) 8 Is formed on the base of the substrate. Q (Q) 14 And Q 15 For diode-connected NPN, two BJTs are connected in series, Q 15 Collector of (d), current source M 8 Drain electrode of (c) and Q 13 Is connected with the base electrode of M 8 Is of fixed bias V B1 。M 5 And M 7 The drain terminal is used as the output terminal of the rail-to-rail error amplifier.
One implementation of an adaptive PSR enhancement structure is given as fig. 3. Wherein M is 10 ，M 11 ，M 12 ，M 13 ，M 14 ，M 15 ，Q 19 ，Q 20 Together forming an adaptive ripple PSR enhancement circuit, M 15 Is an adaptive bias. M is M 14 Scaling down M 15 Current of M 10 And M 13 Is a constant current source M 11 And M 12 Is a current mirror, M 11 The grid and the drain are short-circuited. M is M 13 Drain electrode of (C) and M 15 Gate and drain of (1), Q 19 Emitter, Q of 20 The collector of (C) and the grid of the power tube are connected together, M 13 Gate of (2) is connected with V B1 Fixed bias, M 14 Gate and M of (2) 15 Are joined together, M 14 Drain electrode of M 10 Drain electrode of M 11 Gate and M of (2) 12 Is connected with the grid electrode of M 10 Is of fixed bias V B1 . Power tube M POWER Is output V O . By means of the adaptive PSR enhancing circuit, it is ensured that the effect of a high PSR is achieved under full load conditions.
Fig. 4, fig. 5 and fig. 6 only represent simulation results under a certain simulation condition, and the structure proposed by the present patent still has a corresponding effect under the condition of changing the simulation conditions and circuit parameters, so that changing the simulation conditions and circuit parameters is still within the protection scope of the present invention.
Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations are still within the scope of the present disclosure.
Claims (1)
1. The LDO circuit with low noise and high PSR is characterized by comprising a reference module and an LDO main loop module;
the reference module is used for generating reference current and bias voltage, and the reference current is output to the LDO main loop module as reference voltage V after passing through the RC filter network REF The method comprises the steps of carrying out a first treatment on the surface of the The bias voltage includes a first bias voltage V B1 Second bias voltage V B2 PMOS common grid tube bias voltage V BP NMOS common grid tube bias voltage V BN Switching tube bias voltage V SW ；
The LDO main loop module comprises a rail-to-rail error amplifier, a buffer stage, an adaptive PSR enhancement circuit and a power stage; the rail-to-rail error amplifier comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a first depletion type NMOS laminated tube M dep1 Second depletion type NMOS laminated pipe M dep2 Third depletion type NMOS laminated pipe M dep3 A first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, and an eighteenth transistor Q18; the source electrode of the first MOS tube M1 is connected with a power supply, and the grid electrode thereof is connected with a first bias voltage V B1 Its drain electrode is connected with the first depletion type NMOS laminated pipe M dep1 Gate and drain of (a); the source electrode of the second MOS tube M2 is connected with the power supply, and the grid electrode thereof is connected with the first bias voltage V B1 The drain electrode of the third MOS transistor M3 is connected with the emitter electrode of the third triode Q3, the emitter electrode of the fourth triode Q4 and the source electrode of the third MOS transistor M3; first depletion type NMOS laminated pipe M dep1 The gate electrode of (2) is connected with the second depletion typeNMOS laminated pipe M dep2 Gate and third depletion type NMOS laminate tube M dep3 Gate of first depletion type NMOS laminated pipe M dep1 The source electrode of the first triode Q1 is connected with the base electrode of the third triode Q3; second depletion type NMOS laminated pipe M dep2 The drain electrode of the second depletion type NMOS laminated tube M is connected with the collector electrode of the ninth triode Q9 and the source electrode of the sixth MOS tube M6 dep2 The source electrode of the first triode Q1 is connected with the collector electrode of the first triode Q1; third depletion type NMOS laminated pipe M dep3 The drain electrode of the thirteenth electrode tube Q10 and the source electrode of the seventh MOS tube M7, the third depletion type NMOS laminated tube M dep3 The source electrode of the second triode Q2 is connected with the collector electrode of the second triode Q2; the emitter of the first triode Q1 is connected with the collector of the fifth triode Q5 and the emitter of the second triode Q2; the collector electrode of the third triode Q3 is connected with the source electrode of the fourth MOS tube M4 and the collector electrode of the seventh triode Q7; the base of the fourth triode Q4 is connected with the base of the second triode Q2 and the reference voltage V REF The method comprises the steps of carrying out a first treatment on the surface of the The collector electrode of the fourth triode Q4 is connected with the source electrode of the fifth MOS tube M5 and the collector electrode of the eighth triode Q8; the grid electrode of the third MOS tube M3 is connected with the bias voltage V of the switch tube SW The drain electrode of the third MOS transistor M3 is connected with the base electrode of the fifth triode, the collector electrode and the base electrode of the sixth triode Q6, and the emitter electrode of the fifth triode Q5 and the emitter electrode of the sixth triode Q6 are grounded; the emitter of the ninth triode Q9 is connected with a power supply, and the base of the ninth triode Q9 is connected with the base of the tenth triode Q10 and the emitter of the eleventh triode Q11; the base electrode of the eleventh triode Q11 is connected with the drain electrode of the sixth MOS tube M6, the emitter electrode of the twelfth triode Q12 and the collector electrode of the thirteenth triode Q13, and the collector electrode of the eleventh triode Q11 is grounded; the grid electrode of the sixth MOS tube M6 is connected with the grid electrode of the seventh MOS tube M7 in parallel with the PMOS common grid tube bias voltage V BP The method comprises the steps of carrying out a first treatment on the surface of the The base electrode of the twelfth triode Q12 is connected with the base electrode and the collector electrode of the eighteenth triode Q18 and the drain electrode of the ninth MOS tube M9, and the collector electrode of the twelfth triode Q12 is connected with the emitter electrode of the thirteenth triode Q13, the drain electrode of the fourth MOS tube M4, the base electrode of the seventh triode Q7 and the base electrode of the eighth triode Q8; the base electrode of the thirteenth triode Q13 is connected with the drain electrode of the eighth MOS tube M8, the base electrode and the collector electrode of the fifteenth triode Q15; the grid electrode of the fourth MOS tube M4 is connected with the grid electrode of the fifth MOS tube in parallel with the bias voltage V of the NMOS common grid tube BN The method comprises the steps of carrying out a first treatment on the surface of the The emitter of the seventh triode Q7 and the emitter of the eighth triode Q8 are grounded; the source electrode of the eighth MOS tube M8 is connected with the power supply, the grid electrode thereof is connected with the first bias voltage V B1 The method comprises the steps of carrying out a first treatment on the surface of the The emitter junction of the fifteenth triode Q15 is connected with the collector and the base of the fourteenth triode Q14, and the emitter of the fourteenth triode Q14 is grounded; the emitter of the sixteenth triode Q16 is connected with a power supply, and the collector and the base of the sixteenth triode Q16 are connected with the emitter of the seventeenth triode Q17; the collector and the base of the seventeenth triode Q17 are connected with the emitter of the eighteenth triode Q18; the grid electrode of the ninth MOS tube M9 is connected with the second bias voltage V B2 The source electrode is grounded; the drain electrode of the seventh MOS tube M7 is connected with the drain electrode of the fifth MOS tube M5 and is used as the output end of the rail-to-rail error amplifier;
the input end of the buffer stage is connected with the output end of the rail-to-rail error amplifier, the output end of the buffer stage is connected with the input end of the self-adaptive PSR enhancement circuit, and the bias voltage of the buffer stage is the second bias voltage V B2 ；
The self-adaptive PSR enhancement circuit comprises a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a nineteenth triode Q19 and a twentieth triode Q20; the source electrode of the tenth MOS transistor M10 is connected with the power supply, and the grid electrode thereof is connected with the first bias voltage V B1 The drain electrode of the drain electrode is connected with the drain electrode and the grid electrode of the eleventh MOS tube M11, the grid electrode of the twelfth MOS tube M12 and the drain electrode of the fourteenth MOS tube M14; the source electrode of the eleventh MOS tube M11 is grounded; the source electrode of the fourteenth MOS tube M14 is connected with a power supply, and the grid electrode of the fourteenth MOS tube M14 is connected with the drain electrode of the thirteenth MOS tube M13, the emitter electrode of the nineteenth triode Q19, the grid electrode and the drain electrode of the fifteenth MOS tube M15 and the collector electrode of the twenty-eighth triode Q20; the thirteenth MOS transistor M13 has its source connected to the power supply and its gate connected to the first bias voltage V B1 The method comprises the steps of carrying out a first treatment on the surface of the The base electrode of the nineteenth triode Q19 is connected with the output end of the buffer stage, and the collector electrode of the nineteenth triode Q19 is connected with the base electrode of the twenty-second triode Q20 and the drain electrode of the twelfth MOS tube M12; the source electrode of the twelfth MOS transistor M12 and the emitter electrode of the twenty-third transistor Q20 are grounded; the drain electrode of the fifteenth MOS tube M15 is the output end of the self-adaptive PSR enhancement circuit;
the power stage consists of a PMOS power tube, an off-chip capacitor COUT, an equivalent series resistance RESR, a load resistance RL and a load capacitorCL is formed, the source electrode of the PMOS power tube is connected with a power supply, and the grid electrode of the PMOS power tube is connected with the output of the self-adaptive PSR enhancement circuit; the drain of the PMOS power tube is the output end of the LDO circuit and is connected with one end of the equivalent series resistance RESR, one end of the load capacitor CL and the first depletion type NMOS laminated tube M dep1 A source of a first transistor Q1 and a base of a first transistor Q1; the other end of the equivalent series resistance RESR is grounded after passing through the off-chip capacitor COUT, and the other end of the load capacitor CL is grounded.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117148911A (en) * | 2023-11-01 | 2023-12-01 | 成都芯翼科技有限公司 | Low-noise LDO circuit |
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| CN101841309A (en) * | 2010-06-07 | 2010-09-22 | 西安交通大学 | Rail-to-rail operational amplifier |
| US20160334818A1 (en) * | 2015-05-15 | 2016-11-17 | Analog Devices Global | Circuits and techniques including cascaded ldo regulation |
| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
| CN115617112A (en) * | 2022-09-26 | 2023-01-17 | 北京时代民芯科技有限公司 | LDO circuit with low noise and high PSRR |
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| CN101841309A (en) * | 2010-06-07 | 2010-09-22 | 西安交通大学 | Rail-to-rail operational amplifier |
| US20160334818A1 (en) * | 2015-05-15 | 2016-11-17 | Analog Devices Global | Circuits and techniques including cascaded ldo regulation |
| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117148911A (en) * | 2023-11-01 | 2023-12-01 | 成都芯翼科技有限公司 | Low-noise LDO circuit |
| CN117148911B (en) * | 2023-11-01 | 2024-01-30 | 成都芯翼科技有限公司 | Low-noise LDO circuit |
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