CN116431422B - Access verification system, method and related equipment for multi-simulation environment - Google Patents
Access verification system, method and related equipment for multi-simulation environment Download PDFInfo
- Publication number
- CN116431422B CN116431422B CN202310704831.6A CN202310704831A CN116431422B CN 116431422 B CN116431422 B CN 116431422B CN 202310704831 A CN202310704831 A CN 202310704831A CN 116431422 B CN116431422 B CN 116431422B
- Authority
- CN
- China
- Prior art keywords
- information
- access
- random
- memory
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012795 verification Methods 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000004088 simulation Methods 0.000 title claims abstract description 23
- 230000004044 response Effects 0.000 claims abstract description 50
- 230000003993 interaction Effects 0.000 claims abstract description 46
- 238000013507 mapping Methods 0.000 claims abstract description 25
- 230000006870 function Effects 0.000 claims abstract description 12
- 230000002452 interceptive effect Effects 0.000 claims abstract description 12
- 230000007246 mechanism Effects 0.000 claims description 11
- 238000012360 testing method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000012536 storage buffer Substances 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention is suitable for the technical field of multi-core access verification environments, and particularly relates to an access verification system, method and related equipment for a multi-simulation environment, wherein the system comprises the following components: the random generator module is used for generating random information containing access requests according to the random seeds; the request list module is used for caching the random information into a request list; comparing the response information with the random information, checking overtime, and outputting a verification result; the interaction control module is used for converting the random information into access information corresponding to the interface of the multi-core access subsystem from the request list and sending the access information to the multi-core access subsystem; receiving response information of corresponding access information responded by the multi-core access subsystem and forwarding the response information to the request list module; and the interactive mapping pool module is used for providing mapping functions for the interactive control module and the request list module. According to the invention, the requests of different time sequence scenes of the corresponding access subsystem are generated by configuring different verification modes and parameters, so that the verification coverage rate is improved.
Description
Technical Field
The invention is suitable for the technical field of multi-core access verification environments, and particularly relates to an access verification system, method and related equipment for a multi-simulation environment.
Background
With the increasing performance requirements of the multi-core general superscalar processor, under the Feng Nuoer Mann computer architecture, the existence of a private primary data cache (dcache) of each core greatly reduces load-to-use (load-to-use), and the occurrence of secondary cache and tertiary cache also reduces the possibility of accessing a later-stage memory with slower speed after a primary data cache miss to a certain extent, but the collaborative complexity of the multi-stage cache also presents higher challenges for multi-core data sharing. Therefore, various multi-core cache consistency protocols are realized in the industry, and the multi-core cache consistency protocols are used for maintaining the problem of data sharing among multiple cores so as to ensure the completeness of data access. On the other hand, out-of-order execution of the core memory instructions also greatly helps CPU performance, so that the memory subunit (Load Store Unit) is also relatively complex to implement, so as to ensure that the parallel access to the cache subsystem is maximally implemented and avoid hazards (hard).
However, the out-of-order asynchronous scenario of the memory subsystem (including memory subunits, level-of-cache and multi-core cache coherency protocols) is very numerous, and the implementation of the true register translation stage (Register Transfer Level) is inevitably subject to error. Therefore, how to perform complete function verification on the complex out-of-order access subsystem with the superscalar amount is a problem to be solved in the current industry.
Disclosure of Invention
The invention provides a memory access verification system, a memory access verification method and related equipment for a multi-simulation environment, and aims to solve the problem that complete function verification cannot be performed on a complex out-of-order memory access subsystem in the prior art.
In a first aspect, the present invention provides a memory verification system for a multi-emulation environment, the memory verification system being configured to verify a multi-core memory subsystem, the multi-core memory verification system comprising:
the random generator module is used for generating random information containing access requests according to the random seeds;
the request list module is used for caching the random information into a request list; comparing the response information with the random information, and outputting a verification result, wherein the response information is sent out by the multi-core access subsystem;
the interaction control module is used for converting the random information into access information corresponding to an interface format of the multi-core access subsystem from the request list and sending the access information to the multi-core access subsystem; the multi-core access subsystem is also used for receiving the response information corresponding to the access information and responding to the multi-core access subsystem and forwarding the response information to the request list module;
and the interaction mapping pool module is used for providing mapping functions for the interaction control module and the request list module.
Further, the access verification system for the multi-simulation environment is divided into a self-checking mode and a non-self-checking mode according to the access verification mode, wherein:
the random generator module in the self-checking mode does not allow overlapping of access addresses of different access requests generated by the random seed;
the random generator module in the non-self-checking mode allows overlapping according to the memory access address of the memory access request generated by the random seed.
Further, the content of the random seed in the self-checking mode is a request list base address number, and offsets of two access requests adjacent to the access request currently generated;
the random seed in the non-self-checking mode is accessed by the address and the access content.
Still further, the request list module includes:
a request sending sub-module, configured to receive the random information and obtain a context of the random information; acquiring the random information interaction number to be sent in the request list, and forwarding the random information to the interaction control module, wherein the context comprises a request number and a state machine; the method comprises the steps of,
the request storage submodule is used for registering the random information to obtain the request list; and based on a preset data checking mechanism and a preset overtime checking mechanism, comparing the response information with the random information and the context to obtain the verification result.
Still further, the interaction control module includes:
the interactive transmitting sub-module is used for converting the random information into the access information corresponding to the interface format of the multi-core access subsystem from the request list;
the interaction special channel sub-module is used for converting the random information into the access information corresponding to a preset special interface format;
and the interaction response sub-module is used for receiving the response information from the interface of the access subsystem and forwarding the response information to the request list module.
Still further, the interactive mapping pool module is specifically configured to:
and mapping the request number and the interaction number when the interaction response sub-module receives the response information.
In a second aspect, the present invention further provides a memory access verification method for a multi-emulation environment, where the memory access verification method is used for verifying a multi-core memory access subsystem, and the multi-core memory access verification method includes the following steps:
generating random information containing a memory access request according to the random seed;
caching the random information into a request list;
converting the random information into an information format corresponding to an interface of the multi-core memory access subsystem from the request list to obtain memory access information, and sending the memory access information to the multi-core memory access subsystem; receiving response information after mapping conversion of the multi-core access subsystem corresponding to the access information;
and comparing the response information with the random information, and outputting a verification result.
Further, before the step of generating the random information including the access request according to the random seed, the method further includes the steps of:
determining a memory access verification mode, wherein the memory access verification mode comprises a self-checking mode and a non-self-checking mode, and in the self-checking mode, memory access addresses of different memory access requests generated according to the random seeds are not allowed to overlap;
in the non-self-checking mode, the memory access addresses of the memory access requests generated according to the random seed are allowed to overlap.
In a third aspect, the present invention also provides a computer device comprising: the memory, the processor and the access verification program stored in the memory and capable of being executed in the processor under the multi-simulation environment, wherein the steps in the access verification method in the multi-simulation environment according to any one of the embodiments are realized when the processor executes the access verification program in the multi-simulation environment.
In a fourth aspect, the present invention further provides a computer readable storage medium, where a memory access verification program in a multi-emulation environment is stored, where the memory access verification program in the multi-emulation environment, when executed by a processor, implements the steps in the memory access verification method in the multi-emulation environment according to any one of the above embodiments.
The invention has the beneficial effects that a system capable of carrying out multi-core access verification in a plurality of simulation environments is provided, the requests corresponding to different time sequence scenes of the access subsystem can be generated by configuring different verification modes and parameters, the portability of the system in different simulation environments is improved based on a request list and the realization mode of a subsystem interface, on the other hand, the waveform generation of hardware simulation can be triggered by the verification judgment carried out by the interface, the analysis and the debugging of verification data are facilitated, and the verification coverage rate is improved.
Drawings
FIG. 1 is a schematic diagram of a memory verification system for a multi-emulation environment according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a process of generating a memory request by a random seed of a random generator module in a self-checking mode according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a process of generating a memory request by a random seed of a random generator module in a non-self-checking mode according to an embodiment of the present invention;
FIG. 4 is a schematic logic diagram of a request list module according to an embodiment of the present invention;
FIG. 5 is a logic diagram of an interactive control module according to an embodiment of the present invention;
FIG. 6 is a logic diagram of an interaction map pool module provided by an embodiment of the present invention;
FIG. 7 is a block flow diagram of steps of a memory verification method for a multi-emulation environment provided by an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory access verification system for a multi-emulation environment according to an embodiment of the present invention, in the process of memory access verification, since various timing scenes need to be generated for a multi-core memory access subsystem, so that timing problems on multi-core cache (cache) consistency and resource interlocking problems of different requests are verified, but a self-checking program in the prior art cannot generate different resource competition scenes. Specifically, the access verification system is configured to verify a multi-core access subsystem, and the multi-core access verification system 100 includes:
a random generator module 101, configured to generate random information including a memory access request according to a random seed;
a request list module 102, configured to cache the random information into a request list; comparing the response information with the random information, and outputting a verification result, wherein the response information is sent out by the multi-core access subsystem;
the interaction control module 103 is configured to convert the random information from the request list into access information corresponding to an interface format of the multi-core access subsystem, and send the access information to the multi-core access subsystem; the request list module 102 is further configured to receive response information corresponding to the access information responded by the multi-core access subsystem, and forward the response information to the request list module;
an interaction mapping pool module 104, configured to provide mapping functions for the interaction control module 103 and the request list module 102.
In the random generator module 101, a random Seed (Seed) is used to generate information required by different request timing scenarios by a Linear Feedback Shift Register (LFSR), further, the multi-core access verification system 100 is divided into a self-checking mode (selfcheck) and a non-self-checking mode (non-selfcheck) according to the access verification mode, and the access addresses of the different access requests generated by the random Seed in the self-checking mode are not allowed to overlap, and in the implementation process, the access requests in the self-checking mode are limited in type, for example, store single Byte (Store Byte) and Load Word (Load Word);
the random generator module in the non-self-checking mode allows overlapping according to the memory access address of the memory access request generated by the random seed, and in the implementation process, the memory access request in the non-self-checking mode is only used for realizing the check of request timeout although the type is not limited.
Specifically, please refer to fig. 2 and fig. 3, respectively, fig. 2 and fig. 3 are schematic diagrams of a process of generating access requests by random seeds of the random generator module in a self-checking mode and a non-self-checking mode, wherein the self-checking mode is to input two random seeds, one content is a request list base address number, the other content is offset of two adjacent access requests of the access requests currently generated, and output is a request list number corresponding to all multi-core access channels calculated by an Adder (ALU); the non-self-checking mode is also to input two seeds, wherein one content is an access address, the other content is an access type, the addresses and the type seeds of all multi-core access channels are calculated through an adder, in addition, some configuration parameters can be defined for the access content in the implementation process, and the output in the non-self-checking mode is the addresses and the types of all multi-core access channels subjected to parameter constraint.
Still further, the request list module 102 includes:
a request sending submodule 1021, configured to receive the random information and obtain a context of the random information; acquiring the random information interaction number to be sent in the request list, and forwarding the random information to the interaction control module 103, wherein the context comprises a request number and a state machine; the method comprises the steps of,
a request storage submodule 1022, configured to register the random information to obtain the request list; and based on a preset data checking mechanism and a preset overtime checking mechanism, comparing the response information with the random information and the context to obtain the verification result.
Specifically, referring to fig. 4, fig. 4 is a logic schematic diagram of a request list module provided by an embodiment of the present invention, in the request storage sub-module 1022, each entry corresponding to random information has a state machine (FSM) to maintain a life cycle of each information interaction, and for a self-checking mode, the interaction process is that 4 times of store bytes and then 1 time of load words are accessed for 5 times; and only 1 visit is performed for the non-self-checking mode, if the interaction is completed, the interaction process of carrying other information according to a pre-designed algorithm is continued, and the processing is circularly performed. In practical implementations, the request list module 102 may perform state interaction with a response update (resp update), a storage buffer information (stb info), and a request transmitting module through a crossbar, and output interactive debug information (debug info).
The preset data checking mechanism in the embodiment of the invention is different from the self-checking mode, and for the self-checking mode, the preset data checking mechanism divides a byte sequence into 4 times, selects a machine to send to a random core for storing single bytes in a certain clock period, sends a loading word to the random core after the information of the 4 stored single bytes is written into a first-level data cache, compares the received bytes with the request entry, and outputs the result to a debugging information interface. Such a design is because one byte is in the same cache line, and thus if each core carries different bits of data, it can place a significant test pressure on cache coherency.
For the preset timeout checking mechanism, the non-self-checking mode only interacts once, and only needs to check the timeout condition of the response, and the request timeout checking specifically includes checking whether the response is received after a set number of clock cycles after the request is sent, and writing the request into the first-level data cache after the set number of clock cycles after the request is stored.
Still further, the interaction control module 103 includes:
an interaction emission submodule 1031, configured to convert the random information into the access information corresponding to an interface format of the multi-core access subsystem from the request list;
an interaction special channel submodule 1032, configured to convert the random information into the access information corresponding to a preset special interface format;
an interactive response sub-module 1033, configured to receive the response information from the interface of the access subsystem, and forward the response information to the request list module 102.
Referring to fig. 5, fig. 5 is a logic schematic diagram of an interaction control module provided in an embodiment of the present invention, in the embodiment of the present invention, when converting according to an interface (LSU) format of the multi-core memory subsystem, operations such as out-of-order, delay sending, automatic wake-up, etc. can also be performed in the converted memory information. The preset special interface format may include, but is not limited to, ACP (accelerator coherence), icache (instruction cache), and the like.
Still further, the interactive mapping pool module 104 is specifically configured to:
the mapping of the request number and the interaction number is performed when the interaction response sub-module 1033 receives the response information.
Specifically, referring to fig. 6, fig. 6 is a logic schematic diagram of an interaction mapping pool module provided by an embodiment of the present invention, where the interaction mapping pool module 104 implements three types of operations, that is, obtaining (get), querying (poll), canceling (put), and the obtaining operation is used by the request list module 102 to obtain a corresponding interaction number according to a request number creation mapping (create mapping); the query operation is used for acquiring a request number through an interaction number after the interaction control module 103 receives a ready signal of a corresponding channel of the access subsystem; the cancellation operation is used for acquiring the request number and canceling the mapping of the request number through the interaction number after the interaction control module 103 receives the response of the corresponding channel of the access subsystem (invalidate mapping). In actual implementation, the valid request number corresponding to each interaction may be registered through an additional mapping storage module.
The multi-core access verification system 100 in the embodiment of the present invention may be implemented by adding parameter settings of various functional modules according to needs, for example, including but not limited to:
the capacity of the request list is used for a self-checking mode to meet different cache hit rates, and the larger the capacity is, the lower the hit rate is;
the memory address width range is used for a non-self-checking mode to meet different cache hit rates, and the wider the address width is, the lower the hit rate is;
the multi-core switch can be used for the early-stage function verification or the data self-checking function of a non-cache channel (IO) when only a single core is used for verification of a multi-core access subsystem;
an atomic memory access type (AMO) switch that can generate an atomic memory access type request in a non-self-test mode;
a non-cache way (IO) switch for generating a request associated with the non-cache way;
an accelerator coherency channel (ACP) switch for generating a request associated with the accelerator coherency channel;
an instruction cache channel (icache) switch may generate requests associated with the instruction cache channel in a non-self-checking mode.
The switch related to the log is used for tracking the log, so that the information collection of the request of the problem address in the target access subsystem can be realized, and the later debugging is facilitated.
The invention has the beneficial effects that a system capable of performing multi-core access verification in a plurality of simulation environments is provided, the requests of different time sequence scenes corresponding to the access subsystem can be generated by configuring different verification modes and parameters, the portability of the system in different simulation environments is improved based on the realization mode of a register conversion stage (Register Transfer Level), on the other hand, the waveform generation of hardware simulation can be triggered by the verification judgment performed through a debugging information interface, the analysis and the debugging of verification data are facilitated, and the verification coverage rate is improved.
Example two
The embodiment of the invention also provides a memory verification method for a multi-simulation environment, please refer to fig. 7, fig. 7 is a block flow diagram of steps of the memory verification method for a multi-simulation environment, the memory verification method is used for verifying a multi-core memory subsystem, and the multi-core memory verification method comprises the following steps:
s1, generating random information containing a memory access request according to a random seed;
s2, caching the random information into a request list;
s3, converting the random information into an information format corresponding to an interface of the multi-core access subsystem from the request list to obtain access information, and sending the access information to the multi-core access subsystem; receiving response information after mapping conversion of the multi-core access subsystem corresponding to the access information;
s4, comparing the response information with the random information, and outputting a verification result.
Further, before the step of generating the random information including the access request according to the random seed, the method further includes the steps of:
determining a memory access verification mode, wherein the memory access verification mode comprises a self-checking mode and a non-self-checking mode, and in the self-checking mode, memory access addresses of different memory access requests generated according to the random seeds are not allowed to overlap;
in the non-self-checking mode, the memory access addresses of the memory access requests generated according to the random seed are allowed to overlap.
The access verification method can be implemented based on the access verification system 100 in the above embodiment, and the same technical effects can be achieved, and the description in the above embodiment is omitted here.
Example III
Referring to fig. 8, fig. 8 is a schematic structural diagram of a computer device according to an embodiment of the present invention, where the computer device 200 includes: memory 202, processor 201, and memory access verification program stored on the memory 202 and executable on the processor 201 in a multi-emulation environment.
The processor 201 invokes the memory verification program stored in the memory 202 under the multi-emulation environment, and executes the steps in the memory verification method for the multi-emulation environment provided by the embodiment of the present invention, please refer to fig. 7, specifically including the following steps:
s1, generating random information containing a memory access request according to a random seed;
s2, caching the random information into a request list;
s3, converting the random information into an information format corresponding to an interface of the multi-core access subsystem from the request list to obtain access information, and sending the access information to the multi-core access subsystem; receiving response information after mapping conversion of the multi-core access subsystem corresponding to the access information;
s4, comparing the response information with the random information, and outputting a verification result.
Further, before the step of generating the random information including the access request according to the random seed, the method further includes the steps of:
determining a memory access verification mode, wherein the memory access verification mode comprises a self-checking mode and a non-self-checking mode, and in the self-checking mode, memory access addresses of different memory access requests generated according to the random seeds are not allowed to overlap;
in the non-self-checking mode, the memory access addresses of the memory access requests generated according to the random seed are allowed to overlap.
Further, the content of the random seed in the self-checking mode is a request list base address number, and offsets of two access requests adjacent to the access request currently generated;
the random seed in the non-self-checking mode is accessed by the address and the access content.
The memory 202 may be used to store software programs as well as various data. The memory 202 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data (such as audio data, phonebook, etc.) created according to the use of the handset, etc. In addition, memory 202 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
The processor 201 is a control center of the terminal, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or executing software programs and/or modules stored in the memory 202 and calling data stored in the memory 202, thereby performing overall monitoring of the terminal. The processor 201 may include one or more processing units; preferably, the processor 201 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 201.
The computer device 200 provided in the embodiment of the present invention can implement the steps in the access verification method for multiple simulation environments in the above embodiment, and can implement the same technical effects, and is not described herein again with reference to the description in the above embodiment.
Example IV
The embodiment of the invention also provides a computer readable storage medium, which stores a memory verification program in a multi-simulation environment, and when the memory verification program in the multi-simulation environment is executed by a processor, the memory verification program in the multi-simulation environment realizes each process and step in the memory verification method for the multi-simulation environment provided by the embodiment of the invention, and can realize the same technical effect, so that repetition is avoided and redundant description is omitted.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM) or the like.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
While the embodiments of the present invention have been illustrated and described in connection with the drawings, what is presently considered to be the most practical and preferred embodiments of the invention, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various equivalent modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (7)
1. A memory verification system for a multi-emulation environment, the memory verification system for verifying a multi-core memory subsystem, the memory verification system comprising:
the random generator module is used for generating random information containing access requests according to the random seeds;
the request list module is used for caching the random information into a request list; comparing the response information with the random information, and outputting a verification result, wherein the response information is sent out by the multi-core access subsystem;
the interaction control module is used for converting the random information into access information corresponding to an interface format of the multi-core access subsystem from the request list and sending the access information to the multi-core access subsystem; the multi-core access subsystem is also used for receiving the response information corresponding to the access information and responding to the multi-core access subsystem and forwarding the response information to the request list module;
the interactive mapping pool module is used for providing mapping functions for the interactive control module and the request list module;
wherein the request list module comprises:
a request sending sub-module, configured to receive the random information and obtain a context of the random information; acquiring an interaction number of the random information to be sent in the request list, and forwarding the random information to the interaction control module, wherein the context comprises the request number and a state machine; the method comprises the steps of,
the request storage submodule is used for registering the random information to obtain the request list; based on a preset data checking mechanism and a preset overtime checking mechanism, the response information is subjected to data comparison with the random information and the context to obtain the verification result;
the interaction control module comprises:
the interactive transmitting sub-module is used for converting the random information into access information corresponding to an interface format of the multi-core access sub-system from the request list;
the interaction special channel sub-module is used for converting the random information into access information corresponding to a preset special interface format;
the interaction response sub-module is used for receiving the response information from the interface of the multi-core access subsystem and forwarding the response information to the request list module;
the interactive mapping pool module is specifically configured to:
and mapping the request number and the interaction number when the interaction response sub-module receives the response information.
2. The memory verification system for a multi-emulation environment of claim 1, wherein the memory verification system for a multi-emulation environment is divided into a self-test mode and a non-self-test mode according to a memory verification mode, wherein:
the random generator module in the self-checking mode does not allow overlapping of access addresses of different access requests generated by the random seed;
the random generator module in the non-self-checking mode allows overlapping according to the memory access address of the memory access request generated by the random seed.
3. The memory verification system for a multiple emulation environment of claim 2, wherein the contents of said random seed in said self-test mode are a request list base address number, an offset of two memory requests adjacent to said memory request currently being generated;
the random seed in the non-self-checking mode is accessed by the address and the access content.
4. The access verification method for the multi-simulation environment is used for verifying a multi-core access subsystem and is characterized by comprising the following steps of:
generating random information containing a memory access request according to the random seed;
caching the random information into a request list;
converting the random information into an information format corresponding to an interface of the multi-core memory access subsystem from the request list to obtain memory access information, and sending the memory access information to the multi-core memory access subsystem; receiving response information corresponding to the access information, which is responded by the multi-core access subsystem;
comparing the response information with the random information, and outputting a verification result;
the step of comparing the response information with the random information and outputting a verification result comprises the following steps:
acquiring a context of the random information and an interaction number of the random information to be sent in the request list, wherein the context comprises a request number and a state machine, and comparing the response information with the random information and the context based on a preset data checking mechanism and a preset timeout checking mechanism to obtain the verification result;
converting the random information into an information format corresponding to an interface of the multi-core memory access subsystem from the request list to obtain memory access information, and sending the memory access information to the multi-core memory access subsystem; the step of receiving the response information corresponding to the access information responded by the multi-core access subsystem specifically comprises the following steps:
and converting the random information into access information corresponding to an interface format of the multi-core access subsystem from the request list, converting the random information into access information corresponding to a preset special interface format, receiving the response information from the interface of the multi-core access subsystem, and mapping the request number and the interaction number when receiving the response information.
5. The memory verification method for a multi-emulation environment of claim 4, wherein prior to said step of generating random information comprising a memory request based on a random seed, further comprising the step of:
determining a memory access verification mode, wherein the memory access verification mode comprises a self-checking mode and a non-self-checking mode, and in the self-checking mode, memory access addresses of different memory access requests generated according to the random seeds are not allowed to overlap;
in the non-self-checking mode, the memory access addresses of the memory access requests generated according to the random seed are allowed to overlap.
6. A computer device, comprising: memory, processor and memory verification program stored on said memory and executable on said processor in a multi-emulation environment, said processor implementing the steps in the memory verification method of a multi-emulation environment as claimed in any one of claims 4-5 when executing said memory verification program in said multi-emulation environment.
7. A computer readable storage medium, wherein a memory verification program in a multi-emulation environment is stored on the computer readable storage medium, and the memory verification program in the multi-emulation environment implements the steps in the memory verification method in the multi-emulation environment according to any one of claims 4 to 5 when executed by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310704831.6A CN116431422B (en) | 2023-06-14 | 2023-06-14 | Access verification system, method and related equipment for multi-simulation environment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310704831.6A CN116431422B (en) | 2023-06-14 | 2023-06-14 | Access verification system, method and related equipment for multi-simulation environment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116431422A CN116431422A (en) | 2023-07-14 |
| CN116431422B true CN116431422B (en) | 2023-09-29 |
Family
ID=87091190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310704831.6A Active CN116431422B (en) | 2023-06-14 | 2023-06-14 | Access verification system, method and related equipment for multi-simulation environment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116431422B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101446987A (en) * | 2007-11-27 | 2009-06-03 | 上海高性能集成电路设计中心 | Consistency physical verification device of multicore processor Cache |
| CN112382321A (en) * | 2020-11-12 | 2021-02-19 | 海光信息技术股份有限公司 | Refreshing method of dynamic random access memory, memory controller and electronic device |
| CN114168200A (en) * | 2022-02-14 | 2022-03-11 | 北京微核芯科技有限公司 | System and method for verifying memory access consistency of multi-core processor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7904286B2 (en) * | 2007-09-14 | 2011-03-08 | International Business Machines Corporation | Method and apparatus for scheduling test vectors in a multiple core integrated circuit |
| GB2565338B (en) * | 2017-08-10 | 2020-06-03 | Mips Tech Llc | Fault detecting and fault tolerant multi-threaded processors |
| US11099635B2 (en) * | 2019-09-27 | 2021-08-24 | Apple Inc. | Blow event detection and mode switching with an electronic device |
-
2023
- 2023-06-14 CN CN202310704831.6A patent/CN116431422B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101446987A (en) * | 2007-11-27 | 2009-06-03 | 上海高性能集成电路设计中心 | Consistency physical verification device of multicore processor Cache |
| CN112382321A (en) * | 2020-11-12 | 2021-02-19 | 海光信息技术股份有限公司 | Refreshing method of dynamic random access memory, memory controller and electronic device |
| CN114168200A (en) * | 2022-02-14 | 2022-03-11 | 北京微核芯科技有限公司 | System and method for verifying memory access consistency of multi-core processor |
Non-Patent Citations (1)
| Title |
|---|
| 基于堆栈式多核处理器的嵌入式系统的研究与实现;何凯成;《中国优秀硕士学位论文全文数据库》;I137-28 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116431422A (en) | 2023-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111625452B (en) | Flow playback method and system | |
| CN110249307A (en) | System and method for executing primary contract on block chain | |
| WO2020233369A1 (en) | Method for improving software integration system on basis of simulated port, and related device | |
| CN107635027B (en) | Domain name resolution method, medium, device and computing equipment | |
| CN114580344B (en) | Test excitation generation method, verification system and related equipment | |
| CN103580937A (en) | Web service simulating method and system and service agent system thereof | |
| CN107832329A (en) | Page resource acquisition methods and terminal device | |
| KR101719500B1 (en) | Acceleration based on cached flows | |
| CN111858296B (en) | Interface testing method, device, equipment and storage medium | |
| CN108595331B (en) | Asynchronous interface testing method, medium, device and computing equipment | |
| CN111382044B (en) | Positioning method and positioning device for performance bottleneck, electronic equipment and storage medium | |
| CN111064804B (en) | Network access method and device | |
| US11294740B2 (en) | Event to serverless function workflow instance mapping mechanism | |
| CN114238948A (en) | Application program detection method and device, electronic equipment and storage medium | |
| CN113204345A (en) | Page generation method and device, electronic equipment and storage medium | |
| CN113965543B (en) | Access method, device and storage medium of application server | |
| CN104731564A (en) | Generation method and device for system interface call records | |
| CN116431422B (en) | Access verification system, method and related equipment for multi-simulation environment | |
| CN106502707B (en) | Code generation method and device | |
| CN114489622A (en) | Js application, electronic device, and storage medium | |
| CN112416747A (en) | Test case execution method, device, equipment and medium | |
| CN112256564B (en) | Application program running method and device and electronic equipment | |
| CN109254858A (en) | Data sharing method, device, equipment and the storage medium of active window | |
| CN115828262A (en) | Open source component vulnerability scanning method, device, equipment and storage medium | |
| CN111228815B (en) | Method, apparatus, storage medium and system for processing configuration table of game |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |